CN112543025A - High-speed serial AD sampling and data processing system and method based on matrixing - Google Patents
High-speed serial AD sampling and data processing system and method based on matrixing Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention discloses a high-speed serial AD sampling and data processing system and a method based on matrixing.A system reference clock is adopted as a sampling reference clock of an ultra-low jitter clock generator and a reference clock of FGPA, and the ultra-low jitter clock generator generates a sampling clock according to the sampling reference clock; the A/DC chip samples analog signals, converts the sampled analog signals into sampled digital signals and outputs serial multi-path sampled digital signals to the FPGA; the FPGA receives and processes the sampling data stream and outputs a parallel sampling data stream; the QDR III memory receives and stores a sample data stream. The invention solves the problems of receiving, storing, transmitting, processing and the like of mass sampling data, and greatly reduces the cost, space and power consumption required by arrayed, high-carrier, high-bandwidth and intermediate-frequency digital products.
Description
Technical Field
The invention relates to the field of data sampling, in particular to a high-speed serial AD sampling and data processing system and method based on matrixing.
Technical Field
In the scheme of array, high carrier and high bandwidth intermediate frequency digital products, the adopted integrated multipath high bandwidth, high sampling rate and high precision intermediate frequency sampling A/DC chips all adopt high speed serial digital output interfaces, and intermediate frequency sampling data send digital intermediate frequency signals to CPU chips such as FPGA with high speed serial interfaces at the rear end through the high speed serial buses. When the front-end intermediate frequency signals are only a few paths, the CPU at the rear end can receive the intermediate frequency digital signals through the high-speed serial interface and can not cause data loss without being processed by a special method, and when the front-end intermediate frequency signals are hundreds, if a simple one or two AD/C chips are also adopted to be accessed into an FPGA scheme through the high-speed serial data interface, a plurality of FPGAs are adopted, so that the cost of the whole intermediate frequency signal acquisition scheme is high, and the problems of component layout space, power consumption and the like are also caused; and if the FPGA with higher performance is properly adopted, a single FPGA can access more AD/C chips, but if the output data of the AD/C chips is not specially processed, the data cannot be timely received, stored, transmitted and processed by a CPU, and the failure of the whole signal processing scheme is caused. Therefore, when the FPGA with higher performance is adopted, the single FPGA can be connected with more AD/C chips, and the problems of receiving, storing, transmitting, processing and the like of mass sampling data are solved by adopting a proper method, so that the cost, the space and the power consumption required by the arrayed, high-carrier, high-bandwidth and intermediate-frequency digitalized products can be greatly reduced.
Disclosure of Invention
In order to solve the problems of receiving, storing, transmitting and processing mass sampling data in the background technology, the invention provides a high-speed serial AD sampling and data processing system and method based on matrixing.
The high-speed serial A/DC sampling and data processing system based on matrixing comprises a system reference clock, an ultra-low jitter clock generator, a plurality of A/DC chips, an FPGA and a QDR III memory;
the system reference clock is used as a sampling reference clock of an ultra-low jitter clock generator and a reference clock of the FPGA;
the ultra-low jitter clock generator generates a sampling clock of the A/DC chip according to a sampling reference clock;
the FPGA comprises a plurality of JESD204B receiving and processing cores, a multi-frame parallel data pipeline n-order sorting unit, a high-speed data memory interface group and a stepping phase clock management unit;
the step phase clock management unit generates a system working clock of the FPGA and a system reference clock of the A/DC chip according to the reference clock of the FPGA;
the A/DC chip is used for sampling an analog signal and converting the sampled analog signal into a sampled digital signal; and for outputting a plurality of high-speed serial sample data streams conforming to the JESD204B protocol;
the JESD204B receiving processing core is configured to receive the sample data stream, and perform deserialization, 8B/10B decoding, data frame/lane alignment, byte detection, and descrambling on the sample data stream; and a synchronous clock for outputting the parallel sampled data stream and data;
the n-order sequencing unit of the multi-frame parallel data assembly line is used for receiving a sampling data stream and a data synchronous clock, and grouping and performing running sequence on the sampling data stream; outputting the sampling data stream to the QDR III memory or reading the sampling data stream in the QDR III memory through the high-speed data memory interface group;
and the QDR III memory is used for receiving and storing the sampled data stream which is finished by grouping and pipelining sequencing.
The working principle is as follows: the scheme adopts a system reference clock, an ultra-low jitter clock generator, a plurality of A/DC chips, an FPGA and a QDR III memory; the system reference clock is used as a sampling reference clock of the ultra-low jitter clock generator and a reference clock of the FPGA; the ultra-low jitter clock generator generates a sampling clock of the A/DC chips according to the sampling reference clock, the A/DC chips are connected into an FPGA, the A/DC chips sample analog signals and convert the sampled analog signals into sampled digital signals, the sampled digital signals are transmitted to the FPGA in a sampled data stream mode, and the FPGA processes the sampled data stream and then outputs the sampled data stream to a QDR III memory for storage.
Further, the system reference clock is generated by a clock source.
Further, the a/DC chips correspond to the JESD204B receiving processing cores one to one.
Furthermore, the A/DC chip adopts an AD9694 chip, the AD9694 chip is 14bit, 4 paths of analog signal sampling A/DC chips are provided, the analog input bandwidth of each path is 500MSPS, 4 high-speed serial digital coding lane output sampling data conforming to the JESD204B subclass 1 protocol are provided, and the serial data rate of each lane is 15 Gbps.
Furthermore, the sampling clock and the system reference clock of the A/DC chip are homologous and synchronous, and the system reference clock of the A/DC chip is used for adjusting the time of the sampling data stream reaching the FPGA by adjusting the system reference clock through another group of ultra-low jitter clock generators.
The high-speed serial A/DC sampling and data processing technology based on matrixing comprises the following steps:
s1, taking the system reference clock as a sampling reference clock and an FPGA reference clock of the ultra-low jitter clock generator;
s2, the ultra-low jitter clock generator generates a sampling clock according to the sampling reference clock;
the S3 and AD9694 chips sample analog signals according to a sampling clock, and the AD9694 chips convert the sampled analog signals into sampled data signals;
the S4 and AD9694 chips output high-speed serial sampling data streams conforming to the JESD204B protocol, and the sampling data streams are adjusted to reach the FPGA by adjusting a system reference clock;
s5, receiving and processing core JESD204B of FPGA, for receiving sampling data stream, and performing deserialization, 8B/10B decoding, data frame/lane alignment, byte detection and descrambling on the sampling data stream;
s6, JESD204B of FPGA receives and processes the sampling data flow and data synchronization clock that the kernel outputs the parallelism to the multiframe parallel data pipeline n rank sequencing unit of FPGA;
s7, receiving the sampled data stream by a multi-frame parallel data pipeline n-order sequencing unit of the FPGA, and grouping and performing pipeline sequencing on the sampled data stream according to the number of high-speed memory interfaces of the FPGA and the data bandwidth thereof;
s8, outputting the sampling data stream to a QDR III memory through a high-speed memory interface by a multi-frame parallel data pipeline n-order sorting unit of the FPGA;
s9, QDR iii memory buffers the sample data stream.
Furthermore, a stepping phase clock management unit in the FPGA generates a system working clock of the FPGA and a system reference clock of the AD9694 chip, and the system reference clock is used as a reference clock of the ultra-low jitter sampling clock generator to generate a sampling clock of the AD9694 chip.
Furthermore, the rule of mapping the multi-frame parallel data into n-level data flow is to compare the data synchronization clock phases in one working clock cycle
And a reference&Phase of working clock
Is given by the formula
Further, the sample data stream buffered in the QDR iii memory is read by an FPGA or other CPU having a high-speed QDR data interface.
A signal acquisition card based on a matrixing high-speed serial A/DC sampling and data processing system and a method thereof adopts a global antenna array and a channel array to output an array analog intermediate frequency signal to an intermediate frequency signal acquisition card, and the intermediate frequency signal acquisition card adopts the matrixing high-speed serial A/DC sampling and data processing system to acquire and buffer massive intermediate frequency digital signals and transmits the signals to a back-end FPGA or CPU array for processing.
Through the implementation of the scheme, the invention has the beneficial effects that: the FPGA with higher performance is adopted, a single FPGA can be connected with more AD/C chips, two clocks are adopted by the A/DC chip, a multi-frame parallel data pipeline n-order sorting unit of the FPGA is used for grouping and sorting the sampled data streams, and the QDR III memory with separate input and output interfaces and higher data transmission bandwidth is used for solving the problems of receiving, storing, transmitting, processing and the like of mass sampled data.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a block diagram of an implementation of the present invention;
FIG. 2 is a block diagram of an n-order sequencing unit implementation of the multi-frame parallel data pipeline of the present invention;
FIG. 3 is a schematic diagram of an application of the signal acquisition card of the present invention.
Detailed Description
The embodiments of the present invention will be described with reference to the accompanying drawings, and the exemplary embodiments and descriptions thereof are only for the purpose of illustrating the present invention and are not to be construed as limiting the present invention.
Example 1
According to fig. 1 and fig. 2, the a/DC chip adopts AD9694, the AD9694 is a 14-bit 4-path analog signal sampling a/DC chip, the analog input bandwidth of each path can reach 1.4GHz, the sampling rate can reach 500MSPS, 4 high-speed serial digital coding lane output sampling data conforming to JESD204B subclass 1 protocol are used, and the serial data rate of each lane is 15 Gbps. When an analog signal is sampled by 300Mhz, each sampling point is represented by 14 bits, and after the analog signal is transmitted to a rear-end FPGA, the analog signal is actually represented by 2Byte, namely 16 bits, the sampling data volume of one path of analog signal is 300 multiplied by 16Mbit/s, the sampling data volume of 4 paths of analog signals is 300 multiplied by 16 multiplied by 4Mbit/s, namely the data volume generated by one AD9694 per second is 300 multiplied by 16 multiplied by 4Mbit/s, if one FPGA is connected with N AD9694, the data generated per second is 300 multiplied by 16 multiplied by 4 multiplied by N Mbit, the sampling data need to reach the FPGA at a controllable moment, therefore, a clock source is adopted to generate system reference time, and the system reference time is used as a sampling reference clock of an ultra-low jitter clock generator and a reference clock of the FPGA; the ultra-low jitter clock generator generates a sampling clock of the AD9694 chip according to a sampling reference clock, and the reference clock of the FPGA generates a system working clock of the FPGA and a system reference clock of the AD9694 chip through the stepping phase clock management unit. The sampling rate can be controlled by adopting the sampling clock of the AD9694 chip, and the time of the sampling data stream reaching the FPGA can be adjusted by adjusting the system reference clock of the AD9694 chip, so that the controllability of the sampling data stream is realized.
After high-speed serial digital sampling data which are output by an AD9694 chip and accord with a JESD204B protocol are input into an FPGA, the JESD204B of the FPGA receives, processes and checks the data to perform operations such as deserialization, 8B/10B decoding, data frame/lane alignment, byte detection and descrambling and the like, and outputs parallel sampling data streams and data synchronization clocks to a multi-frame parallel data pipeline n-order sequencing unit. And the n-order sorting unit of the multi-frame parallel data pipeline performs grouping and pipeline sorting on the data which is received, processed, checked and output by the JESD204B according to the number of high-speed memory interfaces of the FPGA and the data bandwidth thereof. The rule for mapping multi-frame parallel data into n-level data flow is to compare the data synchronous clock fs and the reference in one working clock period&Phase of the operating clock phase fw
Is given by the formula
(taking an integer).
The sampled data stream needs to be buffered before being read by a CPU at the later stage, and a very large storage space is needed, so that a QDR III memory is adopted. After the data pipeline is arranged, the data is output to the QDR III memory through the high-speed memory interface. The input interface and the output interface of the QDR III memory are separated, and the data transmission bandwidth is twice of that of the DDR, so that the QDR III memory can be selected to access data more quickly; the data stored in the QDR iii memory can be read by an FPGA or other CPU with a high speed QDR data interface.
Example 2
As shown in fig. 3, based on embodiment 1, the system and method for high-speed serial a/DC sampling and data processing based on matrixing implements a signal acquisition card, outputs an array analog intermediate frequency signal to an intermediate frequency signal acquisition card through a spherical antenna array and a channel array, and the intermediate frequency signal acquisition card acquires and caches a large amount of intermediate frequency digital signals by using the system and method for high-speed serial a/DC sampling and data processing based on matrixing and transmits the signals to a rear-end FPGA or CPU array for processing.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The system is characterized by comprising a system reference clock, an ultra-low jitter clock generator, a plurality of A/DC chips, an FPGA and a QDR III memory;
the system reference clock is used as a sampling reference clock of an ultra-low jitter clock generator and a reference clock of the FPGA;
the ultra-low jitter clock generator generates a sampling clock of the A/DC chip according to a sampling reference clock;
the FPGA comprises a plurality of JESD204B receiving and processing cores, a multi-frame parallel data pipeline n-order sorting unit, a high-speed data memory interface group and a stepping phase clock management unit;
the step phase clock management unit generates a system working clock of the FPGA and a system reference clock of the A/DC chip according to the reference clock of the FPGA;
the A/DC chip is used for sampling an analog signal and converting the sampled analog signal into a sampled digital signal; and for outputting a plurality of high-speed serial sample data streams conforming to the JESD204B protocol;
the JESD204B receiving processing core is configured to receive the sample data stream, and perform deserialization, 8B/10B decoding, data frame/lane alignment, byte detection, and descrambling on the sample data stream; and a synchronous clock for outputting the parallel sampled data stream and data;
the n-order sequencing unit of the multi-frame parallel data assembly line is used for receiving a sampling data stream and a data synchronous clock, and grouping and performing running sequence on the sampling data stream; outputting the sampling data stream to the QDR III memory or reading the sampling data stream in the QDR III memory through the high-speed data memory interface group;
and the QDR III memory is used for receiving and storing the sampled data stream which is finished by grouping and pipelining sequencing.
2. The matrixing-based high-speed serial a/DC sampling and data processing system of claim 1, wherein: the system reference clock is generated by a clock source.
3. The matrixing-based high-speed serial a/DC sampling and data processing system of claim 1, wherein: the A/DC chip and the JESD204B receiving processing core are in one-to-one correspondence.
4. The matrixing-based high-speed serial a/DC sampling and data processing system of claim 1, wherein: the A/DC chip adopts an AD9694 chip, the AD9694 chip is 14bit, 4 paths of analog signals sample the A/DC chip, the analog input bandwidth of each path is 500MSPS, 4 high-speed serial digital coding lane output sampling data conforming to JESD204B subclass 1 protocol are provided, and the serial data rate of each lane is 15 Gbps.
5. The matrixing-based high-speed serial a/DC sampling and data processing system of claim 1, wherein: the sampling clock and the system reference clock of the A/DC chip are homologous and synchronous, and the system reference clock of the A/DC chip adjusts the time of the sampling data stream reaching the FPGA by adjusting the system reference clock through another group of ultra-low jitter clock generators.
6. The high-speed serial A/DC sampling and data processing method based on matrixing is characterized in that: the method is applied to the system as claimed in any one of claims 1 to 5, and comprises the following steps:
s1, taking the system reference clock as a sampling reference clock and an FPGA reference clock of the ultra-low jitter clock generator;
s2, the ultra-low jitter clock generator generates a sampling clock according to the sampling reference clock;
the S3 and AD9694 chips sample analog signals according to a sampling clock, and the AD9694 chips convert the sampled analog signals into sampled data signals;
the S4 and AD9694 chips output high-speed serial sampling data streams conforming to the JESD204B protocol, and the sampling data streams are adjusted to reach the FPGA by adjusting a system reference clock;
s5, receiving and processing core JESD204B of FPGA, for receiving sampling data stream, and performing deserialization, 8B/10B decoding, data frame/lane alignment, byte detection and descrambling on the sampling data stream;
s6, JESD204B of FPGA receives and processes the sampling data flow and data synchronization clock that the kernel outputs the parallelism to the multiframe parallel data pipeline n rank sequencing unit of FPGA;
s7, receiving the sampled data stream by a multi-frame parallel data pipeline n-order sequencing unit of the FPGA, and grouping and performing pipeline sequencing on the sampled data stream according to the number of high-speed memory interfaces of the FPGA and the data bandwidth thereof;
s8, outputting the sampling data stream to a QDR III memory through a high-speed memory interface by a multi-frame parallel data pipeline n-order sorting unit of the FPGA;
s9, QDR iii memory buffers the sample data stream.
7. The matrixing-based high-speed serial A/DC sampling and data processing method of claim 6, wherein: the stepping phase clock management unit in the FPGA generates a system working clock of the FPGA and a system reference clock of the AD9694 chip, and the system reference clock is used as a reference clock of the ultra-low jitter sampling clock generator to generate a sampling clock of the AD9694 chip.
8. The matrixing-based high-speed serialization of claim 6The A/DC sampling and data processing method is characterized in that: the rule of mapping the multi-frame parallel data into n-level data flow is to compare the phase of the data synchronous clock in one working clock period
And a reference&Phase of working clock
Is given by the formula
9. The matrixing-based high-speed serial A/DC sampling and data processing method of claim 6, wherein: and the sampling data stream cached in the QDR III memory is read by an FPGA or a CPU with a high-speed QDR data interface.
10. The signal acquisition card based on the high-speed serial A/DC sampling and data processing of matrixing, its characterized in that: the signal acquisition card is applied to the system according to any one of claims 1 to 5, an array analog intermediate frequency signal is output by adopting a global antenna array and a channel array, the array analog intermediate frequency signal is received by the intermediate frequency signal acquisition card, and a high-speed serial A/DC sampling and data processing system based on matrixing is applied to the intermediate frequency signal acquisition card, so that a large amount of intermediate frequency digital signals are acquired and buffered, and are transmitted to an FPGA or CPU array for processing.
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