CN115102682B - ADC automatic synchronization method and device for ultrasonic system - Google Patents
ADC automatic synchronization method and device for ultrasonic system Download PDFInfo
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- CN115102682B CN115102682B CN202210690500.7A CN202210690500A CN115102682B CN 115102682 B CN115102682 B CN 115102682B CN 202210690500 A CN202210690500 A CN 202210690500A CN 115102682 B CN115102682 B CN 115102682B
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000002604 ultrasonography Methods 0.000 claims description 16
- 230000001360 synchronised effect Effects 0.000 claims description 10
- 230000000737 periodic effect Effects 0.000 claims description 6
- 238000004590 computer program Methods 0.000 claims description 4
- 238000005070 sampling Methods 0.000 abstract description 4
- 239000000872 buffer Substances 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 7
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- 230000005540 biological transmission Effects 0.000 description 2
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- 238000012423 maintenance Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
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Abstract
The invention discloses an automatic ADC synchronization method and equipment suitable for an ultrasonic system, wherein the method comprises a clock chip, an ADC and a field programmable gate array FPGA, the clock chip is used for respectively generating a homologous clock for the ADC and the FPGA, a JESD204B link is adopted between the ADC and the FPGA, the JESD204B link simultaneously uses a timing reference signal sysref and a synchronization signal sync for carrying out link synchronization, and the timing reference signal sysref and the synchronization signal sync are both generated by the FPGA and transmitted to the ADC. The method of the invention not only greatly reduces the number of clock buffers, but also reduces the area of the board card and the wiring difficulty of the PCB, greatly improves the cost, the resource, the flexibility and the anti-interference capability, and simultaneously meets the basic requirement of the ultrasonic equipment on the ADC stable sampling function.
Description
Technical Field
The invention belongs to the field of high-speed interface design, and particularly relates to an automatic ADC synchronization method and device for an ultrasonic system.
Background
JESD204B is a novel data converter ADC/DAC data transmission interface based on a high-speed serial communication technology SERDES. With the continuous increase of the sampling rate of the ADC/DAC, the throughput of data is also larger and larger, and for the ADC/DAC with the sampling rate above 500MSPS, the throughput rate of data is often tens of G, but the design requirements are difficult to meet by adopting the conventional CMOS and LVDS interfaces, so the JESD204B has been generated. Compared with the traditional CMOS and LVDS interfaces, the JESD204B interface has the advantages of high integration level, low power consumption, fewer pins and the like, but also introduces the defect of complex clock structure. As shown in fig. 1, in the conventional JESD204B interface design, the reference clock and the timing reference signal sysref are usually generated by an external clock chip and then sent to an analog-to-digital converter (ADC) and a Field Programmable Gate Array (FPGA), respectively, and only one pair of JESD204B devices needs 4 clock signals. A complete ultrasound system often includes multiple external ADCs (JESD 204B transmitters), and as the requirements for the integration of the ultrasound system become higher, a JESD204B design method capable of saving hardware clock resources is urgently needed. Due to different environment temperatures, when the ultrasonic equipment is started, the establishment and maintenance time of sysref is not satisfied due to temperature drift, so that the risk of JESD204B link synchronization failure is caused, a great hidden danger is brought to the functional stability of the ultrasonic equipment, and a method capable of dynamically adjusting the phase of the sysref is urgently needed.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an automatic ADC synchronization method for an ultrasonic system, which can save hardware clock resources and solve the influence of temperature drift on JESD204B link synchronization during power-on the premise of meeting the functional requirements of the ultrasonic system.
In order to solve the technical problems, the invention adopts the following technical scheme: an automatic ADC synchronization method for an ultrasonic system mainly comprises a clock chip, an ADC and an FPGA on hardware.
The clock chip is used for respectively generating homologous clocks for the ADC and the FPGA, a link of JESD204B is adopted between the ADC and the FPGA, the link of JESD204B simultaneously uses a timing reference signal sysref and a synchronous signal sync for carrying out link synchronization, and the timing reference signal sysref and the synchronous signal sync are both generated by the FPGA and transmitted to the ADC.
Further, the clock cycles to the FPGA are integer multiples of the clock cycles to the ADC.
Further, phase adjustment of sysref and the reference clock of the ADC is achieved by ODELAYE 3.
Further, the phase adjustment method includes the following steps. Step 1: after the ultrasonic system is powered on, the FPGA and the ADC are reset, the delay value of the ODELAYE3 is set to 255 in the reset stage, and the delay mode of the ODELAYE3 is a COUNT mode.
Step 2: after the reset is completed, a sysref_generate module in the FPGA is enabled to start generating a sysref, a sync is taken as a mark signal of a link synchronization state, the sync is 1 to indicate that the link synchronization is successful, and the sync is 0 to indicate that the link synchronization is failed. The sysref generated by the sysref_generate module enters the sysref_shift module, and the sysref_shift module can adjust the delay value of the ODELAYE3 according to the synchronous state of the current link, so as to adjust the phase relation between the sysref and the device clock.
Step 3: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is 0, if so, setting the delay value to 256, entering step 4, if not, subtracting 1 from the delay value, and repeating step 3.
Step 4: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is equal to 512, if so, entering step 5, otherwise, adding 1 to the delay value, and repeating step 4.
Step 5: the delay value is maintained and the enable signal of the sysref_generate module is turned off, and sysref is not generated.
Furthermore, the sysref_shift module is preset with an adjustment interval, in each adjustment interval, the sysref_shift module detects the synchronization state of the link, if the link synchronization is successful, the delay value is maintained and no adjustment is performed any more, and if the link synchronization is failed, the delay value adjustment is continued.
Further, the adjustment interval of the sysref_shift module is 0.5ms to 2ms.
Further, the sysref is a configurable signal, which can be configured to generate only one pulse when powered up, or can be configured as a controlled periodic signal, and the sysref and the device clock are homologous signals.
Further, when the sysref is a controlled periodic signal, the period of the sysref is an integer multiple of the local multiframe counter LMFC. Lmfc=k×f×frame clock period, K is the number of frames included in the multiframe, and F is the number of bytes in the frame data.
The invention also discloses an ADC automatic synchronization device for the ultrasonic system, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method when executing the computer program.
In summary, the method of the invention is suitable for desk ultrasound, portable ultrasound and palm ultrasound devices. Through innovative optimization of the ADC synchronous circuit, the cost and the anti-interference capability are greatly improved, and the stability requirement of the system on an ADC interface is met. The method reduces the number of clocks required by hardware to be half of that of the original clocks, not only greatly reduces the number of clock buffers, but also reduces the area of a board card and the wiring difficulty of a PCB, greatly improves the cost, resources, flexibility and anti-interference capability, and simultaneously meets the basic requirement of ultrasonic equipment on the stable sampling function of an ADC.
The timing reference signal sysref is generated by the FPGA and used for JESD204B link synchronization between the FPGA and the ADC, and the establishment and maintenance time between the sysref and the device clock can be ensured to be met by the design constraint of the reference clock device clock of the FPGA and the ADC, so that the JESD204B link can complete synchronization.
Considering the influence of temperature drift on circuit synchronization time sequence, when equipment is started in different temperature environments, the FPGA automatically adjusts the phase relation between the output synchronization signal and the clock, thereby meeting the requirement of establishing and maintaining time between the reference signal sysref of the ADC and the reference clock and solving the problem of JESD204B link synchronization failure caused by temperature drift of ultrasonic equipment in different temperature environments.
Drawings
FIG. 1 is a schematic diagram of a conventional JESD204B clock design.
Fig. 2 is a clock design schematic diagram of an ADC auto-synchronization method for an ultrasound system according to an embodiment of the invention.
Fig. 3 is a schematic diagram of adjusting the phase relationship of sysref and device clock for an ADC auto-synchronization method for an ultrasound system according to an embodiment of the invention.
Fig. 4 is a schematic diagram of temperature drift clock offset and phase adjustment range of an ADC auto-synchronization method for an ultrasound system according to an embodiment of the invention.
Detailed Description
The patent of the invention is further described below with reference to the accompanying drawings and examples.
In embodiment 1, referring to fig. 2, the present embodiment provides an automatic synchronization method for an ADC of an ultrasound system, in which the ADC and a device clock of an FPGA are provided by the same clock chip, the transmission direction of data in a link of a JESD204B is from the ADC to the FPGA, the JESD204B uses sysref and a sync signal to perform link synchronization at the same time, and the sysref and the sync are generated by the FPGA and transmitted to the ADC through physical wires.
The device clock period of the FPGA is an integer multiple of the device clock period of the ADC.
sysref is a configurable signal, which may be a pulse generated only when powered up, or a controlled periodic signal, and sysref and device clock are homologous signals. When sysref is a controlled periodic signal, the period of sysref is an integer multiple of the local multiframe counter LMFC, where lmfc=k×f×frame clock period, K is the number of frames contained in the multiframe, and F is the number of bytes in the frame data.
The phase relationship between sysref and device clock can be automatically adjusted according to the current system state, and when JESD204B link synchronization is completed or the adjustment range is exceeded, the current delay value is maintained, and the generation of sysref is stopped. The adjustment range of the ODELAYE3 is generally not more than 1.25ns, and the clock offset caused by the temperature drift is generally below 500ps, the phase adjustment range of the ODELAYE3 is sufficient to cope with the influence of the temperature drift, and the phase relationship is shown in fig. 4.
According to JESD204B protocol, when the receiving end detects 4 continuous/K28.5/characters, the sync will be pulled high, so the sync is used as the mark signal of the link synchronization state, and the embodiment obtains the synchronization state of the current link of the device according to the sync state, so that the phase adjustment can be effectively performed, and the automatic synchronization of the link is realized.
Referring to fig. 3, the specific steps for adjusting the phase relationship between sysref and device clock include:
step 1: after the ultrasonic system is powered on, the FPGA and the ADC are reset, the delay value of the ODELAYE3 is set to 255 in the reset stage, and the delay mode of the ODELAYE3 is a COUNT mode.
Step 2: after the reset is completed, a sysref_generate module in the FPGA is enabled to start generating a sysref, and a sync of 1 indicates successful link synchronization and a sync of 0 indicates failure link synchronization. The sysref generated by the sysref_generate module enters the sysref_shift module, and the sysref_shift module can adjust the delay value of the ODELAYE3 according to the synchronous state of the current link, so as to adjust the phase relation between the sysref and the device clock. The adjustment interval of the sysref_shift module is 1ms, and in each adjustment interval, the sysref_shift module detects the synchronous state of the link, if the link is successful in synchronization, the delay value is kept and no adjustment is performed any more, and if the link is failed in synchronization, the delay value adjustment is continued.
Step 3: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is 0, if so, setting the delay value to 256, entering step 4, if not, subtracting 1 from the delay value, and repeating step 3.
Step 4: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is equal to 512, if so, entering step 5, otherwise, adding 1 to the delay value, and repeating step 4.
Step 5: the delay value is maintained and the enable signal of the sysref_generate module is turned off, and sysref is not generated.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present patent are intended to be included within the scope of the present patent claims.
Claims (9)
1. An automatic synchronization method of an ADC (analog-to-digital converter) for an ultrasonic system comprises a clock chip, an ADC (analog-to-digital converter) and a field programmable gate array FPGA, and is characterized in that: the clock chip is used for respectively generating homologous clocks for the ADC and the FPGA, a JESD204B link is adopted between the ADC and the FPGA, the JESD204B link simultaneously uses a timing reference signal sysref and a synchronous signal sync for carrying out link synchronization, and the timing reference signal sysref and the synchronous signal sync are both generated by the FPGA and transmitted to the ADC;
the method comprises the following steps:
step 1: after the ultrasonic system is powered on, resetting the FPGA and the ADC, and setting the delay value of the ODELAYE3 to 255 in a resetting stage;
step 2: after the reset is completed, a sysref_generate module in the FPGA is enabled to start to generate a timing reference signal sysref; taking a synchronization signal sync as a mark signal of a link synchronization state, wherein a sync of 1 indicates successful link synchronization, and a sync of 0 indicates failure link synchronization; the sysref generated by the sysref-generate module enters a sysref-shift module, and the sysref-shift module adjusts the delay value of the ODELAYE3 according to the synchronous state of the current link, so as to adjust the phase relation between the sysref and the device clock;
step 3: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is 0, if so, setting the delay value to 256, entering a step 4, if not, subtracting 1 from the delay value, and repeating the step 3;
step 4: detecting the current link state, and if the link synchronization is completed, entering step 5; if the link is not finished synchronously, judging whether the current delay value is equal to 512, if so, entering a step 5, otherwise, adding 1 to the delay value, and repeating the step 4;
step 5: the delay value is maintained and the enable signal of the sysref_generate module is turned off, and sysref is not generated.
2. The automatic synchronization method of ADC for an ultrasound system according to claim 1, wherein: the clock cycles to the FPGA are integer multiples of the clock cycles to the ADC.
3. The automatic synchronization method of ADC for an ultrasound system according to claim 1, wherein: phase adjustment of sysref and the reference clock device clock of the ADC is achieved by ODELAYE 3.
4. The automatic synchronization method of ADC for an ultrasound system according to claim 1, wherein: the sysref_shift module is preset with an adjustment interval, in each adjustment interval, the sysref_shift module detects the synchronous state of the link, if the link is successful in synchronization, the delay value is kept and no adjustment is performed any more, and if the link is failed in synchronization, the delay value adjustment is continued.
5. The automatic synchronization method for ADC of an ultrasound system according to claim 4, wherein: the adjustment interval of the sysref_shift module is 0.5 ms-2 ms.
6. A method of automatic synchronization of ADCs for an ultrasound system according to any of claims 1-3, wherein the sysref is a configurable signal, configurable to generate only one pulse upon power-up, or configured as a controlled periodic signal, the sysref and device clock being homologous signals.
7. The method of claim 6, wherein when sysref is a controlled periodic signal, the period of sysref is an integer multiple of LMFC, where lmfc=k×f×frame clock period, K is the number of frames included in a multiframe, and F is the number of bytes in frame data.
8. The method of automatic synchronization of ADC for an ultrasound system according to claim 1, wherein the phase relationship between sysref and device clock is adjusted according to the current system state, and the phase adjustment is stopped when JESD204B link synchronization is completed.
9. An ADC auto-synchronization device for an ultrasound system, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any one of claims 1 to 8 when executing the computer program.
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402597A (en) * | 2017-07-31 | 2017-11-28 | 上海联影医疗科技有限公司 | A kind of data and method, apparatus of clock alignment, medium and magnetic resonance equipment |
| CN108132592A (en) * | 2017-12-20 | 2018-06-08 | 上海联影医疗科技有限公司 | A kind of time-to-digital conversion apparatus, detector, method and medium |
| CN108134607A (en) * | 2017-12-20 | 2018-06-08 | 北京华航无线电测量研究所 | High-speed AD synchronous acquisition circuit and synchronous method between plate based on JESD204B |
| CN108233906A (en) * | 2018-02-07 | 2018-06-29 | 中国电子科技集团公司第三十八研究所 | A kind of booting certainty delayed time system and method based on ADC |
| CN108322483A (en) * | 2018-04-10 | 2018-07-24 | 北京航空航天大学 | A kind of implementation method of the receiving terminal circuit based on JESD204B agreements |
| CN109286483A (en) * | 2018-11-13 | 2019-01-29 | 珠海格力电器股份有限公司 | Method and equipment for acquiring data |
| CN109815099A (en) * | 2018-12-28 | 2019-05-28 | 北京时代民芯科技有限公司 | The FPGA verification method of JESD204B controller |
| CN109889211A (en) * | 2018-12-24 | 2019-06-14 | 中国电子科技集团公司第二十研究所 | A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit |
| CN211264148U (en) * | 2020-03-25 | 2020-08-14 | 四川鸿创电子科技有限公司 | Novel array ADC gathers synchronous device |
| CN112543025A (en) * | 2020-12-08 | 2021-03-23 | 成都天奥信息科技有限公司 | High-speed serial AD sampling and data processing system and method based on matrixing |
| CN112615613A (en) * | 2020-10-29 | 2021-04-06 | 北京无线电测量研究所 | Ultra-wideband waveform storage and generation device |
| CN113098647A (en) * | 2020-01-09 | 2021-07-09 | 烽火通信科技股份有限公司 | Method and system for calculating asymmetric errors of link caused by wavelength difference |
| CN113467696A (en) * | 2021-06-30 | 2021-10-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel AD data synchronous transmission system |
| CN113507305A (en) * | 2021-07-31 | 2021-10-15 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array beam forming device |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2902866B1 (en) * | 2014-02-04 | 2018-03-07 | Hittite Microwave LLC | System ready in a clock distribution chip |
| US10075156B2 (en) * | 2016-09-30 | 2018-09-11 | Texas Instruments Incorporated | Synchronous clock generation using an interpolator |
-
2022
- 2022-06-17 CN CN202210690500.7A patent/CN115102682B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402597A (en) * | 2017-07-31 | 2017-11-28 | 上海联影医疗科技有限公司 | A kind of data and method, apparatus of clock alignment, medium and magnetic resonance equipment |
| CN108132592A (en) * | 2017-12-20 | 2018-06-08 | 上海联影医疗科技有限公司 | A kind of time-to-digital conversion apparatus, detector, method and medium |
| CN108134607A (en) * | 2017-12-20 | 2018-06-08 | 北京华航无线电测量研究所 | High-speed AD synchronous acquisition circuit and synchronous method between plate based on JESD204B |
| CN108233906A (en) * | 2018-02-07 | 2018-06-29 | 中国电子科技集团公司第三十八研究所 | A kind of booting certainty delayed time system and method based on ADC |
| CN108322483A (en) * | 2018-04-10 | 2018-07-24 | 北京航空航天大学 | A kind of implementation method of the receiving terminal circuit based on JESD204B agreements |
| CN109286483A (en) * | 2018-11-13 | 2019-01-29 | 珠海格力电器股份有限公司 | Method and equipment for acquiring data |
| CN109889211A (en) * | 2018-12-24 | 2019-06-14 | 中国电子科技集团公司第二十研究所 | A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit |
| CN109815099A (en) * | 2018-12-28 | 2019-05-28 | 北京时代民芯科技有限公司 | The FPGA verification method of JESD204B controller |
| CN113098647A (en) * | 2020-01-09 | 2021-07-09 | 烽火通信科技股份有限公司 | Method and system for calculating asymmetric errors of link caused by wavelength difference |
| CN211264148U (en) * | 2020-03-25 | 2020-08-14 | 四川鸿创电子科技有限公司 | Novel array ADC gathers synchronous device |
| CN112615613A (en) * | 2020-10-29 | 2021-04-06 | 北京无线电测量研究所 | Ultra-wideband waveform storage and generation device |
| CN112543025A (en) * | 2020-12-08 | 2021-03-23 | 成都天奥信息科技有限公司 | High-speed serial AD sampling and data processing system and method based on matrixing |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
| CN113467696A (en) * | 2021-06-30 | 2021-10-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel AD data synchronous transmission system |
| CN113507305A (en) * | 2021-07-31 | 2021-10-15 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Digital array beam forming device |
Non-Patent Citations (7)
| Title |
|---|
| "基于 JESD204B 协议的相控阵雷达下行同步采集技术应用";陈洋等;《雷达与对抗》;第35卷(第2期);0-4节 * |
| "基于JESD204B 协议的雷达多通道同步采集实现";孙维佳等;《电子技术与软件工程》;全文 * |
| A JESD204B-Compliant Architecture for Remote and Deterministic-Latency Operation;Raffaele Giordano等;《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》;第64卷(第6期);附图4 * |
| 一种基于国产ADC的高速信号采集系统;王育才;包晓军;刘远曦;李琳;刘会涛;;电子世界(第13期);全文 * |
| 基于AD9250的高速数据接口设计;吴志勇;王杰;程琦;;电子制作(第02期);全文 * |
| 基于JESD204B协议的高速雷达数字接收机设计;焦喜香;吴兵;李武建;向海生;;信息通信(第06期);全文 * |
| 用于波形数字化的JESD204B高速接口设计;郑墁煜;曹平;安琪;;原子核物理评论(第04期);全文 * |
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