CN105610532A - Signal transmission processing method, signal transmission processing device and signal transmission processing equipment - Google Patents
Signal transmission processing method, signal transmission processing device and signal transmission processing equipment Download PDFInfo
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- CN105610532A CN105610532A CN201410631790.3A CN201410631790A CN105610532A CN 105610532 A CN105610532 A CN 105610532A CN 201410631790 A CN201410631790 A CN 201410631790A CN 105610532 A CN105610532 A CN 105610532A
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Abstract
The invention provides a signal transmission processing method, a signal transmission processing device and signal transmission processing equipment. The method comprises the following steps: detecting a request signal generated by first equipment in a first clock domain, wherein the request signal is used for indicating that data reception in the first clock domain is allowed; converting the request signal into a keep signal, wherein the keep signal is a signal which is continuously kept effective before the keep signal is synchronized in a second clock domain; using the second clock domain to synchronize the keep signal to get an output signal of the request signal, and outputting the output signal to second equipment in the second clock domain. By adopting the technical scheme provided by the invention, the technical problem in the related technologies that cross-clock-domain signal transmission occupies a lot of hardware resources and is complex to implement is solved, and the consumption of hardware resources is reduced and the complexity of implementation is lowered while elimination of the metastable state is guaranteed.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of method for transmission processing of signal and device, equipment.
Background technology
In the communications field or hardware logic design field, only relate to the system in single clock territory few, for more complicated, in system, conventionally there is the transmission between multiple clock zone signals, due to metastable existence, if method for transmitting signals in applicationImproper, can cause metastable propagation on a large scale, affect the normal function of system. Adopt rationally cross clock domain transmission efficientlyMethod, can avoid metastable appearance, ensures that system stability and function are normal.
In correlation technique, the conventional method across clock signal transmission, can be divided into following a few class:
One, directly to need to be across the mutual signal of clock, utilize the clock of two-stage or three grades of register pair target clock zones to beatClap and process, signal is synchronized to target clock zone, complete across clock transfer.
Two, use asynchronous FIFO (First-InFirst-Out, referred to as FIFO) to process across clock signal and transmit. AsynchronousTwo clocks of FIFO be used for respectively to data writing in FIFO and from FIFO sense data. By complete writingEnter and read process, the cross clock domain of settling signal transmits.
Although can utilize technique scheme to realize the signal transmission of cross clock domain, have following technical problem: if adoptedUse the first scheme, directly signal is carried out to register and play bat processing, first can not ensure to eliminate metastable state, and depositDevice is beaten in bat process, because the clock zone under signal changes, likely causes the loss of signal; If employing the secondScheme, is used asynchronous FIFO mode that cross clock domain signal is transmitted and processed, although can more effectively eliminate metastable state,Be that FIFO itself has taken more hardware resource, increased logic complexity.
For the problems referred to above in correlation technique, there is no at present effective solution.
Summary of the invention
The invention provides a kind of method for transmission processing of signal and device, equipment, at least to solve cross clock domain in correlation techniqueSignals transmission exists and takies more hardware resource, realizes the technical problems such as complicated.
According to an aspect of the present invention, provide a kind of method for transmission processing of signal, having comprised: detected in the first clock zoneThe request signal that the first equipment produces, wherein, described request signal is used to indicate and allows to receive data at described the first clock zone;Described request signal is converted to inhibit signal, and described inhibit signal is to the synchronous success of described inhibit signal in second clock territoryBefore, the signal that continues to remain valid; Utilize described second clock territory to carry out synchronously described inhibit signal, obtain described request letterNumber output signal, and described output signal is exported to the second equipment that is arranged in described second clock territory.
Preferably, utilize described second clock territory to described inhibit signal carry out synchronous after, also comprise: by described first o'clockClock territory carries out synchronously, obtaining for making the signal that described inhibit signal is invalid to described output signal.
Preferably, after exporting described output signal to be arranged in described second clock territory the second equipment, comprising: receive rootThe answer signal producing in described second clock territory according to described output signal; Described answer signal is synchronized to described the first clock zone,And export the described answer signal after synchronous to described the first equipment, wherein, described answer signal is used for triggering described first and establishesThe standby data that receive from described the second equipment.
Preferably, below, one of at least signal is 1 bit: described request signal, described inhibit signal, described output signal.
According to another aspect of the present invention, provide a kind of transmission processing device of signal, having comprised: detection module, for inspectionMeasure the request signal that in the first clock zone, the first equipment produces, wherein, described request signal is used to indicate and allows described firstClock zone receives data; Modular converter, for described request signal is converted to inhibit signal, described inhibit signal is secondClock zone is to before the synchronous success of described inhibit signal, the signal that continues to remain valid; The first synchronization module, described in utilizingSecond clock territory carries out synchronously, obtaining the output signal of described request signal to described inhibit signal; Output module, for by instituteState output signal and export the second equipment that is arranged in described second clock territory to.
Preferably, said apparatus also comprises: the second synchronization module, and for described output signal being entered by described the first clock zoneRow is synchronous, obtains for making the signal that described inhibit signal is invalid.
Preferably, said apparatus also comprises: receiver module, produces in described second clock territory according to described output signal for receivingRaw answer signal; The 3rd synchronization module, for described answer signal being synchronized to described the first clock zone, and by after synchronousDescribed answer signal exports described the first equipment to, and wherein, described answer signal is used for triggering described the first equipment and receives from instituteState the data of the second equipment.
According to a further aspect of the invention, provide a kind of transmission processing apparatus of signal, having comprised: controller, for examiningWhile measuring the request signal from the first equipment in the first clock zone, described request signal is converted to inhibit signal, and by instituteState inhibit signal and be sent to SYN register, wherein, described request signal is used to indicate and allows to receive number at described the first clock zoneAccording to, described inhibit signal is before second clock territory is to the synchronous success of described inhibit signal, the signal that continues to remain valid; InstituteState SYN register, be connected with described controller, for utilizing described second clock territory to carry out synchronously described inhibit signal,To the output signal of described request signal, and described output signal is exported to the second equipment that is arranged in described second clock territory.
Preferably, the said equipment also comprises: feedback register, is connected with described SYN register, for by described output signalFeed back to described controller, and by described the first clock zone, described output signal is carried out synchronously, obtaining for making described maintenanceThe signal of invalidating signal, and signal invalid described inhibit signal is sent to described controller.
Preferably, described controller, also for receiving the answer signal producing in described second clock territory according to described output signal,And described answer signal is synchronized to described the first clock zone, and exports the described answer signal after synchronous to described first and establishStandby, wherein, described answer signal receives the data from described the second equipment for triggering described the first equipment.
By the present invention, adopt the request signal that in the first clock zone, the first equipment produces is converted to inhibit signal, and utilize instituteState second clock territory described inhibit signal is carried out to technological means synchronous and output, solved in correlation technique cross clock domain letterNumber transmitting procedure exists and takies more hardware resource, realizes the technical problems such as complicated, thereby eliminates the metastable while ensureing,Reduce hardware resource, reduced the complexity realizing.
Brief description of the drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, of the present invention showingMeaning property embodiment and explanation thereof are used for explaining the present invention, do not form inappropriate limitation of the present invention. In the accompanying drawings:
Fig. 1 is according to the flow chart of the method for transmission processing of the signal of the embodiment of the present invention;
Fig. 2 is according to the structured flowchart of the transmission processing device of the signal of the embodiment of the present invention;
Fig. 3 is another structured flowchart according to the transmission processing device of the signal of the embodiment of the present invention;
Fig. 4 is according to the structured flowchart of the transmission processing apparatus of the signal of the embodiment of the present invention;
Fig. 5 is another structured flowchart according to the transmission processing apparatus of the signal of the embodiment of the present invention;
Fig. 6 is the principle schematic that realizes according to the cross clock domain signal transmission of the embodiment of the present invention;
Fig. 7 is synchronization stretching (Sync&PulseBroaden) the inside modules operation principle schematic diagram according to the embodiment of the present invention;
Fig. 8 be according to the embodiment of the present invention for embodying the oscillogram of signal cross clock domain transmitting procedure.
Detailed description of the invention
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments. It should be noted that, in the situation that not conflicting,Feature in embodiment and embodiment in the application can combine mutually.
The embodiment of the present invention can not thoroughly be avoided metastable state for signal in correlation technique across time domain transmission, takies more hardware resource,Realize the shortcomings such as complicated, the implementation of signal transmission between a kind of different clock-domains is provided, be used for realizing signal in the time of differenceTransmission between clock territory. This scheme is supported the transmission of signal between frequency, the diverse clock zone of phase place, supports pulse widthBe less than the transmission of the signal of clock cycle. Below describe this implementation in detail.
Fig. 1 is according to the flow chart of the method for transmission processing of the signal of the embodiment of the present invention. As shown in Figure 1, the method comprise withLower treatment step:
Step S102, detects the request signal that in the first clock zone, the first equipment produces, and wherein, this request signal is used to indicateAllow to receive data at above-mentioned the first clock zone;
Step S104, is converted to inhibit signal by above-mentioned request signal, and above-mentioned inhibit signal is to above-mentioned maintenance in second clock territoryBefore the synchronous success of signal, the signal that continues to remain valid;
Step S106, utilizes above-mentioned second clock territory to carry out synchronously above-mentioned inhibit signal, obtains the output letter of above-mentioned request signalNumber, and above-mentioned output signal is exported to the second equipment that is arranged in above-mentioned second clock territory.
By above-mentioned each treatment step, due to the request signal that sends to second clock territory is converted to inhibit signal, and canWith the signal that continued to remain valid, therefore, can realize pulse signal before this inhibit signal is by the synchronous success in second clock territoryBroadening, avoided thoroughly eliminating metastable defect, and, saved register resources, reduced realize across time domainThe complexity of signal transmission.
In order to save operation resource, avoid inhibit signal to continue to keep, also need above-mentioned inhibit signal to carry out invalid setting,In a preferred embodiment of the present invention, can utilize above-mentioned output signal to arrange: utilize above-mentioned second clock territory onState inhibit signal carry out synchronous after, by above-mentioned the first clock zone, above-mentioned output signal is carried out synchronously, obtaining for making above-mentionedThe signal that inhibit signal is invalid, is about to be divided into two-way by the above-mentioned output signal obtaining in step S106, and a road exports toState the second equipment, an other road is for generation of making the signal that above-mentioned inhibit signal is invalid. Like this, just, can believe above-mentioned outputWhen number synchronous success, remove above-mentioned inhibit signal (inhibit signal being set invalid). Wherein, in concrete application process, will protectHolding signal setting is that invalid process can be presented as that inhibit signal is set to low level, but is not limited to this.
For the process that above-mentioned inhibit signal is invalid can be realized by self feed back mechanism, for example, in step S102-S106For example, when executive agent is a designated equipment (controller), after can carrying out synchronously to above-mentioned output signal by the first clock zone,Feed back to this designated equipment, it is invalid to be set to by the above-mentioned inhibit signal of this designated equipment.
Before step S102, be about to send to before the request signal in second clock territory is converted to the inhibit signal of remaining valid,Also need to detect that the first clock zone produces above-mentioned request signal, and, after the above-mentioned output signal of output, receive according to upperState the answer signal that output signal produces in above-mentioned second clock territory; Above-mentioned answer signal is synchronized to above-mentioned the first clock zone, andExport the above-mentioned answer signal after synchronous to above-mentioned the first equipment, wherein, above-mentioned answer signal is used for triggering above-mentioned the first equipmentReceive the data from above-mentioned the second equipment. So just, can realize the transmission of data at different clock-domains. A concrete applicationIn process, can show as following processing procedure, but be not limited to this:
Above-mentioned the second equipment is sending in answer signal, and the data that needs are sent are put on interface signal line Data_Out alsoMaintain, receive after above-mentioned answer signal at the first equipment, it is invalid that above-mentioned request signal is set to, and receive from secondThe data of equipment.
In a preferred embodiment of the invention, in order to save operation resource, can be by above-mentioned request signal, above-mentioned maintenance letterNumber, one of be at least set to 1 bit in above-mentioned output signal. Can save like this register resources:
1, when utilizing two-stage or three grades of registers to play bat, when data are synchronized to this method of destination register, for example, needThe data of 2 8bit are passed to target clock zone, and the register quantity of using when two-stage is played bat is so 2*8*2=32, beats for three gradesThe register quantity of using when bat is 2*8*3=48,
And while adopting the scheme of the embodiment of the present invention, request, feedback, the inhibit signal used due to handshake phase are all single-bit,The register quantity of using in middle handshake procedure is far smaller than 8 multiple, and the rear data of having shaken hands are disposable while passing to targetClock territory, pilot process does not need register to participate in, so can save 3 times of above registers than two-stage or three grades of methods of playing batQuantity.
2, when realize across clock transfer with FIFO, build FIFO itself and can use a lot of registers and realize, for example wideDegree is that 8 degree of depth are just at least to have used 16 registers at 2 o'clock, and using register quantity is also the side far more than the embodiment of the present inventionCase.
The embodiment of the present invention can reduce the reason of register use amount, is to have used multiple single-bit signal to complete middle shaking hands,The disposable data transmission many bits of the rear ability of having shaken hands is gone over, and has avoided the transmission of multi-bit data in intermediate steps, alsoJust reduce shared register quantity.
The embodiment of the present invention also provides a kind of transmission processing device of signal, for realizing said method, as shown in Figure 2, shouldDevice comprises following processing module:
Detection module 20, for detection of the request signal that the first equipment produces in the first clock zone, wherein, this request signal is usedAllow to receive data at above-mentioned the first clock zone in instruction;
Modular converter 22, is connected to detection module 20, for above-mentioned request signal is converted to inhibit signal, and above-mentioned inhibit signalFor before second clock territory is to the synchronous success of above-mentioned inhibit signal, the signal that continues to remain valid;
The first synchronization module 24, is connected to modular converter 22, same for utilizing above-mentioned second clock territory to carry out above-mentioned inhibit signalWalk, obtain the output signal of above-mentioned request signal;
Output module 26, is connected to the first synchronization module 24, is positioned at above-mentioned second clock territory for above-mentioned output signal is exported toIn the second equipment.
The function realizing by above-mentioned modules, can avoid thoroughly eliminating metastable defect equally, and, saveRegister resources, reduces the complexity realizing across time domain signal transmission.
In a preferred embodiment, the transmission processing device of the signal that the embodiment of the present invention provides, as shown in Figure 3, all rightComprise: the second synchronization module 28, for above-mentioned output signal being carried out synchronously, obtaining for making by above-mentioned the first clock zoneState the signal that inhibit signal is invalid.
In a preferred implementation process, the transmission processing device of the signal that the embodiment of the present invention provides, as shown in Figure 3, also canTo comprise: receiver module 30, for receiving the answer signal producing in above-mentioned second clock territory according to above-mentioned output signal; The 3rdSynchronization module 32, is connected to receiver module 30, for above-mentioned answer signal being synchronized to above-mentioned the first clock zone, and by after synchronousAbove-mentioned answer signal export above-mentioned the first equipment to, wherein, above-mentioned answer signal be used for triggering above-mentioned first equipment receive fromThe data of above-mentioned the second equipment.
The embodiment of the present invention also provides a kind of transmission processing apparatus of signal, and as shown in Figure 4, this equipment comprises:
Controller (being called again control register) 40, for the request signal of the first equipment in detecting from the first clock zoneTime, above-mentioned request signal is converted to inhibit signal, and above-mentioned inhibit signal is sent to SYN register, wherein, above-mentionedRequest signal is used to indicate and allows to receive data at above-mentioned the first clock zone, and above-mentioned inhibit signal is to above-mentioned guarantor in second clock territoryBefore holding the synchronous success of signal, the signal that continues to remain valid;
SYN register 42, is connected with controller 40, for utilizing above-mentioned second clock territory to carry out synchronously above-mentioned inhibit signal,Obtain the output signal of above-mentioned request signal, and export above-mentioned output signal to be arranged in above-mentioned second clock territory the second equipment.
In a preferred implementation process, as shown in Figure 5, can also comprise: feedback register 44, connects with SYN register 42Connect, for above-mentioned output signal is fed back to above-mentioned controller, and above-mentioned output signal is carried out same by above-mentioned the first clock zoneStep, obtains for making the signal that above-mentioned inhibit signal is invalid, and signal invalid above-mentioned inhibit signal is sent to above-mentioned controlDevice 40.
In a preferred embodiment of the present invention, controller 40, also for receiving according to above-mentioned output signal at above-mentioned second clockThe answer signal that territory produces, and above-mentioned answer signal is synchronized to above-mentioned the first clock zone, and by the above-mentioned letter of replying after synchronousNumber export above-mentioned the first equipment to, wherein, above-mentioned answer signal is used for triggering above-mentioned the first equipment and receives from above-mentioned the second equipmentData.
It should be noted that, in the transmission processing apparatus of the signal providing in the embodiment of the present invention, involved register (for exampleSYN register, feedback register etc.) can be one or more, concrete quantity can be determined according to actual conditions.
In order to understand better above-described embodiment, describe in detail below in conjunction with preferred embodiment.
It is a kind of by handshake can be according to the transmission system of signal of the automatic broadening of feedback that the preferred embodiment of the present invention provides,Realize the cross clock domain transmission of signal, improve the correctness of signal transmission, the normal steady operation of guarantee system.
The transmission processing device of the signal that the present embodiment provides mainly comprises following a few part: main frame (is equivalent in above-described embodimentThe first equipment), slave (being equivalent to the second equipment in above-described embodiment) and synchronization stretching module (be equivalent to above-described embodimentIn the transmission processing apparatus of signal and/or the transmission processing device of signal that provide). Wherein the corresponding clock zone of main frame is (host clock)MasterClock, the corresponding clock zone of slave is slave clock (SlaveClock), the existing MasterClock of synchronization stretching inside modules,There is again SlaveClock.
● the function of main frame has: send request signal, receive data, finish current request signal according to slave answer signal.
● the function of slave has: receive request signal, send data, send answer signal.
● the function of synchronization stretching module has: the request signal of main frame is carried out synchronously, automatically carrying out according to the situation of replying of slaveBroadening, and be passed to slave module; The answer signal of slave is carried out synchronously, being passed to main frame.
What cross clock domain signal transmitted realizes principle as shown in Figure 6.
(1) main frame (Master) sends request signal (Master_Req_In), and expression can receive data.
(2) synchronization stretching module (Sync&PulseBroaden) operation principle as shown in Figure 7. Control register is received main frameRequest signal (Master_Req_In), utilizes Master_Req_In as judging signal, produces at MasterClock clock zoneA single-bit inhibit signal (keep), keep signal is undertaken same by the SYN register (1,2) of SlaveClock clock zoneAfter step, the output signal (Maste_Req_Out) that becomes request signal outputs to slave as request signal. Then, request letterNumber output signal (Maste_Req_Out), after feedback register (1,2) by MasterClock clock zone is synchronous,The clear signal that becomes maintenance (keep) signal, feeds back to control register, so that keep signal is returned to low level.
By the method for widening of step (2), can avoid host request signal (Master_Req_In) being synchronized to SlaveClockWhen clock zone, lose: in the time that host clock and slave clock difference cause very greatly first synchronization failure, keep signal is owing to receivingTo clear signal, will remain on high level, until by the correct sample-synchronous success of SlaveClock always; When after synchronous success,Keep receives clear signal, will be reduced in time low level.
(3) slave (Slave) is received after the output signal Master_Req_Out of request signal, utilizes this signal at SlaveClockClock zone produces an answer signal Slave_Ack_In, and the data that simultaneously needs sent are put on interface signal line Data_OutAnd maintain.
(4) answer signal (Slave_Ack_In) is synchronized to MasterClock by synchronization stretching module (Sync&PulseBroaden)Clock zone, outputs to main frame after becoming Slave_Ack_Out.
(5) Host Detection is after the output signal Slave_Ack_Out of normal answer signal, by request signalMaster_Req_In retracts low level, the data in slave interface signal line are deposited into simultaneously come, so just completed data from fromMachine is to the transmission of main frame
(6) slave detects that host request signal retracts after low level, and the answer signal Slave_Ack_In of oneself is also become lowLevel.
Through above 6 steps, complete the transmission that realizes cross clock domain signal by handshake. If (3) step in additionFail and reply, host module can be initiated request signal again, is successfully completed transfer of data until both sides shake hands.
The oscillogram of Fig. 8 has embodied the complete step of signal cross clock domain transmission equally. Wherein clk and pclk are two when differentClock, signal data1～data4 will be passed to clk from pclk. First be that clk clock zone sends request signal Master_Req_In.Synchronization stretching module is received the request signal Master_Req_In of main frame, utilizes Master_Req_In as judging signal,MasterClock clock zone produces a single-bit inhibit signal keep, and keep signal is undertaken same by SlaveClock clock zoneAfter step, become the output signal Maste_Req_Out of request signal, output to slave. Then, Maste_Req_Out passes through againAfter MasterClock clock zone is synchronous, become the clear signal that keeps keep signal, be used for keep signal to be returned to low level.Slave is received after request signal Master_Req_Out, utilizes this signal to produce an answer signal at SlaveClock clock zoneSlave_Ack_In, the data that simultaneously needs sent are put into interface signal line Data_Out and go up and maintain. Synchronization stretching module(Sync&PulseBroaden) answer signal Slave_Ack_In is synchronized to MasterClock clock zone, becomesAfter Slave_Ack_Out, output to main frame. Host Detection is after normal answer signal Slave_Ack_Out, by request signalMaster_Req_In retracts low level, the data in slave interface signal line are deposited into simultaneously come, so just completed data from fromMachine is to the transmission of main frame. Slave detects that host request signal retracts after low level, by the answer signal Slave_Ack_In of oneselfAlso become low level.
In sum, the embodiment of the present invention has realized following beneficial effect: (1) is beaten to clap with direct use register and compared, and avoidsCan not thoroughly eliminate metastable state, the signal transmitting when needs is when a lot of, the use of minimizing register resources that again can be at double. (2)Compare with asynchronous FIFO, reduced the use of module complexity and hardware resource, implementation method is more succinct.
In another embodiment, also provide a kind of software, this software is used for carrying out above-described embodiment and preferred embodimentThe technical scheme of middle description.
In another embodiment, also provide a kind of storage medium, in this storage medium, stored above-mentioned software, this storageMedium includes but not limited to: CD, floppy disk, hard disk, scratch pad memory etc.
Obviously, it is apparent to those skilled in the art that each module of the present invention or each step can be next with general calculation elementRealize, they can concentrate on single calculation element, or are distributed on the network that multiple calculation elements form, optionalGround, they can be realized with the executable program code of calculation element, thereby, they can be stored in storage device byCalculation element is carried out, and in some cases, can carry out shown or described step with the order being different from herein,Or they are made into respectively to each integrated circuit modules, or the multiple modules in them or step are made into single integratedCircuit module is realized. Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art, the present invention can have various modifications and variations. Within the spirit and principles in the present invention all, any amendment of doing, etc.With replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a method for transmission processing for signal, is characterized in that, comprising:
The request signal that in the first clock zone, the first equipment produces detected, wherein, described request signal is used to indicate permissionReceive data at described the first clock zone;
Described request signal is converted to inhibit signal, and described inhibit signal is same to described inhibit signal in second clock territoryBefore walking successfully, the signal that continues to remain valid;
Utilize described second clock territory to carry out synchronously, obtaining the output signal of described request signal to described inhibit signal, andDescribed output signal is exported to the second equipment that is arranged in described second clock territory.
2. method according to claim 1, is characterized in that, utilizes described second clock territory to carry out described inhibit signal sameAfter step, also comprise:
By described the first clock zone, described output signal is carried out synchronously, obtaining for making the letter that described inhibit signal is invalidNumber.
3. method according to claim 1, is characterized in that, described output signal is exported to and is positioned at described second clock territoryIn the second equipment after, comprising:
Receive the answer signal producing in described second clock territory according to described output signal;
Described answer signal is synchronized to described the first clock zone, and exports the described answer signal after synchronous to described theOne equipment, wherein, described answer signal receives the data from described the second equipment for triggering described the first equipment.
4. according to the method in any one of claims 1 to 3, it is characterized in that, below one of at least signal be 1 bit:
Described request signal, described inhibit signal, described output signal.
5. a transmission processing device for signal, is characterized in that, comprising:
Detection module, for detection of the request signal that the first equipment produces in the first clock zone, wherein, described request letterNumber be used to indicate and allow to receive data at described the first clock zone;
Modular converter, for described request signal is converted to inhibit signal, described inhibit signal is in second clock territory pairBefore the synchronous success of described inhibit signal, the signal that continues to remain valid;
The first synchronization module, for utilizing described second clock territory to carry out synchronously, obtaining described request to described inhibit signalThe output signal of signal;
Output module, for exporting described output signal to the second equipment that is positioned at described second clock territory.
6. device according to claim 5, is characterized in that, also comprises:
The second synchronization module, for carrying out synchronously, obtaining for making to described output signal by described the first clock zoneState the signal that inhibit signal is invalid.
7. device according to claim 5, is characterized in that, also comprises:
Receiver module, for receiving the answer signal producing in described second clock territory according to described output signal;
The 3rd synchronization module, for described answer signal being synchronized to described the first clock zone, and by described the answering after synchronousAnswer signal and export described the first equipment to, wherein, described answer signal is used for triggering described the first equipment and receives from describedThe data of the second equipment.
8. a transmission processing apparatus for signal, is characterized in that, comprising:
Controller, during for the request signal of the first equipment in detecting from the first clock zone, by described request signalBe converted to inhibit signal, and described inhibit signal is sent to SYN register, wherein, described request signal is used in reference toShow and allow to receive data at described the first clock zone, described inhibit signal is synchronous to described inhibit signal in second clock territoryBefore success, the signal that continues to remain valid;
Described SYN register, is connected with described controller, for utilizing described second clock territory to enter described inhibit signalRow is synchronous, obtains the output signal of described request signal, and described output signal is exported to and is positioned at described second clock territoryIn the second equipment.
9. equipment according to claim 8, is characterized in that, also comprises:
Feedback register, is connected with described SYN register, for described output signal is fed back to described controller, andBy described the first clock zone, described output signal is carried out synchronously, obtains for making the signal that described inhibit signal is invalid,And signal invalid described inhibit signal is sent to described controller.
10. equipment according to claim 8, is characterized in that, described controller, also for receiving according to described output signalThe answer signal producing in described second clock territory, and described answer signal is synchronized to described the first clock zone, and willDescribed answer signal after synchronous exports described the first equipment to, and wherein, described answer signal is used for triggering described first and establishesThe standby data that receive from described the second equipment.
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| CN201410631790.3A CN105610532B (en) | 2014-11-11 | 2014-11-11 | The method for transmission processing and device of signal, equipment |
| PCT/CN2015/074533 WO2016074402A1 (en) | 2014-11-11 | 2015-03-18 | Signal transmission processing method and apparatus, and device |
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| CN112148655A (en) * | 2019-06-28 | 2020-12-29 | 深圳市中兴微电子技术有限公司 | Method and device for processing multi-bit data across clock domains |
| CN113821075A (en) * | 2021-09-27 | 2021-12-21 | 上海航天计算机技术研究所 | Clock domain crossing processing method and device for asynchronous multi-bit signal |
| CN114117972A (en) * | 2022-01-26 | 2022-03-01 | 之江实验室 | Synchronous device and method of asynchronous circuit |
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| CN112148655B (en) * | 2019-06-28 | 2023-11-17 | 深圳市中兴微电子技术有限公司 | Multi-bit data clock domain crossing processing method and device |
| CN113821075A (en) * | 2021-09-27 | 2021-12-21 | 上海航天计算机技术研究所 | Clock domain crossing processing method and device for asynchronous multi-bit signal |
| CN114117972A (en) * | 2022-01-26 | 2022-03-01 | 之江实验室 | Synchronous device and method of asynchronous circuit |
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| CN105610532B (en) | 2019-05-24 |
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