JP2007274049A - Semiconductor integrated circuit and semiconductor integrated circuit design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a design period and decrease power noise in a semiconductor integrated circuit and an EMI problem of a product. <P>SOLUTION: A source synchronous type interface for transmitting a clock and data at the same time is adopted for an interface between hierarchical blocks. A receiver 24 of a receiver side block 22 is provided with a clock phase detector 27 and a VDL 28 for configuring a mesochronous type synchronization circuit, receives data of the inter-block interface without setup/hold violation and transfers the data to an internal circuit of the receiver side block 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention can shorten the design period of a large-scale semiconductor integrated circuit and reduce power supply noise in a large-scale semiconductor integrated circuit, which will be a problem in future semiconductor integrated circuits in which the power supply voltage is lowered, thereby improving reliability and reducing EMI. The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit design method.

Conventionally, semiconductor integrated circuits have been designed by the following method.
1) When designing a large-scale semiconductor integrated circuit, when incorporating an existing IP macro (for example, a macro block in a black box purchased from another company), the semiconductor integrated circuit is hierarchized to form a lower layer block and its lower layer block. In general, the design is divided into the top level of the upper layer connecting the blocks. In this case, the clock delays reaching the FFs in each lower layer block are made as equal as possible, and the clock skew between all the FFs in the semiconductor integrated circuit is made as small as possible. In order to design the clock skew of the entire semiconductor integrated circuit as small as possible, the physical design within the block is first performed, the clock delay inside the block is determined, and this is fed back to the clock wiring delay at the TOP level. (For example, refer to Patent Document 1 below.)

  2) On the other hand, by analyzing the power consumption in the clock cycle in the semiconductor integrated circuit, a large number of clock drivers included in the clock system and the power consumption of the FF operating immediately after the clock arrives, the entire chip It has been found that there is a phenomenon that more than 1/3 of the power consumption is consumed, the power consumption gradually decreases thereafter, and there is almost no power consumption in the second half of the clock cycle. The FF consumes power every time the clock enters, and the distribution of the delay of the logical path between the FFs increases as the delay is shorter and the delay time is longer than half of the clock cycle. Since there are quite a few things, this is the power consumption pattern.

JP-A-5-61564

  However, in the case of the hierarchical design of 1) according to the prior art, the timing convergence of the inter-block wiring passing through the TOP level is the most difficult. For example, when the distance between blocks is long and wiring delays unexpected by the logic designer take place, it is necessary to change the logical design, such as adding a relay FF, or change the floor-plan, such as changing the arrangement of blocks. However, there is a problem that the period of logical design / verification or physical design becomes longer.

  As a result of the above 2), when the clock input skew of each FF in a large-scale semiconductor integrated circuit is made as small as possible, the clock reaches a large number of FFs at the same time. , The power consumption gradually decreases, and the power consumption becomes minimal shortly before the arrival of the next clock edge. This causes a large power supply voltage fluctuation (power supply noise), which is the largest source of malfunction and EMI (ELECTROMAGNETIC INTERFERENCE).

  In order to prevent these problems, it is necessary to consider a sufficient power supply margin that can cope with the power supply noise at the time of design.To that end, it is necessary to extend the physical design period and to install a capacitor in the semiconductor integrated circuit. There is a problem that the cost of the semiconductor integrated circuit is increased due to the increase in size of the semiconductor integrated circuit due to the mounting. Further, with respect to EMI, when a large amount of capacitors are mounted on a package / printed circuit board to solve the problem, there arises a problem that the cost of the product is increased.

  The present invention provides a semiconductor integrated circuit and a semiconductor integrated circuit design method capable of shortening a design period and reducing power supply noise in a semiconductor integrated circuit and EMI problems of a product in order to eliminate the above-described problems caused by the prior art. For the purpose.

  In order to solve the above-described problems and achieve the object, the semiconductor integrated circuit according to the present invention is characterized in that the interface between the hierarchized blocks is a source-synchronous type that simultaneously transmits a clock and data.

  Also, the block on the receiving side is provided with a mesochronous type synchronization circuit, and the interface data is received without a setup / hold violation and transferred to the internal circuit of the block on the receiving side.

  Further, the interface between the blocks may be DDR (Double-Data-Rate) or QDR (Quad-Data-Rate) synchronized with the clock, and the number of interface signals between the blocks may be reduced. .

  Further, the present invention is characterized by comprising delay means for operating the blocks with independent clocks and supplying clocks with different phases to the blocks to flatten the difference in power consumption within one clock of the entire circuit.

  In addition, the semiconductor integrated circuit design method according to the present invention is characterized in that the interface between the hierarchized blocks is designed as a source synchronous type that simultaneously sends a clock and data.

  According to the above configuration, the interface timing constraint between lower blocks can be removed in the hierarchical design, and the design period can be shortened. Also, the clock phase can be changed intentionally for each block.

  According to the semiconductor integrated circuit and the semiconductor integrated circuit design method of the present invention, it is possible to remove the restriction that the inter-block interface signal is transferred within one cycle, so that the circuit design period can be shortened. In addition, since the operation time of each block FF can be deliberately shifted, the maximum / minimum power consumption in the clock cycle can be leveled as a whole semiconductor integrated circuit. There is an effect that the EMI problem at the time can be reduced.

  Exemplary embodiments of a semiconductor integrated circuit and a semiconductor integrated circuit design method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Summary of Invention)
The semiconductor integrated circuit includes a plurality of lower blocks and upper level blocks including the plurality of lower blocks, and an interface signal between the lower blocks is designed as a source synchronous type. That is, the transmission side block sends a control signal / data together with the clock of the transmission side block, and the reception side block once latches the reception data with the received clock, and then sends the received block internal clock in phase with the received clock. For receiving circuit.

  In addition, by using a training pattern during initialization, the receiving lower block extracts the clock from the change point of the inter-block interface signal without a clock (CDR: Clock-Data-Recovery), and the above-mentioned source synchronous transfer Data is transferred in the same way as time. Further, the time for the clock to reach each lower block FF is shifted from the semiconductor integrated circuit as a whole, the clock delay can be adjusted in units of lower blocks, and the power supply noise / EMI of the semiconductor integrated circuit is reduced.

(Embodiment)
(Configuration of semiconductor integrated circuit)
FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit according to an embodiment of the present invention. A semiconductor integrated circuit 10 shown in FIG. 1 includes a plurality of lower blocks BLK1 to BLK5 (11-1 to 11-5) and a clock generation circuit 14, and the clock generation circuit 14 transmits a clock to each lower block (11- 1-11-5). Each lower block (11-1 to 11-5) includes a core logic (12-1 to 12-5) and a clock tree (13-1 to 13-5), and each clock tree (13 -1 to 13-5) uses the clock transmitted from the clock generation circuit 14 for FF groups (not shown in FIG. 1) present in the core logic (12-1 to 12-5) in each block. And has a function of transmitting with low skew.

  The core logic (12-1 to 12-5) of each block includes a source synchronous transmitter (16-1-5, 16-5-1, 16-5-3, 16-3-5) and a source. This includes all logic except the synchronous receivers (15-1-5, 15-5-1, 15-5-3, 15-3-5), and corresponds to the concept of the lower block of the conventional hierarchical design. .

  BLK1 (11-1), BLK3 (11-3), and BLK5 (11-5) include source synchronous transmitters (16-1-5, 16-5-1, 16-5-3, 16-3). -5) and source synchronous receivers (15-1-5, 15-5-1, 15-5-3, 15-3-5), and these three sub-blocks (BLK1 (11-1) ), BLK3 (11-3), BLK5 (11-5)), an inter-block clock and data / control signals (18-15, 18-35) are wired. Only data / control signals are wired between BLK2 (11-2) and BLK3 (11-3).

  In the example shown in FIG. 1, between BLK1 (11-1) and BLK5 (11-5), between BLK3 (11-3) and BLK5 (11-5), and between BLK2 (11-2) and BLK3 (11- 3) Only the inter-block signals are depicted as being limited, but actually there are inter-block signals between other blocks, which are omitted in FIG.

  BLK2 (11-2) and BLK3 (11-3) are supplied with the same clock from the clock generation circuit 14, and these two lower blocks operate synchronously, so the interface between both lower blocks is: A conventional inter-synchronous block interface 17 is provided. On the other hand, BLK1 (11-1), BLK5 (11-5), and BLK3 (11-3) and BLK5 (11-5) are supplied with individual clocks from the clock generation circuit 14, and these clocks are supplied. Are mesochronous types with the same frequency but different phases.

  These source synchronous transmitters (16-1-5, 16-5-1, 16-5-3, 16-3-5) and source synchronous receivers (15-1-5, 15-5-1). , 15-5-3, 15-3-5), the phase of the clock to the lower blocks (11-1, 11-3, 11-5) may be arbitrary, and each lower block (11-1, 11-3 and 11-5), the power consumption at the clock cycle level of the semiconductor integrated circuit 10 can be dispersed by largely shifting the clock arrival time to the FF in each of the CMOSs constituting the semiconductor integrated circuit 10. By distributing / homogenizing the switching operation of the transistor elements, the power consumption of the semiconductor integrated circuit 10 can be made uniform without relying on a power supply stabilization capacitor, and power supply noise can be reduced.

(Configuration example 1 of transmitter / receiver: When transmission clock is inverted)
Hereinafter, each configuration example of the transmitter and the receiver provided in the semiconductor integrated circuit illustrated in FIG. 1 will be described. FIG. 2 is a block diagram showing an example of the transmitter / receiver of the present invention. FIG. 2 shows an example in which the transmission clock is inverted (the rising edge of the clock arrives at the receiving block after the data is stabilized).

  The transmission side block 21 includes a transmitter 23, and the transmitter 23 includes a transmission side FF group (positive edge FF group) 25 and an inverter 26 that inverts and outputs the BLK clock. With this structure, the clock at the data change point becomes a down edge, and when the receiving block 22 receives the inter-block clock and the inter-block data from the transmitting block 21, the data is stable at the positive edge of the clock. Therefore, the reception FF group 1 (29-1) can latch the inter-block data propagated from the transmission side block 21 by using the inter-block clock propagated from the transmission side block 21.

  The reception side block 22 includes a receiver 24, and the receiver 24 includes a clock phase detector 27 constituting a synchronization circuit therein and a variable-delay-line (VDL) 28 under the control of the clock phase detector 27. The clock phase detector 27 detects the phase of the inter-block clock sent from the transmission side block 21 and the phase of the clock in the reception side block 22, and the reception FF group 2 (29-2) does not cause a setup / hold timing violation. Such a clock is generated by the VDL 28, and once latched by the reception FF group 2 (29-2), data is transferred to the reception FF group 3 (29-3) using the clock in the reception side block 22.

(Configuration example 2 of transmitter / receiver: When the transmission clock is not inverted)
FIG. 3 is a block diagram showing an example of the transmitter / receiver of the present invention. The configuration in FIG. 3 is almost the same as that in FIG. 2, but is an example in which the positive edge of the clock output from the transmission side block 31 is the same as the data change point (the transmission clock is not inverted).

  The transmission side block 31 includes a transmission side FF group 35 and a buffer 36. The clock in the transmitter 33 is output to the receiving side block 32 via the buffer 36. In the receiver 34 in the reception side block 32, first, the phase relationship of the input inter-block clock is detected by the clock in the reception side block 32 and the clock phase detector 37, and the reception FF group 1 (39-1 is detected by the VDL 38. ) And a clock for the reception FF group 2 (39-2). As the clock for the reception FF group 1 (39-1), a clock obtained by inverting the clock received as the normal inter-block clock is given. Also, as a clock for the reception FF group 2 (39-2), a setup / hold violation between the reception FF group 1 (39-1) and the reception FF group 3 (39-3) using the clock in the BLK. A clock adjusted so that the timing will not appear is given. As a result, the reception side block 32 can receive without setup / hold violation and can transfer to the internal circuit of the reception side block 32.

(Configuration example 3 of the receiver 1 when the clock phase difference between the blocks is known 1)
FIG. 4 is a block diagram showing an example of the receiver of the present invention. The configuration examples of FIGS. 2 and 3 are circuits when the clock phase is not guaranteed at all between the transmission side block and the reception side block, whereas the configuration of FIG. In this example, the phase relationship between the two clocks of the block (omitted) and the receiving side block 41 is known to some extent limited.

  2 and 3, the receiving side block synchronizes data with a three-stage FF group. In the configuration of FIG. 4, the clock phase detector 43 and the VDL 44 are used to synchronize data from the transmitting side block. By narrowing the correlation between the clock and the clock in the reception side block 41 to a certain range at the time of physical design, the reception FF group 1 (45-1) and the reception FF group 2 (45-2) in the receiver 42 Data can be received by the FF of the stage. The range of clock adjustment by the above-mentioned “restricting the correlation between the clock from the transmission side block and the clock in the reception side block 41 to a certain range at the time of physical design” is much more flexible than in the case of complete synchronization. High and easy to do.

(Receiver configuration example 4 ... when the clock phase difference between blocks is known 2)
FIG. 5 is a block diagram showing an example of the receiver of the present invention. The configuration of FIG. 5 is also an example when the phase relationship between the two clocks of the transmission side block (omitted) and the reception side block 51 is known to some extent. The clock in the reception side block 51 is supplied to the reception FF group 2 (55-2) and the clock phase detector 53. 4 generates the clock to be given to the reception FF group 1 (45-1) from the clock of the reception side block 41, whereas in the configuration of FIG. The difference is that the clock for the reception FF group 1 (55-1) is made delayed by the VDL 54.

(Configuration Example 5 of Transmitter / Receiver 1 when DDR is used 1)
FIG. 6A is a block diagram showing an example of a transmitter / receiver of the present invention. In the configuration shown in FIG. 6A, the source synchronous interface is used as the inter-block interface as in the above-described configuration, but DDR (Double-Data) that performs transfer using both the positive edge and the negative edge of the inter-block clock. -Rate) is an example.

  FIG. 6B is a time chart of data transfer according to the configuration of FIG. Transmission / reception that parallel data D0 and D1 in the transmission side block 61 is transferred at a double speed serially in synchronization with the Up / Down edge of the clock at the inter-block interface 60 portion, and parallelized again in the reception side block 62. This is a side block logic example.

  The transmitter 63 in the transmission side block 61 in FIG. 6A has a multiplexer 66-2, and uses the intra-block clock for transmission side FF group even (65-0) and transmission side FF group odd. The data from (65-1) is selected, data synchronized with the clock up / down is created, and is sent to the receiving side block 62. At that time, the clock in the transmission side block 61 is also sent simultaneously through the buffer 66-1. As a result, the inter-block interface 60 becomes double speed data synchronized with both edges of the clock as shown in the time chart of FIG. 6B.

  In addition to the clock phase detector 67 and the VDL 68, the receiver 64 in the reception side block 62 includes three sets of reception FF groups for even (69-0-1, 69-0-2, 69-0-3). ) And 4 sets (69-1-1, 69-1-2, 69-1-3, 69-1-4) for odd of the reception FF group. The inter-block clock that has reached the receiving block 62 is transmitted to the VDL 68 and the clock phase detector 67. The VDL 68 is other than the receiving FF group even3 (69-0-3) and the receiving FF group odd4 (69-1-4). The clocks of the FF groups (69-0-1, 69-0-2, 69-1-1, 69-1-2, 69-1-3) are created.

  The reception FF group even1 (69-0-1) uses a clock obtained by delaying the received inter-block clock by 90 °, and the reception FF group odd1 (69-1-1) uses a clock obtained by inverting the clock. The reception FF group odd2 (69-1-2) is used to synchronize data shifted by 180 ° with the even-side clock using the same clock as the even-side. The subsequent reception FF group even2 (69-0-2), reception FF group even3 (69-0-3), reception FF group odd3 (69-1-3), reception FF group odd4 (69-1-4) The reception FF group 2 (39-2) and the reception FF group 3 (39-3) in FIG. 3 are functionally the same, and are used to adjust the phase to the clock of the reception side block 62.

(Configuration Example 6 of Transmitter / Receiver 2 when DDR is used 2)
FIG. 7 is a block diagram showing an example of the transmitter / receiver of the present invention. The configuration shown in FIG. 7 is an inter-block interface that uses the same DDR as in FIG. 6A, and the same components as those in FIG. 7 differs from FIG. 6A in that the transmitter 73 of the transmission side block 71 is provided with a transmission clock 90 ° phase shifter 76-1, and the output clock is already 90 ° out of phase. Therefore, the up / down edge of the inter-block clock comes to the center of the data window on the inter-block interface 60. Therefore, the receiver 74 in the reception side block 72 uses the received inter-block clock as it is for the reception FF group even1 (69-0-1), and further receives the clock obtained by inverting the received inter-block clock as the reception FF. It is used as a clock for the group odd1 (69-1-1). 6-1 and FIG. 7 differ only in this clock structure.

(Example 7 of transmitter / receiver configuration ... when QDR is used)
FIG. 8-1 is a block diagram showing an example of the transmitter / receiver of the present invention. FIG. 8B is a time chart of data transfer with the configuration of FIG. The configuration illustrated in FIG. 8A is an example in the case of Quad-Data-Rate (QDR) that transmits four data in one clock. The transmission side block 81 includes a transmitter 83, in which transmission side FF groups 0 to 3 (85-0 to 85-3) are provided, and a 4: 1 multiplexer 86-2 is provided at the output destination. Provided. The multiplexer 86-2 is controlled by a multiplexer selection signal generation circuit 86-3.

  The multiplexer selection signal generation circuit 86-3 transmits a cyclic selection signal of 0 → 1 → 2 → 3 → 0 to the multiplexer 86-2 at a speed four times the clock of the transmission side block 81, and receives a 4-bit input. Serialize to 1 bit at 4x speed. The 4 × speed cyclic selection signal may be generated based on a 4 × clock in the multiplexer selection signal generation circuit 86-3, or may be externally supplied to the multiplexer selection signal generation circuit 86-3. A double clock may be input. However, it must be shown that D0 is synchronized with the rising edge of the transmission clock and that the rising edge of the interblock clock is D0 on the interblock interface 80.

  The structure of the receiving side block 82 is basically the same as the configuration example of the DDR shown in FIGS. 6A and 6B, but in the configuration example of FIG. Clock / latch enable generation circuit 87-2 generates a quadruple clock and enable signal for the first-stage reception FF group (89-0-0, 89-1-0, 89-2-0, 89-3-0). Is generated. Similar to the multiplexer selection signal generation circuit 86-3 of the transmission side block 81, the reception clock / latch enable generation circuit 87-2 may internally generate a latch enable signal that operates at four times the clock frequency. However, it is also possible to obtain a reference four times the clock from the outside.

  Then, the reception clock / latch enable generation circuit 87-2, based on the phase information of the inter-block clock, receives a quadruple clock that can successfully receive quadruple-speed data and data transferred at the rise of the inter-block clock. And D0 at the next quadruple clock, and D2 at the next, and a function to create a latch enable that can receive data sent at quadruple speed. In the cycle in which all of D0 to D3 are stored in the first-stage reception FF group 89-0-0, 89-1-0, 89-2-0, 89-3-0), the next-stage FF group (89- 0-1, 89-1-1, 89-2-1, 89-3-1) are given clocks, and 4-bit data is taken in as parallelized 1-clock data.

  Thereafter, the data is sent into the receiving side block 82 in synchronization with the clock of the receiving side block 82. In this case as well, the third-stage FF group (89-0-2, 89-1-) is used so that the clocks of the transmitting side block 81 and the receiving side block 82 for communication can maintain a completely free phase relationship. 2, 89-2-2, 89-3-2) and the fourth stage FF group (89-0-3, 89-1-3, 89-2-3, 89-3-3) is there.

  As described above, by using DDR or QDR synchronized with the clock for the inter-block interface, the number of signals of the inter-block interface can be reduced.

(Configuration Example 8 of Transmitter / Receiver: When CDR is Used)
FIG. 9 is a block diagram showing an example of the transmitter / receiver of the present invention. The configuration shown in FIG. 9 is an example of clock data recovery (CDR) different from the source synchronous that transmits the clock and data simultaneously as described above. When it is desired to send data at a higher speed than QDR, it is difficult to maintain the correct relationship between the clock signal and the data signal in terms of circuit. Therefore, a clock data recovery technique for embedding a clock signal in data is used.

  In the following example, an example of a CDR circuit in the case of receiving quadruple speed data equivalent to QDR will be described, but it is naturally possible to cope with a higher data rate. When the serialized data enters the receiver 90, the data is taken in by a plurality of FF groups (91-0 to 91-8) having different latch timings. The plurality of different latch timings are achieved by supplying clocks having different timings by the optimum CLK generation circuit 92. In this example, a clock that is shifted by 1/8 of one cycle is supplied.

  Since the input Data_in is latched by the plurality of FFs, when Data_in changes, a change is observed somewhere in one of the FF groups (91-0 to 91-8). The change is observed by the input data phase detection edge detection circuit 93. A change point is detected by the EORs 94-0 to 94-7 in the edge detection circuit 93 for detecting the input data phase, and the location of the change point is stored by the edge detection circuit 95 having hysteresis. The reason for having hysteresis is to prevent the detected change point from fluctuating frequently.

  In the example of FIG. 9, if a change is observed between the FF groups 91-2 and 91-3, the input data phase detection edge detection circuit 93 is most stable at the FF 91-8 far from the input data phase detection edge detection circuit 93. The location is transmitted to the optimum CLK generation circuit 92, and the optimum CLK generation circuit 92 gives an instruction to the selector 96 so that the output of the FF 91-8 is selected.

  Thereafter, the optimum CLK generation circuit 92 generates a clock four times as large as the description of FIG. 8 and generates a latch enable corresponding to the clock, thereby generating the first stage FF group (99-0-0, 99). -0-1, 99-0-2, 99-0-3). When data is stored in these four first stage FF groups (99-0-0, 99-0-1, 99-0-2, 99-0-3), the next stage FF group (99-1- 0, 99-1-1, 99-1-2, 99-1-3), and further in order to synchronize with the receiving side clock, the third stage FF group (99-2-0, 99) -2-1, 99-2-2, 99-2-3) and the fourth stage FF group (99-3-0, 99-3-1, 99-3-2, 99-3-3) After that, data is sent in the receiving block. However, unlike the case of DDR / QDR, since only the above circuit does not know which serialized data is at the head of parallel data, it is usually detected using a training pattern or the like ( A specific circuit is omitted).

  As described above, according to the CDR method, the inter-block interface signal can be further reduced as compared with DDR and QDR.

(Example 9 of receiver configuration: example of eliminating clock cycle deviation between received data bits)
FIG. 10 is a block diagram showing an example of the receiver of the present invention. When creating a source-synchronous interface in a semiconductor integrated circuit, clocks and data are arranged as much as possible to have the same drive capability and the same wiring length / wiring layer, and the propagation delay error is reduced. However, this is an example of a circuit that eliminates the shift when it cannot be done and a timing shift occurs due to bits. In the reception side block 100, any one of the receivers 101 described as the respective configuration examples is arranged. Then, as shown in FIG. 10, a bit alignment block 102 is added in the receiving side block 100 just inside the receiver 101.

  The bit alignment block 102 uses a training mode (training_mode). For this reason, the transmitting block is added with a function in which all output data bits are High during training_mode and a function in which all output data bits are Low for 7 cycles. In the receiving side block 100, the reception data output from the receiver 101 is taken into the bit alignment control block 103, and it is detected whether there is any bit shift. When the bit alignment control block 103 detects a 1-bit shift, the bit that arrived early is once taken into the FF (104-0 to 104-3) and delayed by one cycle, and the data that arrived in the next cycle is The multiplexers (105-0 to 105-3) are controlled so as to output directly. As a result, bit shift alignment can be achieved. The sample code described in the block of the bit alignment control block 103 is an example of control logic (control software) of this circuit. According to the above configuration, the bit shift can be automatically corrected using the training pattern.

  According to each configuration example described above, when a semiconductor integrated circuit is hierarchically designed, a source synchronous receiving circuit of a mesochronous type (when the frequency is the same and only the phase is unknown) is included in each lower block. The transmission-side lower block transmits a data / control signal together with its own clock, and the reception-side lower block receives these clock / data / control signals by a mesochronous type source synchronous reception circuit. As a result, the timing design can be completed independently for each lower block, and the upper block including the lower block can transmit the transmission clock and the data / control signal of the interface signal group between the blocks without worrying about the timing of each lower block. The design of the upper block can be completed as long as the relative delay (ie, skew between the source clock and the data / control signal) is designed to fall within a certain range, and the entire semiconductor integrated circuit can be fitted with the lower block in the upper block. The design can be completed and the design period can be shortened by designing the lower block and the upper block completely separately.

(Example 1 of clock control for each block in a semiconductor integrated circuit)
FIG. 11 is a block diagram for controlling the clock for each block in the semiconductor integrated circuit of the present invention. FIG. 7 shows how the clocks are shifted when the clocks of BLK0 to BLK9 (116-0 to 116-9), which are lower blocks of the semiconductor integrated circuit 111, are arbitrarily shifted by the above-described configurations. 11 shows. As a method of arbitrarily delaying the clock, an intentional delay is added by the PLL 114 or the DLL / VDL 115 in the clock generation circuit 112. Alternatively, the delay element 113-2 is arranged inside the clock generation circuit 112 as the delay element 113-1 or the upper block of the lower block BLK 1 (116-1).

(Example 2 of clock control for each block in a semiconductor integrated circuit)
FIG. 12 is a block diagram for controlling the clock for each block in the semiconductor integrated circuit of the present invention. The configuration of FIG. 12 is an example of a clock control method for a lower block and an example in which an intelligence function is provided in power supply noise reduction. In the semiconductor integrated circuit 121, a plurality of power supply noise measurement circuits 1 to 5 (125-1 to 125-5) are arranged. When the plurality of lower blocks BLK1 to BLK4 (126-1 to 126-4) are operated with the clocks delayed by the VDLs 123-1 to 123-4 in the clock generation circuit 122, the power supply noise measurement circuit 1 The clock delay control circuit 124 controls the VDLs 123-1 to 123-4 so that the power supply noise detected by .about.5 (125-1 to 125-5) is reduced.

  According to the configuration of the above control examples 1 and 2, when clock wiring to the lower block of the upper block, a different clock delay is intentionally given to the clock given to each lower block, and the FF in each lower block has a different timing. As a result, the operation timing of the FF as the entire semiconductor integrated circuit can be shifted. As a result, the difference between the maximum and minimum power consumption can be flattened / reduced as compared to the case where all the FFs in all the semiconductor integrated circuits operate simultaneously. At the same time, the power supply noise of the semiconductor integrated circuit can be reduced and the EMI can be reduced, so that the number of power supply pins and the area required for the on-chip capacitor, which have been conventionally required, can be reduced, and the size of the semiconductor integrated circuit can be reduced. The cost of the integrated circuit can be reduced. Furthermore, the number of external bypass capacitors for power supply noise / EMI countermeasures mounted on the package / printed circuit board on which the conventional semiconductor integrated circuit is mounted can be reduced, thereby reducing the cost of the package / printed board module. It becomes.

  The configuration of the semiconductor integrated circuit described above can be determined at the time of designing the semiconductor integrated circuit. This method for designing a semiconductor integrated circuit can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Supplementary note 1) A semiconductor integrated circuit characterized in that the interface between the hierarchized blocks is of a source synchronous type for simultaneously sending a clock and data.

(Supplementary note 2) A mesochronous type synchronization circuit is provided in the block on the receiving side, the interface data is received without a setup / hold violation, and is transferred to an internal circuit of the block on the receiving side. The semiconductor integrated circuit according to appendix 1.

(Supplementary Note 3) The interface between the blocks uses DDR (Double-Data-Rate) or QDR (Quad-Data-Rate) synchronized with the clock to reduce the number of inter-block interface signals. The semiconductor integrated circuit according to appendix 1.

(Supplementary note 4) The block on the transmission side and the block on the reception side are of a mesochronous type and use a CDR (Clock-Data-Recovery) method in which a clock is embedded in the data without using a clock line, and an inter-block interface The semiconductor integrated circuit according to appendix 1, wherein the number of signals is reduced.

(Appendix 5) Using a high-speed source synchronous interface as an interface between the blocks,
The semiconductor integrated circuit according to appendix 1, wherein the block on the receiving side includes bit alignment means for correcting a bit shift by a predetermined training pattern.

(Additional remark 6) The said block is operated with an independent clock, The delay means which gives a clock with a different phase to each said block is provided, The difference of the power consumption in 1 clock of the whole circuit is planarized, It is characterized by the above-mentioned. The semiconductor integrated circuit according to any one of appendices 1 to 5.

(Supplementary note 7) A method for designing a semiconductor integrated circuit, wherein an interface between layered blocks is designed as a source synchronous type for simultaneously sending a clock and data.

  As described above, the semiconductor integrated circuit and the semiconductor integrated circuit design method according to the present invention are useful for timing convergence between blocks in a large-scale integrated circuit using a large number of FFs, and in particular, a large number of FFs are used. Suitable for LSI design.

It is a figure which shows the structural example of the semiconductor integrated circuit by embodiment of this invention. It is a block diagram which shows an example of the transmitter / receiver of this invention. It is a block diagram which shows an example of the transmitter / receiver of this invention. It is a block diagram which shows an example of the receiver of this invention. It is a block diagram which shows an example of the receiver of this invention. It is a block diagram which shows an example of the transmitter / receiver of this invention. 6 is a time chart of data transfer according to the configuration of FIG. It is a block diagram which shows an example of the transmitter / receiver of this invention. It is a block diagram which shows an example of the transmitter / receiver of this invention. It is a time chart of the data transfer by the structure of FIGS. It is a block diagram which shows an example of the transmitter / receiver of this invention. It is a block diagram which shows an example of the receiver of this invention. It is a block diagram which controls a clock for every block in the semiconductor integrated circuit of this invention. It is a block diagram which controls a clock for every block in the semiconductor integrated circuit of this invention.

Explanation of symbols

10 Semiconductor Integrated Circuit 11-1 to 11-5 Lower Block (BLK1 to BLK5)
12-1 to 12-5 Core logic 13-1 to 13-5 Clock tree 14 Clock generation circuit 15-1-5, 15-5-1, 15-5-3, 15-3-5 Source synchronous receiver 16-1-5, 16-5-1, 16-5-3, 16-3-5 Source synchronous transmitter 17 Interface between synchronous blocks

Claims (5)

  A semiconductor integrated circuit characterized in that the interface between the hierarchized blocks is a source synchronous type that simultaneously sends a clock and data.   2. The block on the receiving side is provided with a mesochronous type synchronization circuit, receives the data of the interface without any setup / hold violation, and transfers it to the internal circuit of the block on the receiving side. A semiconductor integrated circuit according to 1.   2. The semiconductor integrated circuit according to claim 1, wherein the number of interface signals between the blocks is reduced by using DDR or QDR synchronized with the clock for the interface between the blocks.   A delay means for operating the blocks with independent clocks and supplying clocks with different phases to the blocks, and flattening a difference in power consumption within one clock of the entire circuit. 4. The semiconductor integrated circuit according to any one of 3 above. A method for designing a semiconductor integrated circuit, wherein an interface between layered blocks is designed as a source synchronous type that simultaneously sends a clock and data.

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