JP2002108809A - Method and device for transferring source synchronous data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily and exactly transfer data between LSIs. SOLUTION: After making transferred data synchronize with a system clock on a sending side, a sending side LSI 10 sends it to an LSI 20 on a receiving side through a data line 30. In parallel to this, the LSI 10 generates a source clock by making a definer signal (a signal having 1/m frequency of an external clock and 1:m-1 duty ratio) synchronize with the system clock on the sending side and sends it to the LSI 20 through a source clock line 40. The line 30 and the line 40 have the same delay quantity. The LSI 20 generates a phase- matched system clock on the receiving side by matching the phase of the system clock on the receiving side with that of the source clock. Then, data from the LSI 10 is stored in an FIFO circuit 22 consisting of m-stages synchronizing with the phase-matched system clock on the receiving side, and data held in the circuit 22 is read in accordance with the system clock on the receiving side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer technique between LSIs, and more particularly, to a technique for transferring data from a sending LSI to a receiving LSI.
The present invention relates to a data transfer technique capable of transferring data to a computer at high speed and accurately.

[0002]

2. Description of the Related Art Conventionally, when data is transferred from a sending side LSI to a receiving side LSI, an external clock output from the same oscillator (oscillator) is distributed to both the sending side LSI and the receiving side LSI, and the sending side LSI is It is common practice to synchronize the transmission and reception operations of the receiving LSI with the external clock.

FIG. 5 is a block diagram of the above-mentioned conventional technology. An external clock is supplied to the sending LSI 100 and the receiving LSI 200 from the same oscillator (not shown). In the sending side LSI 100, transfer data from an internal logic circuit (not shown) is synchronized with an external clock using a D flip-flop (DF / F) 101, and then transferred to a receiving side LSI 200 via a buffer 102. . In the receiving LSI 200, the DF / F 202 to which the transfer data is input via the buffer 201 is
Captures transfer data in synchronization with an external clock.

[0004] In the prior art shown in FIG.
Data transferred to I200 and receiving LSI 200
There is no circuit guarantee for the timing relationship with the external clock supplied to the circuit. Therefore, there is no problem if the transfer cycle is much longer than the delay time, but if the transfer cycle is shorter, the D
The setup time and the hold time of the F / F 202 cannot be satisfied, and there is a possibility that accurate data transfer cannot be performed.

Further, a data transfer device as shown in the block diagram of FIG.
-214475).

In FIG. 6, a sending side LSI 300 transfers data transferred from an internal logic circuit (not shown) to a DF / F
After synchronizing with an external clock using 301, the data is transferred to the receiving LSI 400 via the buffer 302. Also,
In parallel with this, the external clock is sent to the receiving LSI 400 via the buffer 303. At this time, the data and the clock are transferred to the receiving LSI 400 using a path in which the data delay and the clock delay are equal. In the receiving LSI 400, the DF / F 401 is
The data transferred from the transmission-side LSI 30
0 according to the clock sent from DF / DF /
F402 captures the output data of DF / F401 according to the external clock and supplies the data to an internal logic circuit (not shown) that operates according to the external clock.

[0007]

According to the data transfer apparatus shown in FIG. 6, the transmission side LSI 300 and the reception side LSI
Since it is possible to guarantee the timing relationship between the data transferred to 400 and the clock, the DF / F 401 in which the data and the clock are input to the data terminal and the clock terminal respectively is used. Even if the transfer speed increases, data can be accurately captured.
However, the DF / F40 is connected to the data terminal and the clock terminal, respectively.
1 and the DF /
In F402, the timing relationship between the output data and the external clock is not guaranteed. Therefore, if the transfer cycle is shortened, the setup time and the hold time cannot be satisfied. May not be possible. That is, accurate data may not be supplied to the internal logic circuit.

Therefore, a main object of the present invention is to provide a feeder LS
An object of the present invention is to enable high-speed and accurate data transfer from I to a receiving LSI.

[0009]

In order to achieve the above object, a source synchronous data transfer method according to the present invention is a source synchronous data transfer method for transferring data from a sending LSI to a receiving LSI. Sending LSI
A process of synchronizing transfer data to the receiving LSI with a sending system clock supplied from outside, and transferring the data to the receiving LSI via a data line; / M (m is an integer of 2 or more) and a duty ratio of 1: (m-1)
Generating a source clock by synchronizing an externally supplied refiner signal with the transmission side system clock, and transmitting the source clock to the receiving side via a source clock line having the same delay amount as the data line. L
And transmitting the same to the source LSI. The source LSI receives, from the source LSI, a phase of the destination system clock supplied from the outside and having the same frequency as the source system clock supplied from outside. A process of generating a phase-matched receiving system clock by adjusting the phase of the clock, and an m-stage FIFO circuit,
A process of storing transfer data transferred from the sending LSI in synchronization with the phase-matched receiving system clock, and reading data stored in the FIFO circuit in synchronization with the receiving system clock; And processing.

According to this configuration, the transfer data and the source clock synchronized with the transmission side system clock are transmitted from the transmission side LSI to the reception side LSI via the data line and the source clock line (having the same delay amount), respectively. The timing relationship between the data sent to the receiving LSI and the source clock can be guaranteed. Therefore, the FIFO circuit that holds data from the sending LSI in synchronization with the phase-matched receiving system clock can hold accurate data even if the data transfer speed is high. Further, since data is read from the FIFO circuit according to the external clock, correct data can be supplied to the internal logic circuit operating according to the external clock.

As a device suitable for carrying out the above method, the source synchronous data transfer device of the present invention comprises:
A source synchronous data transfer device for transferring data from a sending side LSI to a receiving side LSI, wherein the sending side L
A data output circuit that outputs transfer data to the receiving LSI in synchronization with a sending system clock supplied from the outside;
After synchronizing an externally supplied refiner signal having a frequency of m (m is an integer of 2 or more) and a duty ratio of 1: (m-1) to the transmission side system clock,
A source clock generating circuit for outputting as a source clock, a data line for transferring transfer data output from the data output circuit to the receiving LSI, and a source line for outputting a source clock output from the source clock generating circuit to the receiving side. The source clock line sent to the LSI has the same delay amount, and the receiving LSI sends from the sending LSI a phase of the receiving system clock supplied from the outside and having the same frequency as the sending system clock. A DLL circuit that generates a phase-matched receiving system clock by adjusting the phase of the source clock that has been obtained, and a phase-locked receiving system clock that is generated by the DLL circuit. While holding the transfer data, hold and hold in synchronization with the receiving system clock. F m-stage configuration for outputting are data
An IFO circuit.

Further, the source synchronous data transfer device of the present invention can reduce the size of the receiving LSI.
The receiving LSI shifts a source clock sent from the sending LSI in accordance with the phase-matched receiving system clock, thereby obtaining the FIFO.
A write address generation circuit comprising an m-stage shift register for generating a write address for a circuit; and an m-stage shift circuit for generating a read address for the FIFO circuit by shifting the definer signal in accordance with the receiving system clock. A read address generation circuit comprising a register.

According to this configuration, the write address generation circuit and the read address generation circuit are realized by the shift register having a small area.
Can be reduced in size.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. As shown in FIG. 1, the sending side LSI 10 and the receiving side L
The same external clock and the same definer (reference) signal are supplied to the SI 20. The frequency of the definer signal is 1 / m (m is an integer of 2 or more) of the external clock.
In addition, the signal is "Hi": "Low" = 1: (m-1). Here, m has the same value as the number of stages of the FIFO 22 in the receiving LSI 20 described later. Further, it is desirable to generate the definer signal by dividing the external clock in order to accurately set the frequency to 1 / m of the external clock.

The sending side LSI 10 includes a DF / F 11, a buffer 12, a source clock generation circuit 13, and a buffer 14.

The DF / F 11 has its data terminal input with transfer data from an internal logic circuit (not shown), and has its clock terminal connected to a sending system clock (sending LSI 1).
The external clock input to 0 is called a sending system clock), and the transfer data is synchronized with the sending system clock. The buffer 12 has D
The transfer data output from the F / F 11 is output to the data line 30.

The source clock generation circuit 13 synchronizes the refiner signal with the transmission side system clock,
Output as source clock. The buffer 14 outputs a source clock output from the source clock generation circuit 13 to a source clock line 40. Note that data line 3
0, the source clock line 40 has the same delay amount. More specifically, using the same media (printed wiring board, cable, connector, etc.), the data line 3
0, by configuring the source clock line 40, the sending side LSI 10 of the data line 30 and the source clock line 40,
The delay amount between the receiving LSIs 20 is made the same.

The receiving LSI 20 includes a buffer 21 and an F
IFO (First-In-First-Out: First-In-First-Out) circuit 22, DF / F 23, and buffer 24
And DLL (Delay Lock Loop) circuit 2
5, a write address generation circuit 26, and a read address generation circuit 27.

The DLL circuit 25 is a circuit for adjusting the phase of the input signal to the phase of the Ref signal using a delay line. In the present embodiment, the DLL circuit 2
5 adjusts the phase of the receiving system clock (referred to as the receiving system clock receiving the external clock input to the receiving LSI 20), which is the input signal, to the phase of the source clock input as the Ref signal. FIG. 2 shows the DLL.
4 shows a configuration example of a circuit 25. The DLL circuit 25 outputs a FeedBack signal (DLL circuit 2) by the phase comparator 251.
5 is compared with the phase of the Ref signal (source clock), and the control circuit 252 outputs an error signal corresponding to the phase difference.
To enter. The control circuit 252 adjusts the phase of the receiving system clock so that the phase difference is eliminated by changing the delay amount of the delay line 253 having a variable delay amount according to the error signal.

The write address generation circuit 26 outputs the received system clock (phase-matched receiving system clock) output from the DLL circuit 25 after the phase matching with the source clock, and via the buffer 24. Based on the added source clock, an m-stage F
A write address in synchronization with the phase-adjusted receiving system clock, in which each stage of the IFO circuit 22 is cyclically set as a write position, is generated. The read address generation circuit 27
Based on the definer signal and the receiving-side system clock, a read address synchronized with the receiving-side system clock is generated, in which each stage of the m-stage FIFO circuit 22 is cyclically set as a read position.

The FIFO circuit 22 indicates the transfer data added via the buffer 21 by the write address from the write address generation circuit 26 in synchronization with the phase-matched receiving system clock output from the DLL circuit 25. Store in column. Also, FIFO circuit 2
2 outputs the data stored in the stage indicated by the read address output from the read address generation circuit 27.

The DF / F 23 receives the output data of the FIFO circuit 22 in synchronization with the system clock on the receiving side.
It is supplied to an internal logic circuit (not shown). DF / F2
3, the data output from the FIFO circuit 22 may be directly supplied to the internal logic circuit.

[0024]

Next, the operation of this embodiment will be described.

In the sending side LSI 10, the DF / F 11
After synchronizing the transfer data from the internal logic circuit with the transmission side system clock, the buffer 12 and the data line 3
0 to the receiving-side LSI 20. In parallel with this, the source clock generation circuit 13 generates a source clock by synchronizing the definer signal with the transmission side system clock, and transfers it to the reception side LSI 20 via the buffer 14 and the source clock line 40. Here, the transfer data and the source clock are both synchronized with the transmission side system clock, and the data line 30 and the source clock line 40 have the same delay amount as described above. The timing relationship between the data transferred to the LSI 20 and the source clock is guaranteed in terms of the circuit.

The DLL circuit 25 in the receiving LSI 20 is
By adjusting the phase of the receiving system clock to the phase of the source clock, a phase-matched receiving system clock is generated and supplied to the FIFO circuit 22 and the write address generating circuit 26.

The write address generation circuit 26 is provided with a source clock applied via the buffer 24 and the DLL circuit 2.
5, a write address synchronized with the phase-adjusted receiving system clock, in which each stage of the m-stage FIFO circuit 22 is cyclically set to the write position based on the phase-adjusted receiving system clock output from Generate
It is supplied to the FIFO circuit 22.

The FIFO circuit 22 synchronizes the transfer data applied via the buffer 21 with the phase-matched receiving system clock output from the DLL circuit 25 by using the write address output from the write address generation circuit 26. Store in the indicated column. Where FI
The receiving system clock, which has been phase-aligned with the transfer data to be applied to the FO circuit 22, is synchronized with the source clock, so that the FIFO circuit 22 ensures that correct data is transmitted even when the data transfer speed is high. Is stored.

On the other hand, the read address generation circuit 27 generates the read address based on the receiving side system clock and the definer signal.
A read address synchronized with the receiving-side system clock is generated to cyclically set each stage of the m-stage FIFO circuit 22 to the read position, and is supplied to the FIFO circuit 22.

The FIFO circuit 22 outputs data stored in the stage indicated by the read address from the read address generation circuit 27. DF / F23 is FI
The data output from the FO circuit 22 is captured in synchronization with the receiving side system clock and output to the internal logic circuit. Here, the read address supplied to the FIFO circuit 22 is synchronized with the receiving system clock, and the data output from the FIFO circuit 22 is synchronized with the receiving system clock. DF / F2 to take in data in synchronization with clock
In No. 3, accurate data can be taken in reliably.

[0031]

Next, embodiments will be described in detail. FIG.
FIG. 2 is a block diagram of an example of the embodiment shown in FIG.

Referring to FIG. 3, the same external clock and the same definer signal are supplied to the sending LSI 10 and the receiving LSI 20. In this embodiment, since the FIFO circuit 22 has a four-stage configuration, as will be described later, the definer signal is a signal whose frequency is １ ／ of the external clock and “Hi”: “Low” = 1: 3. Become.

The sending side LSI 10 includes a DF / F 11 for synchronizing transfer data from an internal logic circuit (not shown) with a sending side system clock, a buffer 12, and a source clock generation circuit 13 composed of a DF / F. , A buffer 14. A source system clock is input to a clock terminal of the DF / F constituting the source clock generation circuit 13, and a definer signal is input to a data terminal.

The receiving side LSI 20 includes a buffer 21 and 4
It has a staged FIFO circuit 22, a DF / F 23, a buffer 24, a DLL circuit 25, a write address generation circuit 26, and a read address generation circuit 27.

The write address generation circuit 26 converts the source clock output from the buffer 24 into a DLL circuit 25
This is realized by a 4-bit shift register that shifts according to the phase-matched receiving-side system clock output from. This shift register has four DF /
F261-264, each DF / F261-2
64 are the second bit b, the third bit c, the fourth bit d, and the first bit a of the write address, respectively.
Becomes

The read address generating circuit 27 shifts the definer signal in accordance with the receiving side system clock.
This is realized by a shift register having a bit configuration. This shift register is composed of four DF / Fs 271 to 274, and the outputs of the DF / Fs 271 to 274 output the second bit B, the third bit C, and the third bit C, respectively, of the read address.
The fourth bit D and the first bit A are provided.

The four-stage FIFO circuit 22 includes DF / Fs 221 to 224 corresponding to the first to fourth stages, and
Selectors 225 to 228 for each of the F / Fs 221 to 224;
Buffers 229 to 232 for each DF / F 221 to 224
And

Each of the selectors 225 to 228 outputs one of the transfer data added via the buffer 21 and the output data of the DF / Fs 221 to 224 corresponding to its own selector from the write address generation circuit 26. First bit a to fourth bit d of the write address to be output
Select according to. In this embodiment, each selector 225 to
228, the transfer data output from the buffer 21 is selected when the first bit a to the fourth bit d of the write address output from the write address generation circuit 26 are “Hi”, and when the first bit a to the fourth bit d are “Low”, , Corresponding DF / F
Output data 221 to 224 are selected.

Each of the DF / Fs 221 to 224 has a D
The outputs of the selectors 225 to 228 are captured in synchronization with the phase-matched receiving system clock output from the LL circuit 25.

Each of the buffers 229 to 232 is activated only when the first bit A to the fourth bit D of the read address output from the read address generation circuit 27 are “Hi”, and the corresponding DF / F 221 to 232 is set. 224 output data is supplied to the DF / F 23.

[0041]

Next, the operation of this embodiment will be described in detail with reference to the timing chart of FIG.

The DF / F 11 in the sending-side LSI 10 synchronizes the transfer data from the internal logic circuit with the sending-side system clock shown in FIG. Transfer to the receiving LSI 20. The transfer data output from the DF / F 11 is shown in FIG.
(C) is obtained.

The source clock generation circuit 13 in the sending side LSI 10 synchronizes the definer signal shown in FIG. 4B with the sending side system clock shown in FIG. Is generated, and the source clock is sent to the receiving side LSI 20 via the buffer 14 and the source clock line 40.

The transfer data and source clock from the sending side LSI 10 are sent to the receiving side LSI 20 via the data line 30 and the source clock line 40 having the same delay amount, so that the buffers 21 and 24 in the receiving side LSI 20 The output transfer data and source clock are shown in FIG.
(E) and (F) are synchronized.

The DLL circuit 25 adjusts the phase of the receiving side system clock shown in FIG. 4 (P) to the phase of the source clock shown in FIG. 4 (F), and adjusts the phase of the receiving side system shown in FIG. 4 (G). Output clock. The phase-matched receiving system clock is supplied to the FIFO circuit 22 and the write address generation circuit 26. here,
The phase-matched receiving system clock generated by the DLL circuit 25 is supplied to the FIFO circuit 22 because the data sent from the sending LSI 10 and the receiving system clock not synchronized with the source clock are used as they are. This is because when input to the FIFO circuit 22, racing may occur.

The write address generation circuit 26 has four D addresses.
Using a shift register composed of F / Fs 261 to 261, the source clock shown in FIG.
By shifting in accordance with the phase-adjusted receiving-side system clock shown in (G), the write address shown in FIGS. The first bit a, the second bit b, the third bit c, and the fourth bit d of the write address are shown in FIGS. 4 (K), (H), (I),
(J). However, in order to avoid multiple inputs to the DF / Fs 221 to 224 constituting the FIFO circuit 22, these must be initialized before the operation. This is performed by a reset signal.

Each of the DF / Fs 221 to 221 in the FIFO circuit 22
224 correspond to FIGS. 4 (K), (H), (I),
When the first bit a to the fourth bit d of the write address shown in (J) are "Hi", in order to capture data at a more effective point, the phase-adjusted receiving system shown in FIG. Data is captured at the falling edge of the clock. Therefore, the transfer data d1, d shown in FIG.
, D3, d4, d5,.
F / F221, DF / F222, DF / F223, DF
/ F224, DF / F221,..., And are held for four cycles. Therefore, DF / Fs 221 to 22
4 are output data shown in FIGS.
(N).

On the other hand, the read address generation circuit 27
4 (R) by shifting the definer signal shown in FIG. 4 (Q) according to the receiving side system clock shown in FIG. 4 (P) using a shift register composed of DF / Fs 271 to 274. (U) are generated. The first bit A, the second bit B to the fourth bit D of the read address are respectively shown in FIG.
(U) and (R) to (T). However, FI
In order to avoid a multiselect in which the outputs of the DFs / Fs 221 to 224 constituting the FO circuit 22 cause bus fight, it is necessary to initialize the DFs / Fs 221 to 224 before the operation. This is the write address generation circuit 2
This is performed by a reset signal in the same manner as 6.

Buffers 229-2 in FIFO circuit 22
32, the first bit A to the fourth bit D of the read address shown in FIGS. 4 (U) and (R) to (T) are "H", respectively.
At the time of "i", the circuit becomes conductive. As a result, the FIFO circuit 2
Data d1, d2, d3, d4, d5,... From FIG.
It is output as shown in (V).

The DF / F 23 converts the data d1, d2, d3, d4, d5,.
It is taken in according to the receiving side system clock shown in FIG. 4 (P) and sent to the internal logic circuit. As a result, the data shown in FIG. 4 (W) is sent to the internal logic circuit.

In the embodiment described above, the feed side L
The case where serial data is transferred from the SI 10 to the receiving LSI 20 has been described as an example, but the present invention can of course be applied to the case where parallel data is transferred.
However, in the case of transferring n-bit parallel data, the sending side LSI 10 is provided with n DF / Fs 11 and buffers 12 corresponding to each bit of the parallel data, and the receiving side LSI 20 has one stage. n-bit FIF
O circuit 22 and n corresponding to each bit of the parallel data
It is necessary to provide DF / Fs 23.

In the above-described embodiment, the write address generation circuit 26 and the read address generation circuit 27 are constituted by using a 4-bit shift register.
It may be configured using a binary counter or the like. However, when the write address generation circuit 26 and the read address generation circuit 27 are configured using shift registers as in the embodiment, the area of the write address generation circuit 26 and the read address generation circuit 27 on the LSI is reduced. It is desirable because it can be.

[0053]

As described above, according to the present invention, the transmission data and the source clock synchronized with the transmission side system clock are transmitted from the transmission side LSI to the reception side LSI by the data line and the source clock line having the same delay amount. In the receiving LSI, the transfer data is held in the FIFO circuit in synchronization with the phase-matched receiving system clock whose phase has been adjusted to the source clock, and the data held in the FIFO circuit is read in accordance with the external clock.
Even if the data transfer speed is high, accurate data can be reliably received.

Further, according to the present invention, the write address and the read address for the FIFO circuit are generated using the shift register, so that it is possible to reduce the size of the receiving LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a DLL circuit 25.

FIG. 3 is a block diagram of an example of an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG. 3;

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is a block diagram of another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Sending side LSI 11 ... DF / F 12 ... Buffer 13 ... Source clock generation circuit 14 ... Buffer 20 ... Receiving side LSI 21 ... Buffer 22 ... FIFO circuit 221-224 ... DF / F 225-228 ... Selector 229-232 ... Buffer 23 DF / F 24 Buffer 25 DLL circuit 251 Phase comparator 252 Control circuit 253 Delay line 26 Write address generation circuits 261 to 264 DF / F 27 Read address generation circuits 271 to 274 DF / F 30 data line 40 source clock line 100 sending LSI 101 DF / F 102 buffer 200 receiving LSI 201 buffer 202 DF / F 300 sending LSI 301 DF / F 302, 303 ... Buffer 400 ... Receiver LSI 401,4 2 ... DF / F

Claims (6)

[Claims] 1. A source synchronous data transfer method for transferring data from a sending LSI to a receiving LSI, wherein the sending LSI sends the transfer data to the receiving LSI from outside. A process of synchronizing with the receiving side system clock and then transferring it to the receiving side LSI via a data line; and having a frequency of 1 / m (m is an integer of 2 or more) of the sending side system clock and a duty ratio of 1: (m-1)
Generating a source clock by synchronizing an externally supplied refiner signal with the transmission side system clock, and transmitting the source clock to the receiving side via a source clock line having the same delay amount as the data line. L
And transmitting the same to the SI. The source LSI receives the externally supplied phase of the receiving system clock having the same frequency as the transmitting system clock supplied from the outside in the receiving LSI. Generating a phase-matched receiving-side system clock by adjusting the phase of the clock; and transmitting the transfer data transferred from the sending-side LSI to the phase-matched receiving-side system clock to an m-stage FIFO circuit. A source synchronous data transfer method, comprising: performing a process of storing data in synchronization with the data; and a process of reading data stored in the FIFO circuit in synchronization with the receiving system clock. 2. The source synchronous data transfer method according to claim 1, wherein the receiving LSI shifts a source clock sent from the sending LSI in accordance with the phase-matched receiving system clock. Generating a write address for the FIFO circuit, and shifting the definer signal in accordance with the receiving system clock to generate a read address for the FIFO circuit. 3. A source synchronous data transfer device for transferring data from a sending side LSI to a receiving side LSI, wherein the sending side LSI sends the transfer data to the receiving side LSI from an external source. A data output circuit that outputs in synchronization with a system clock; and a frequency of 1 / m (m is an integer of 2 or more) of the transmission side system clock and a duty ratio of 1: (m-1).
A source clock generation circuit that synchronizes a refiner signal supplied from the outside with the transmission side system clock and then outputs the same as a source clock, and transfers the transfer data output from the data output circuit to the reception side LSI. A data line to be transferred to the receiving side L and a source clock output from the source clock generating circuit to the receiving side L
The source clock line to be sent to the SI has the same delay amount, and the receiving LSI sends from the sending LSI a phase of the receiving system clock supplied from the outside and having the same frequency as the sending system clock. A DLL circuit that generates a phase-matched receiving-side system clock by adjusting the phase of the source clock that has been acquired, and a phase-locked receiving-side system clock generated by the DLL circuit in synchronization with the transmission-side LSI clock. An m-stage FIF for holding transfer data and outputting the held data in synchronization with the receiving side system clock
A source synchronous data transfer device comprising an O circuit. 4. The source synchronous data transfer device according to claim 3, wherein the receiving LSI shifts a source clock sent from the sending LSI in accordance with the phase-matched receiving system clock. And a write address generation circuit comprising an m-stage shift register for generating a write address for the FIFO circuit, and a read address for the FIFO circuit by shifting the definer signal in accordance with the receiving system clock. A source synchronous data transfer device, comprising: a read address generation circuit including a shift register having a stage configuration. 5. The source synchronous data transfer device according to claim 4, wherein the source clock generation circuit includes a DF in which the refiner signal is input to a data terminal and the transmission side system clock is input to a clock terminal. / F, the source synchronous data transfer device. 6. The source synchronous data transfer device according to claim 5, wherein the receiving LSI includes a data receiving circuit that captures data output from the FIFO circuit in synchronization with the receiving system clock. A source synchronous data transfer device.