CN109307833A - Apparatus for testing chip and chip detecting method - Google Patents
Apparatus for testing chip and chip detecting method Download PDFInfo
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- CN109307833A CN109307833A CN201811308516.7A CN201811308516A CN109307833A CN 109307833 A CN109307833 A CN 109307833A CN 201811308516 A CN201811308516 A CN 201811308516A CN 109307833 A CN109307833 A CN 109307833A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The present invention relates to a kind of apparatus for testing chip and chip detecting methods, the test machine includes multiple digital channels, the multiple digital channel is respectively connected to the development board, for carrying out bidirectional data transfers between the test machine and the development board；The test machine and the development board are respectively connected to chip to be measured.The both-way communication of test machine and development board can be realized without external private communication unit as communication unit by multiple digital channels of test machine itself for the apparatus for testing chip, and data exchange is stablized, and program development cost is effectively reduced.
Description
Technical field
The invention belongs to chip testing technology fields, and in particular to a kind of apparatus for testing chip and chip detecting method.
Background technique
Chip will carry out the final test of finished product after the completion of encapsulating factory's encapsulation.Currently used test method is certainly
It is tested in dynamic test equipment.However, in addition to test machine, the partial function of chip is needed toward contact in chip testing process
External development board such as FPGA (field programmable gate array) and processor etc. is wanted to realize some functions.And test machine with
When both external development boards act synergistically, there will be communication issue between the two.For example using traditional communication module
USB (universal serial bus) turns UART (universal asynchronous receiving-transmitting transmitter) interface module, parallel port or other communication cards, technology ratio
It is more mature, but it is more to occupy resource, and exploitation is complex, and it is long to expend the period.
For example, communicating by taking the Parallel Interface Communication of the hole DB-25 as an example using computer parallel port, 17 signal lines and 8 ground are needed
Line, signal wire are divided into 3 groups again, and every group respectively includes 4 control lines, 5 bar state lines and 8 data lines, it means that opens outside
Power Generation Road plate needs to be arranged 17 signal lines and is attached with host computer, needs to occupy more development board resources；Or
Person could complete entire communication process using the scheme that USB turns parallel port, and which further increases new hardware costs, and use
Usb protocol development difficulty increases.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of apparatus for testing chip and chip to survey
Method for testing.The technical problem to be solved in the present invention is achieved through the following technical solutions:
One aspect of the present invention provides a kind of apparatus for testing chip, including test machine and development board, wherein
The test machine includes multiple digital channels, and the multiple digital channel is connected to the development board, is used
In carrying out bidirectional data transfers between the test machine and the development board；
The test machine and the development board are respectively connected to chip to be measured.
In one embodiment of the invention, Logic control module, the logic control are provided in the development board
Molding block connects the multiple digital channel and the chip to be measured, for being referred to according to the state from the multiple digital channel
It enables and determines test vector, and the corresponding operating mode of the test vector is sent to the chip to be measured.
In one embodiment of the invention, the Logic control module includes field programmable gate array chip and control
Chip, wherein
The field programmable gate array chip connects the multiple digital channel and the control chip, for that will come from
The status command of the multiple digital channel is sent to the control chip；
The control chip connects the chip to be measured, for receive the status command and according to the status command it is true
Fixed corresponding test vector, and the corresponding operating mode of the test vector is sent to the chip to be measured；
The control chip is also used to obtain the chip to be measured and runs the working condition after the operating mode, and according to
The working condition determines the test result of the chip to be measured；
The field programmable gate array chip is also used to receive the test result and feeds back to the test machine.
In one embodiment of the invention, the number of the multiple digital channel is 4, the multiple digital channel pair
The respective pin of the field programmable gate array chip should be connected to.
In one embodiment of the invention, described including vector generation and comparing unit in the multiple digital channel
Vector generates and comparing unit is for generating between the test machine and the development board through the multiple digital channel
Carry out the sequential relationship of bidirectional data transfers.
In one embodiment of the invention, the apparatus for testing chip further includes selecting module, wherein the selection mould
The first end of block is connected to the test machine, and second end is connected to the development board, and third end is connected to chip to be measured, uses
On-off between the control test machine and the chip to be measured or between the development board and the chip to be measured.
In one embodiment of the invention, the selecting module is relay, wherein the normally open end of the relay connects
It is connected to the test machine, the normal-closed end of the relay is connected to the development board, and the common end of the relay
It is connected to the chip to be measured.
Another aspect provides a kind of chip detecting methods, comprising:
S1: the status command from test machine digital communication channel is obtained；
S2: the working condition of chip to be measured is controlled according to described instruction state, and is obtained and is tested according to the working condition
As a result；
S3: the test result is fed back into the test machine digital communication channel.
In one embodiment of the invention, the S2 includes:
S21: it receives the status command and determines corresponding test vector；
S22: being sent to chip to be measured for the corresponding operating mode of the test vector, makes described in the chip operation to be measured
Operating mode；
S23: it obtains the chip to be measured and runs the working condition after the operating mode, and according to the operation state really
The test result of the fixed chip to be measured.
In one embodiment of the invention, after the S3 further include:
The test result is sent to host computer, and is shown by the host computer.
Compared with prior art, the beneficial effects of the present invention are:
1, apparatus for testing chip of the invention and chip detecting method pass through test machine itself when carrying out data transmission
Multiple digital channels are as communication unit, without external private communication module, that is, do not need directly with test machine host computer
The both-way communication of test machine Yu external development board can be realized in connection, and the development cycle is short, and bidirectional data exchange is stablized, effectively
Reduce program development cost.
2, apparatus for testing chip of the invention and chip detecting method are opened using the digital channel of test machine itself with external
Power Generation Road plate carries out SPI communication, economizes on resources, development difficulty is low.
Detailed description of the invention
Fig. 1 is a kind of module diagram of apparatus for testing chip provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of apparatus for testing chip provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of chip detecting method provided in an embodiment of the present invention；
Fig. 4 is the timing diagram that SPI communication is carried out between the test machine of the embodiment of the present invention and development board；
Fig. 5 is another timing diagram that SPI communication is carried out between the test machine of the embodiment of the present invention and development board.
Appended drawing reference is as follows:
1- test machine；2- development board；21- Logic control module；211- field programmable gate array chip；212- control
Coremaking piece；3- host computer；4- chip to be measured；5- selecting module.
Specific embodiment
The content of present invention is described further combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of module diagram of apparatus for testing chip provided in an embodiment of the present invention.This implementation
The apparatus for testing chip of example includes test machine 1 and development board 2, wherein test machine 1 includes multiple digital channels, multiple numbers
Word channel is connected to development board 2, for carrying out bidirectional data transfers between test machine 1 and development board 2；Test
Machine 1 and development board 2 are respectively connected to chip 5 to be measured.
Further, Fig. 2 is referred to, Fig. 2 is a kind of structural representation of apparatus for testing chip provided in an embodiment of the present invention
Figure.Logic control module 21 is provided in development board 2, Logic control module 21 connects multiple digital channels and chip to be measured
5, for determining test vector according to the status command from multiple digital channels, and the corresponding operating mode of test vector is sent out
It send to chip 5 to be measured.
Specifically, Logic control module 21 includes field programmable gate array (FPGA) chip 211 and control chip 212,
Wherein, field programmable gate array chip 211 connects multiple digital channels and control chip 212, for that will come from multiple numbers
The status command in channel is sent to control chip 212；Control chip 212 connects chip 5 to be measured, for reception state instruction and root
Corresponding test vector is determined according to status command, and the corresponding operating mode of test vector is sent to chip 5 to be measured.
In addition, control chip 212, which is also used to obtain chip 5 to be measured, runs the working condition after operating mode, and according to work
The test result of chip 5 to be measured is determined as state；Field programmable gate array chip 211 is also used to receive test result and feeds back
To test machine 1.
In the present embodiment, control chip 212 is that ARM controls chip, can be between chip 5 and ARM to be measured control chip
Pass through I2C or SPI connection.
Further, fpga chip 211 can carry out timing protocols conversion to the vector data that control chip 212 configures,
To meet the sequential relationship that chip to be measured is tested.Control chip 212 according to the status command find it is corresponding test to
Amount, and the vector data is passed into fpga chip 211, fpga chip 211 is according to different types of test vector to described
Vector data carries out protocol conversion, then is sent to chip 4 to be measured by fpga chip 211.Further, in the present embodiment, it surveys
Test result is read by control chip 212.
As shown in Fig. 2, in the present embodiment, the number of multiple digital channels is 4, each digital channel is corresponding to be connected
It is connected to a pin of field programmable gate array chip 211.In the present embodiment, 4 digital channels include SDI,
The channel SDO, CLK and CS.
Further, the multiple digital channel includes that vector generates and comparing unit (not shown), the vector generation
And comparing unit is for generating for carrying out two-way number by the multiple digital channel between test machine 1 and development board 2
According to the sequential relationship of transmission.Specifically, vector generates and comparing unit is for setting 4 digital channels in data transmission procedure
Sequential relationship between SDI, SDO, CLK and CS.Further, test machine 1 further includes vector file unit, for defining test
Machine 1 sends or receives the parameter of data, such as data bit, data format and clock cycle, generates symbol to control the test machine
Close the data of the sequential relationship.
In addition, the two has the mutual relevant of signal when test machine 1 and development board 2 are connected to chip 5 to be measured simultaneously
It disturbs, influences to test signal quality and test frequency, in order to solve this problem, in the present embodiment, the apparatus for testing chip
It further include selecting module 4, wherein the first end of selecting module 4 is connected to test machine 1, and second end is connected to development board 2,
Third end is connected to chip 5 to be measured, for controlling between test machine 1 and chip to be measured 5 or development board 2 and chip to be measured
On-off between 5.Selecting module 4 can make chip 5 to be measured be selectively connected test machine 1 or development board 2, thus effectively
Ground reduces the signal interference between test machine 1 and development board 2.
Preferably, the selecting module 4 is relay, wherein the normally open end of the relay is connected to test machine 1, institute
The normal-closed end for stating relay is connected to the development board 2, and the common end of the relay is connected to chip 5 to be measured.
The switching or disconnection of relay 4 can be controlled according to the test vector by controlling chip 212, to control whether to core to be measured
Piece 5 is tested.
In general, many relays can be arranged in the apparatus for testing chip, to achieve the purpose that while test multiple chips, this
Embodiment controls the actuation or disconnection of relay by control chip 212.In the present embodiment, using single IO, (input is defeated
Pin controls 8 relays out), controls 8 data of I/O pin Serial output of chip 212, then passes through transformation from serial to parallel core
Piece (for example, 6B595) generates 8 control signals.In other embodiments, relay 4 can also control suction by test machine 1
It closes or disconnects.
In addition, it is to be noted that in other embodiments, the selecting module 4 can also be 74 logical series chips,
Switching transistor or other selection switches that circuit selection may be implemented.
Further, test machine 1 further includes host computer 3.Host computer 3 is connect with the test head of test machine 1, for receiving
Test result from the multiple digital channel simultaneously shows the testing result.
There are two types of the testing results of chip to be measured, one is passing through, indicates that chip to be measured by detection, illustrates the core to be measured
Piece is qualified, and another kind is failure, indicates that chip to be measured does not pass through detection, illustrates that the chip to be measured is unqualified.
Specifically, the testing result can be shown in the screen of host computer 3 by forms such as texts, in this way can be square
Just testing staff more gets information about the testing result of chip, or can be stored in the host hard drive of host computer 3, with side
The phase is analyzed and processed after an action of the bowels.Host computer 3 can be the equipment such as computer.
The apparatus for testing chip and chip detecting method of the present embodiment pass through test machine itself when carrying out data transmission
Multiple digital channels are as communication unit, without external private communication module, that is, do not need directly with test machine host computer
The both-way communication of test machine Yu external development board can be realized in connection, and the development cycle is short, and bidirectional data exchange is stablized, effectively
Reduce program development cost.
Embodiment two,
Fig. 3 is referred to, Fig. 3 is a kind of flow chart of chip detecting method provided in an embodiment of the present invention.As shown in figure 3,
Present embodiments provide a kind of chip detecting method, comprising:
S1: the status command from test machine digital communication channel is obtained；
S2: the working condition of chip to be measured is controlled according to described instruction state, and is obtained and is tested according to the working condition
As a result；
S3: the test result is fed back into the test machine digital communication channel.
In the present embodiment, the status command for detecting the Serial Peripheral Interface (SPI) connecting with test machine first, according to the state
Instruction determines corresponding test vector, and the corresponding operating mode of test vector is then sent to chip to be measured, makes chip to be measured
Above-mentioned operating mode is run, the chip to be measured can be obtained in state in which after finally running the operating mode according to chip to be measured
Testing result.Detection pattern corresponding to every kind of status command can be arranged according to demand by user.
Specifically, S2 includes:
S21: it receives the status command and determines corresponding test vector；
S22: being sent to chip to be measured for the corresponding operating mode of the test vector, makes described in the chip operation to be measured
Operating mode；
S23: it obtains the chip to be measured and runs the working condition after the operating mode, and according to the operation state really
The test result of the fixed chip to be measured.
Further, after S3 further include:
Test results machine is sent to host computer, and is shown by host computer.
Specifically, as shown in Fig. 2, in the present embodiment, 4 digital channels (SDI, SDO, CLK, CS) of test machine connect
On four pins of the fpga chip on to development board, and use SPI communication mode.Pass through the vector file of test machine
Unit defines the data bit, data format and clock cycle that test machine sends or receives test data.By in test machine
SPI interface connection between digital channel and fpga chip, completes the two-way SPI communication of test machine and fpga chip.
Please also refer to Fig. 4 and Fig. 5, Fig. 4 be between the test machine of the embodiment of the present invention and road plate carry out SPI communication when
Sequence figure；Fig. 5 is another timing diagram that SPI communication is carried out between the test machine of the embodiment of the present invention and Power Generation Road plate.
As shown in figure 4, carrying out CLK, CS and SDO data of SPI communication by the driving on test machine digital communication channel
Circuit is sent out.In the present embodiment, by taking the transmission of 16bit data as an example, test machine need the data that send by the channel SDI according to
Pre-set clk cycle sequence presses bit and generates low and high level submitting；In fpga chip side, when detecting CLK rising edge
When with CS failing edge, exist in the data that CS low level transmits SDO into the shift register being previously set, and on CS
Rise along when, the data stored in the shift register are sent to control chip, in this way control chip receive data command, open
Beginning execution task；It is complete to control chip processing, processing result is fed back into fpga chip.
As shown in figure 5, in CS low level, fpga chip can be according to test machine when test machine needs to obtain test result
Test result is sent in the SDI communication channel of test machine, at this time the SDI communication channel of test machine by CLK failing edge by bit
Level comparison circuit can be calculated according to clk cycle send back to data the position bit height (standard is compared with low level), obtain
Then the binary data is converted into the decimal system or hexadecimal data by the binary data of this string of 16bit, can obtain
To corresponding test result.In this way, just completing two-way communication process between test machine and development board.
The chip detecting method of the present embodiment carries out SPI using the digital channel of test machine itself and external development board
Communication, economizes on resources, development difficulty is low.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of apparatus for testing chip, which is characterized in that including test machine (1) and development board (2), wherein
The test machine (1) includes multiple digital channels, and the multiple digital channel is connected to the development board (2),
For carrying out bidirectional data transfers between the test machine (1) and the development board (2)；
The test machine (1) and the development board (2) are respectively connected to chip to be measured (5).
2. apparatus for testing chip according to claim 1, which is characterized in that be provided with and patrol on the development board (2)
It collects control module (21), the Logic control module (21) connects the multiple digital channel and the chip to be measured (5), is used for
Test vector is determined according to the status command from the multiple digital channel, and by the corresponding operating mode of the test vector
It is sent to the chip to be measured (5).
3. apparatus for testing chip according to claim 2, which is characterized in that the Logic control module (21) includes scene
Programmable gate array chip (211) and control chip (212), wherein
The field programmable gate array chip (211) connects the multiple digital channel and the control chip (212), is used for
Status command from the multiple digital channel is sent to the control chip (212)；
The control chip (212) connects the chip (5) to be measured, for receiving the status command and being referred to according to the state
It enables and determines corresponding test vector, and the corresponding operating mode of the test vector is sent to the chip to be measured (5)；
Control chip (212) is also used to obtain the chip to be measured (5) and runs the working condition after the operating mode, and
The test result of the chip to be measured (5) is determined according to the working condition；
The field programmable gate array chip (211) is also used to receive the test result and feeds back to the test machine (1).
4. apparatus for testing chip according to claim 3, which is characterized in that the number of the multiple digital channel is 4,
The multiple digital channel is correspondingly connected to the respective pin of the field programmable gate array chip (211).
5. apparatus for testing chip according to claim 1, which is characterized in that include that vector is raw in the multiple digital channel
At and comparing unit, the vector generate and comparing unit for generate the test machine (1) and the development board (2) it
Between by the multiple digital channel carry out bidirectional data transfers sequential relationship.
6. apparatus for testing chip according to claim 1, which is characterized in that the apparatus for testing chip further includes selection mould
Block (4), wherein the first end of the selecting module (4) is connected to the test machine (1), and second end is connected to the exploitation electricity
Road plate (2), third end are connected to chip to be measured (5), for controlling between the test machine (1) and the chip to be measured (5) or
On-off between development board described in person (2) and the chip to be measured (5).
7. apparatus for testing chip according to claim 6, which is characterized in that the selecting module (4) is relay,
In, the normally open end of the relay is connected to the test machine (1), and the normal-closed end of the relay is connected to the exploitation circuit
Plate (2), and the common end of the relay is connected to the chip to be measured (5).
8. a kind of chip detecting method characterized by comprising
S1: the status command from test machine digital communication channel is obtained；
S2: the working condition of chip to be measured is controlled according to described instruction state, and test result is obtained according to the working condition；
S3: the test result is fed back into the test machine digital communication channel.
9. chip detecting method according to claim 8, which is characterized in that the S2 includes:
S21: it receives the status command and determines corresponding test vector；
S22: being sent to chip to be measured for the corresponding operating mode of the test vector, and the chip to be measured is made to run the work
Mode；
S23: it obtains the chip to be measured and runs the working condition after the operating mode, and determine institute according to the operation state
State the test result of chip to be measured.
10. chip detecting method according to claim 8 or claim 9, which is characterized in that after the S3 further include:
The test result is sent to host computer, and is shown by the host computer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811308516.7A CN109307833A (en) | 2018-11-05 | 2018-11-05 | Apparatus for testing chip and chip detecting method |
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| CN201811308516.7A CN109307833A (en) | 2018-11-05 | 2018-11-05 | Apparatus for testing chip and chip detecting method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111596201A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Method for supplying power by using digital channel |
| CN111766509A (en) * | 2020-09-02 | 2020-10-13 | 深圳芯邦科技股份有限公司 | Chip testing method and related equipment |
| CN111913471A (en) * | 2020-07-21 | 2020-11-10 | 北京京瀚禹电子工程技术有限公司 | Testing device |
| CN112285529A (en) * | 2020-09-28 | 2021-01-29 | 上海华岭集成电路技术股份有限公司 | Method for controlling relay by using ATE test vector |
| CN113848457A (en) * | 2021-09-26 | 2021-12-28 | 深圳市金泰克半导体有限公司 | Degradation chip test system based on FPGA |
| CN113960443A (en) * | 2021-09-23 | 2022-01-21 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN118011192A (en) * | 2024-04-10 | 2024-05-10 | 真贺科技(江苏)有限公司 | Multi-mode-grouping chip testing method and system |
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| CN105911451A (en) * | 2016-04-05 | 2016-08-31 | 硅谷数模半导体（北京）有限公司 | Chip test method and chip test device |
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| CN105911451A (en) * | 2016-04-05 | 2016-08-31 | 硅谷数模半导体（北京）有限公司 | Chip test method and chip test device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111596201A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Method for supplying power by using digital channel |
| CN111913471A (en) * | 2020-07-21 | 2020-11-10 | 北京京瀚禹电子工程技术有限公司 | Testing device |
| CN111766509A (en) * | 2020-09-02 | 2020-10-13 | 深圳芯邦科技股份有限公司 | Chip testing method and related equipment |
| CN111766509B (en) * | 2020-09-02 | 2020-12-25 | 深圳芯邦科技股份有限公司 | Chip testing method and related equipment |
| CN112285529A (en) * | 2020-09-28 | 2021-01-29 | 上海华岭集成电路技术股份有限公司 | Method for controlling relay by using ATE test vector |
| CN113960443A (en) * | 2021-09-23 | 2022-01-21 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN113960443B (en) * | 2021-09-23 | 2024-06-07 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN113848457A (en) * | 2021-09-26 | 2021-12-28 | 深圳市金泰克半导体有限公司 | Degradation chip test system based on FPGA |
| CN118011192A (en) * | 2024-04-10 | 2024-05-10 | 真贺科技(江苏)有限公司 | Multi-mode-grouping chip testing method and system |
| CN118011192B (en) * | 2024-04-10 | 2024-06-04 | 真贺科技(江苏)有限公司 | Multi-mode-grouping chip testing method and system |
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