CN111766509B - Chip testing method and related equipment - Google Patents

Chip testing method and related equipment Download PDF

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Publication number
CN111766509B
CN111766509B CN202010909052.6A CN202010909052A CN111766509B CN 111766509 B CN111766509 B CN 111766509B CN 202010909052 A CN202010909052 A CN 202010909052A CN 111766509 B CN111766509 B CN 111766509B
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pin
target
test
tested
chip
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CN111766509A (en
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谢长华
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Chipsbank Technologies Shenzhen Co ltd
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Chipsbank Technologies Shenzhen Co ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]

Abstract

The application provides a chip testing method and related equipment, which can improve the testing efficiency of chip pin testing and reduce the testing time. The method comprises the following steps: acquiring a target time sequence signal through a first target pin of a target chip; analyzing the target time sequence signal to judge whether the target time sequence signal is a pin test instruction, wherein the pin test instruction corresponds to M items to be tested corresponding to each pin to be tested in N pins to be tested of the target chip; when the target time sequence signal is the pin test instruction, starting a timer, and when the timing duration of the timer reaches a preset duration, disconnecting the N pins to be tested from the tester; acquiring test parameters corresponding to the pin test instruction; and testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.

Description

Chip testing method and related equipment
Technical Field
The present disclosure relates to the field of chip testing, and more particularly, to a chip testing method and related apparatus.
Background
When the traditional chip interface circuit is tested, the chip interface circuit is switched to an output state, high and low levels are respectively output, and the voltages at the pin ends of the chips are measured one by one through a testing machine; switching the chip interface circuit to an input state, driving the chip interface circuit to a high level or a low level through a tester according to the NandTree design sequence, and then measuring the pin terminal voltage output by the result.
The testing machine has limited voltage measuring channels and longer measuring time, so that the testing efficiency is reduced, and the testing cost is increased.
Disclosure of Invention
The application provides a chip testing method and related equipment, which can reduce the testing time of pin testing and improve the testing efficiency.
A first aspect of the present application provides a chip testing method, including:
acquiring a target time sequence signal through a first target pin of a target chip, wherein the target chip is a chip to be subjected to pin test;
analyzing the target time sequence signal to judge whether the target time sequence signal is a pin test instruction, wherein the pin test instruction corresponds to M items to be tested corresponding to each pin to be tested in N pins to be tested of the target chip, and N and M are positive integers greater than or equal to 1;
when the target time sequence signal is the pin test instruction, starting a timer, and when the timing duration of the timer reaches a preset duration, disconnecting the N pins to be tested from the tester;
acquiring test parameters corresponding to the pin test instruction;
and testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.
Optionally, the acquiring a target timing signal through a first target pin includes:
capturing, by a signal sampling circuit, the target timing signal input by a user through the first target pin.
Optionally, the testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the test execution, and obtaining the test result includes:
determining a target to-be-detected item, wherein the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of the N to-be-detected pins;
and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result.
Optionally, the method comprises:
latching the test result;
receiving a specific time sequence signal input by the user through a second target pin, wherein the second target pin is a specific pin in the target chip;
and outputting the latched test result according to the specific timing signal.
Optionally, the M items to be tested are at least one of the following items to be tested:
the method comprises a pin input and output test, a pin pull-up resistance test, a pin pull-down resistance test, an adjacent pin short circuit test and a multi-mode pin test.
A second aspect of the present application provides a chip testing apparatus, including:
the device comprises a first acquisition unit, a second acquisition unit and a control unit, wherein the first acquisition unit is used for acquiring a target time sequence signal through a first target pin of a target chip, and the target chip is a chip to be subjected to pin test;
the analysis unit is used for analyzing the target time sequence signal to judge whether the target time sequence signal is a pin test instruction or not, the pin test instruction corresponds to M items to be tested corresponding to each pin to be tested in N pins to be tested of the target chip, wherein N and M are positive integers greater than or equal to 1;
the processing unit is used for starting a timer when the target time sequence signal is the pin test instruction, and disconnecting the N pins to be tested from the tester when the timing duration of the timer reaches a preset duration;
the second acquisition unit is used for acquiring the test parameters corresponding to the pin test instruction;
and the test unit is used for testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.
Optionally, the first obtaining unit is specifically configured to:
capturing, by a signal sampling circuit, the target timing signal input by a user through the first target pin.
Optionally, the test unit is specifically configured to:
determining a target to-be-detected item, wherein the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of the N to-be-detected pins;
and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result.
Optionally, the apparatus further comprises:
the storage unit is used for latching the test result;
and the output unit is used for receiving the specific time sequence signal input by the user through a second target pin, wherein the second target pin is a specific pin in the target chip, and outputting the latched test result according to the specific time sequence signal.
Optionally, the M items to be tested are at least one of the following items to be tested:
the method comprises a pin input and output test, a pin pull-up resistance test, a pin pull-down resistance test, an adjacent pin short circuit test and a multi-mode pin test.
A third aspect of the application provides a chip comprising at least one processor and interface circuitry; the interface circuit provides input and/or output of data or instructions for the at least one processor, and when the at least one processor processes the data or instructions, the steps of the chip testing method according to the first aspect are implemented.
A fourth aspect of the present application provides a computer-readable storage medium, comprising computer instructions, which, when run on a computer device, cause the computer device to perform the steps of the chip testing method according to the first aspect.
In summary, it can be seen that, in the embodiment provided by the present application, the test of the chip pin is a self-test performed after the chip pin is disconnected from the tester, so that all pin test processes perform a self-test on the chip, which can avoid the long test time caused by the limited channel of the test voltage, improve the test efficiency, and avoid the conflict caused by the difference between the input voltage during the test of the existing chip and the voltage of the input chip of the tester.
Drawings
Fig. 1 is a schematic flowchart of a chip testing method according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a virtual structure of a chip testing apparatus according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a chip provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprise," "include," and "have," and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules expressly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus, the division of modules presented herein is merely a logical division that may be implemented in a practical application in a further manner, such that a plurality of modules may be combined or integrated into another system, or some feature vectors may be omitted, or not implemented, and such that couplings or direct couplings or communicative coupling between each other as shown or discussed may be through some interfaces, indirect couplings or communicative coupling between modules may be electrical or other similar, this application is not intended to be limiting. The modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in a plurality of circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present disclosure.
The chip testing method provided in the embodiments of the present application is described below from the perspective of a chip testing device, which may be a server or a service unit in the server, and is not particularly limited.
Referring to fig. 1, fig. 1 is a schematic flow chart of a chip testing method according to an embodiment of the present application, including:
101. and acquiring a target timing signal through a first target pin of the target chip.
In this embodiment, the chip testing apparatus may obtain the target timing signal through the first target pin of the target chip, where the target chip is a chip to be tested. The chip testing device captures a target timing signal input by a user through the first target pin through the signal sampling circuit, that is, the user can input an advanced timing signal (also called a target timing signal) through one or more Pins (PAD) in the target chip, and the advanced timing signal can be captured through the signal sampling circuit arranged in the chip.
It should be noted that, in practical applications, when the chip testing apparatus monitors the target timing signal through the signal sampling circuit, it may also be determined whether the target chip is overtime, if the target chip is overtime, the target chip is normally started, and if the target chip is not overtime, the target timing signal is continuously monitored through the signal sampling circuit until the target timing signal is monitored.
102. Analyzing the target timing signal to determine whether the target timing signal is a pin test command, executing step 103 when the target timing signal is the pin test command, and executing step 106 when the target timing signal is not the pin test command.
In this embodiment, after obtaining the target timing signal, the chip testing apparatus may analyze the target timing signal to determine whether the target timing signal is a pin test instruction, where the pin test instruction corresponds to M items to be tested corresponding to each of N pins to be tested of the target chip (that is, the pin test instruction is a test performed on M items to be tested corresponding to each of the N pins to be tested of the target chip), where N and M are positive integers greater than or equal to 1. That is, before the chip is tested, a set of test instructions is defined, which test instructions are the chip pin test instructions, and after the target timing signal is obtained, the target timing signal may be analyzed to determine whether the target timing signal is the timing signal corresponding to the pin test instruction, if so, step 103 is executed, otherwise, step 106 is executed. The corresponding manner of the timing signal and the chip pin test instruction is not particularly limited, and it is sufficient if the received timing signal can be used to determine whether the received timing signal is an instruction for performing a pin test on the chip.
It should be noted that the M items to be tested include at least one of a pin input/output test, a pin pull-up resistance test, a pin pull-down resistance test, an adjacent pin short circuit test, and a multi-mode pin test; the multi-mode pin test may be, for example, a high impedance mode, a push-pull output mode, and an open-drain output mode, and may also include other modes, which are not limited specifically.
103. And when the target time sequence signal is a pin test instruction, starting a timer, and disconnecting the N pins to be tested from the tester when the timing duration of the timer reaches a preset duration.
In this embodiment, the chip testing apparatus may start the timer when determining that the target timing signal is the pin test instruction, and disconnect the N pins to be tested from the tester when the timing duration of the timer reaches the preset duration. That is, after determining that the timing signal received through the first target pin is a chip pin test instruction, starting a timer, waiting for a period of time (for example, 10 milliseconds, that is, when the timing duration of the timer reaches a preset duration), disconnecting the tester from the N pins to be tested, so as to avoid a conflict caused by a difference between the input voltage of the tester to the chip and the input voltage of the chip during testing.
104. And acquiring test parameters corresponding to the pin test instruction.
In this embodiment, after determining that the target chip is a pin test instruction, the chip testing apparatus may obtain corresponding test parameters, that is, obtain parameter information that needs to be configured for the pin test of the target chip, for example, an input/output test needs to be performed on a certain pin in the target chip, and may configure the test parameters that need to be configured for the input/output test.
105. And testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.
In this embodiment, after the chip testing apparatus obtains the testing parameters, the chip testing apparatus may test, according to the testing parameters, the M items to be tested corresponding to each pin to be tested in the N pins to be tested, so as to obtain a testing result. Specifically, a target to-be-detected item can be determined, where the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of N to-be-detected pins; and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result. That is to say, one pin can be selected from the N pins to be tested at will, the item to be tested in the pin is tested, and so on, all the pins to be tested of the N pins to be tested can be tested, and the corresponding test result is obtained.
In one embodiment, the chip testing device may latch the test result;
receiving a specific time sequence signal input by a user through a second target pin, wherein the second target pin is a specific pin in a target chip;
and outputting the latched test result according to the specific time sequence signal.
In this embodiment, the chip testing apparatus may latch the test result after obtaining the test result. When the test result needs to be output, a specific timing signal input by a user can be received through a chip pin (namely, a second pin) with a preset number, and the test result is input according to the specific timing signal. It can be understood that the chip testing apparatus may latch the test result of the test item every time an item is tested, may also latch the test result corresponding to the test item of the pin after the test item of the pin is completed, and of course may also latch the test result after the test items of all the pins are completed, which is not limited specifically, and the output is the same.
106. Other operations are performed.
In this embodiment, when the target timing signal is not the pin test command, the chip test apparatus may perform another test corresponding to the target timing signal.
In summary, it can be seen that, in the embodiment provided by the present application, the test of the chip pin is a self-test performed after the chip pin is disconnected from the tester, which can avoid the long test time caused by the limited channel of the test voltage in the prior art, and improve the test efficiency, and all pin test processes perform the self-test on the chip, thereby avoiding the conflict caused by the difference between the input voltage during the test of the prior chip and the voltage of the input chip of the tester.
The present application is described above in terms of a chip testing method, and the present application is described below in terms of a chip testing apparatus.
Referring to fig. 2, fig. 2 is a schematic view of a virtual structure of a chip testing apparatus according to an embodiment of the present application, including:
a first obtaining unit 201, configured to obtain a target timing signal through a first target pin of a target chip, where the target chip is a chip to be subjected to a pin test;
an analysis unit 202, configured to analyze the target timing signal to determine whether the target timing signal is a pin test instruction, where the pin test instruction corresponds to M items to be tested corresponding to each of N pins to be tested of the target chip, where N and M are positive integers greater than or equal to 1;
the processing unit 203 is configured to start a timer when the target timing signal is the pin test instruction, and disconnect the N pins to be tested from the tester when a timing duration of the timer reaches a preset duration;
a second obtaining unit 204, configured to obtain a test parameter corresponding to the pin test instruction;
and the test unit 205 is configured to test, according to the test parameter corresponding to the pin test instruction, the M items to be tested corresponding to each pin to be tested in the N pins to be tested, so as to obtain a test result.
Optionally, the first obtaining unit 201 is specifically configured to:
capturing, by a signal sampling circuit, the target timing signal input by a user through the first target pin.
Optionally, the test unit 205 is specifically configured to:
determining a target to-be-detected item, wherein the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of the N to-be-detected pins;
and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result.
Optionally, the apparatus further comprises:
a storage unit 206, configured to latch the test result;
an output unit 207, configured to receive the specific timing signal input by the user through a second target pin, where the second target pin is a specific pin in the target chip, and output the latched test result according to the specific timing signal.
Optionally, the M items to be tested are at least one of the following items to be tested:
the method comprises a pin input and output test, a pin pull-up resistance test, a pin pull-down resistance test, an adjacent pin short circuit test and a multi-mode pin test.
In summary, it can be seen that, in the embodiment provided by the present application, the test of the chip pin is a self-test performed after the chip pin is disconnected from the tester, which can avoid the long test time caused by the limited channel of the test voltage in the prior art, and improve the test efficiency, and all pin test processes perform the self-test on the chip, thereby avoiding the conflict caused by the difference between the input voltage during the test of the prior chip and the voltage of the input chip of the tester.
Fig. 3 is a schematic structural diagram of a chip according to an embodiment of the present disclosure. Chip 300 includes one or more processors 301 and interface circuitry 302. Optionally, the chip 300 may further include a bus 303. Wherein:
the processor 301 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 301. The processor 301 described above may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The methods, steps disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The type of processor 1310 described above may also be referred to in the explanation of the processor 301.
The interface circuit 302 may perform transmission or reception of data, instructions, or information, and the processor 301 may perform processing using the data, instructions, or other information received by the interface circuit 302, and may transmit the processing completion information through the interface circuit 302.
Optionally, the chip further comprises a memory, which may include read only memory and random access memory, and provides operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).
Optionally, the memory stores executable software modules or data structures, and the processor may perform corresponding operations by calling the operation instructions stored in the memory (the operation instructions may be stored in an operating system).
Alternatively, the chip may be used in a communication apparatus (including a master node and a slave node) according to an embodiment of the present application. Optionally, the interface circuit 302 may be used to output the execution result of the processor 301. For the chip testing method provided by one or more embodiments of the present application, reference may be made to the foregoing embodiments, which are not repeated herein.
It should be noted that the functions corresponding to the processor 301 and the interface circuit 302 may be implemented by hardware design, software design, or a combination of hardware and software, which is not limited herein.
It will be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM, enhanced SDRAM, SLDRAM, Synchronous Link DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
According to the method provided by the embodiment of the present application, the present application further provides a computer program product, which includes: computer program code which, when run on a computer, causes the computer to perform the chip testing method as provided by one or more embodiments of the present application.
According to the method provided by the embodiment of the application, the application also provides a computer readable storage medium, which stores program codes, and when the program codes are run on a computer, the computer is caused to execute the chip testing method provided by one or more embodiments of the application.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.
The network device in the foregoing various apparatus embodiments corresponds to the terminal device or the network device in the terminal device and method embodiments, and the corresponding module or unit executes the corresponding steps, for example, the communication unit (transceiver) executes the steps of receiving or transmitting in the method embodiments, and other steps besides transmitting and receiving may be executed by the processing unit (processor). The functions of the specific elements may be referred to in the respective method embodiments. The number of the processors may be one or more.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps (step) described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for testing a chip, comprising:
acquiring a target time sequence signal through a first target pin of a target chip, wherein the target chip is a chip to be subjected to pin test;
analyzing the target time sequence signal to judge whether the target time sequence signal is a pin test instruction, wherein the pin test instruction corresponds to M items to be tested corresponding to each pin to be tested in N pins to be tested of the target chip, and N and M are positive integers greater than or equal to 1;
when the target time sequence signal is the pin test instruction, starting a timer, and when the timing duration of the timer reaches a preset duration, disconnecting the N pins to be tested from the tester;
acquiring test parameters corresponding to the pin test instruction;
and testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.
2. The method of claim 1, wherein the obtaining the target timing signal via the first target pin comprises:
capturing, by a signal sampling circuit, the target timing signal input by a user through the first target pin.
3. The method according to claim 1 or 2, wherein the testing the M items to be tested corresponding to each of the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result comprises:
determining a target to-be-detected item, wherein the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of the N to-be-detected pins;
and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result.
4. The method of claim 2, wherein the method comprises:
latching the test result;
receiving a specific time sequence signal input by the user through a second target pin, wherein the second target pin is a specific pin in the target chip;
and outputting the latched test result according to the specific timing signal.
5. The method according to claim 1 or 2, wherein the M items under test are at least one of the following items under test:
the method comprises a pin input and output test, a pin pull-up resistance test, a pin pull-down resistance test, an adjacent pin short circuit test and a multi-mode pin test.
6. A chip testing apparatus, comprising:
the device comprises a first acquisition unit, a second acquisition unit and a control unit, wherein the first acquisition unit is used for acquiring a target time sequence signal through a first target pin of a target chip, and the target chip is a chip to be subjected to pin test;
the analysis unit is used for analyzing the target time sequence signal to judge whether the target time sequence signal is a pin test instruction or not, the pin test instruction corresponds to M items to be tested corresponding to each pin to be tested in N pins to be tested of the target chip, wherein N and M are positive integers greater than or equal to 1;
the processing unit is used for starting a timer when the target time sequence signal is the pin test instruction, and disconnecting the N pins to be tested from the tester when the timing duration of the timer reaches a preset duration;
the second acquisition unit is used for acquiring the test parameters corresponding to the pin test instruction;
and the test unit is used for testing the M items to be tested corresponding to each pin to be tested in the N pins to be tested according to the test parameters corresponding to the pin test instruction to obtain a test result.
7. The apparatus according to claim 6, wherein the first obtaining unit is specifically configured to:
capturing, by a signal sampling circuit, the target timing signal input by a user through the first target pin.
8. The device according to claim 6 or 7, characterized in that the test unit is specifically configured to:
determining a target to-be-detected item, wherein the target to-be-detected item is any one of M to-be-detected items corresponding to a target to-be-detected pin, and the target to-be-detected pin is any one of the N to-be-detected pins;
and testing the target item to be tested according to the test parameters corresponding to the pin test instruction to obtain the test result.
9. A chip, wherein the chip comprises at least one processor and interface circuitry; the interface circuit provides input and/or output of data or instructions for the at least one processor, which when processed implements the method of any one of claims 1 to 5.
10. A computer readable storage medium comprising computer instructions which, when run on a computer device, cause the computer device to perform the method of any of claims 1 to 5.
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