CN105988077A - Built-in self-test method, device and system on chip - Google Patents

Abstract

The embodiment of the invention discloses a built-in self-test device, which comprises a test control circuit connected with an analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; the test response analysis circuit comprises a fault detection module and a parameter calculation module; the test control circuit is used for instructing the test pattern generation circuit to generate a test pattern corresponding to the test mode and instructing the test response analysis circuit to switch to a working mode corresponding to the test mode when a test mode signal is monitored. Multi-mode testing of analog/mixed signal circuits can be achieved. The embodiment of the application also provides a built-in self-test method and a system on a chip.

Description

Built-in self-test method, device and system on chip

Technical Field

The invention relates to the technical field of testing, in particular to a built-in self-testing method, a built-in self-testing device and a system on a chip.

Background

Integrated circuit technology has evolved to the System on a Chip (SoC) stage, with testing being one of the key technologies for socs. In addition to a large number of Intellectual Property (IP) cores of digital circuits, an analog circuit or an IP core of a digital-analog mixed signal circuit (hereinafter referred to as an analog/mixed signal circuit) is integrated in the SoC. For the analog/mixed signal circuit, since there is no support of a mature testability design tool like a digital integrated circuit, it is a problem to be considered and solved in SoC testability design to study the test structure and self-test method of the analog/mixed signal circuit in SoC.

There are two basic test methods for analog/mixed signal IP cores: functional testing and structural testing. The functional test is a test derived from product specifications, and aims to check whether a circuit meets design requirements, and the main contents of the functional test include a direct current parameter (also called a static parameter) and an alternating current parameter (also called a dynamic parameter). The structural test is a test originated from defects, which is also called a fault-based test, the existing fault models are fatal faults and parameter faults, the fatal fault models describe the conditions of open circuit or short circuit of internal connecting wires and the like, and the parameter fault models describe the conditions that the component values exceed the allowable variation range.

built-In-Self-Test (BIST) is one implementation technique for design for testability. Test generation, application, analysis and test control structures are built inside the circuit so that the circuit can test itself, which is a built-in self test. Because the built-in self-test is to complete the test process in the chip, the dependence on high-performance test equipment during the test can be reduced, and the test time and the test cost of the IP core can be reduced. Therefore, testing of an increasing number of analog/mixed signal IP cores currently employs built-in self-test structures.

However, at present, the test of the analog/mixed signal IP core by using the built-in self-test structure is either based on a functional test or a fault test, and the test mode is relatively single.

Disclosure of Invention

The invention aims to provide a built-in self-test method, a built-in self-test device and a system on a chip, so as to realize multi-mode test of an analog/mixed signal circuit.

In order to achieve the purpose, the invention provides the following technical scheme:

a built-in self-test apparatus for a system-on-chip integrated with analog/mixed signal circuitry, the apparatus comprising: the test control circuit is connected with the analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; wherein,

the test response analysis circuit comprises a fault detection module and a parameter calculation module;

the test control circuit is configured to instruct the test pattern generation circuit to generate a test pattern corresponding to the test mode and instruct the test response analysis circuit to switch to a working mode corresponding to the test mode when a test mode signal is monitored, where the working mode of the test response analysis circuit includes: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode;

the fault detection module is used for judging whether the analog/mixed signal circuit has faults or not according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit;

the parameter calculation module is used for calculating parameters corresponding to the analog/mixed signal circuit according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, and the parameters comprise static parameters and/or dynamic parameters.

The above apparatus, preferably, the parameter calculating module includes:

a static parameter calculation submodule and/or a dynamic parameter calculation submodule.

In the above apparatus, preferably, when the parameter calculation module includes a static parameter calculation submodule and a dynamic parameter calculation submodule, the operation mode of the parameter calculation module includes:

the static parameter calculation submodule is in an independent starting mode, the dynamic parameter calculation submodule is in an independent starting mode, or the static parameter calculation submodule and the dynamic parameter calculation submodule are both in a starting mode.

In the above apparatus, preferably, if the system on chip is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit, the test pattern generating circuit is connected to the mixed signal circuit through the digital-to-analog conversion circuit.

In the above apparatus, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is a digital-to-analog conversion circuit, the test response analyzing circuit is connected to the mixed signal circuit through the analog-to-digital conversion circuit.

Preferably, the apparatus further includes:

the differential circuit is used for carrying out differential operation on the test pattern signal generated by the test pattern generating circuit and the signal output by the mixed signal circuit responding to the test pattern;

the accumulator is used for carrying out accumulation operation on the absolute value of the difference operation result;

and the decision device judges whether the mixed signal circuit has faults or not according to the accumulation operation result.

Preferably, in the above apparatus, the parameter calculation module includes a static parameter submodule, and the static parameter submodule includes:

the counter is used for counting the occurrence times of each digital code of the signal output by the mixed signal circuit;

and the first arithmetic unit is used for calculating to obtain the static parameters according to the occurrence times of each digital code of the signals output by the mixed signal circuit.

Preferably, in the above apparatus, the parameter calculation module includes a dynamic parameter submodule, and the dynamic parameter submodule includes:

the converter is used for carrying out fast Fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

and the second operation module is used for calculating to obtain dynamic parameters according to the frequency spectrum of the signal output by the mixed signal circuit.

Preferably, in the above apparatus, if the system on chip is integrated with an analog circuit, the test pattern generating circuit is connected to the analog circuit through a digital-to-analog conversion circuit, and the test response analyzing circuit is connected to the analog circuit through an analog-to-digital conversion circuit.

A system on a chip comprising a built-in self-test device as described in any one of the above.

A built-in self-test method is applied to a system-on-chip, wherein the system-on-chip is integrated with an analog/mixed signal circuit, and the system-on-chip further comprises the following steps: the test control circuit is connected with the analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; the test response analysis circuit comprises a fault detection module and a parameter calculation module; the method comprises the following steps:

when the test control circuit monitors that a test mode signal is input, the test control circuit instructs the test pattern generation circuit to generate a test pattern corresponding to the test mode and instructs the test response analysis circuit to switch to a working mode corresponding to the test mode, wherein the working mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode;

when the fault detection module is in a working state, judging whether the analog/mixed signal circuit has a fault according to response information of the analog/mixed signal circuit to a test pattern generated by the test pattern generation circuit;

and when the parameter calculation module is in a working state, calculating parameters corresponding to the analog/mixed signal circuit according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, wherein the parameters comprise static parameters and/or dynamic parameters.

In the above method, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, determining whether the mixed signal circuit has a fault according to response information of the mixed signal circuit to the test pattern generated by the test pattern generating circuit includes:

carrying out difference operation on the test pattern signal generated by the test pattern generating circuit and the signal output by the mixed signal circuit responding to the test pattern;

performing accumulation operation on the absolute value of the difference operation result;

and judging whether the mixed signal circuit has faults or not according to the accumulation operation result.

In the above method, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a static parameter, calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit includes:

counting the occurrence times of each digital code of the signal output by the mixed signal circuit;

and calculating to obtain static parameters according to the occurrence times of each digital code of the signal output by the mixed signal circuit.

In the above method, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a dynamic parameter, calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit includes:

performing fast Fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

and calculating to obtain dynamic parameters according to the frequency spectrum of the signal output by the mixed signal circuit.

According to the scheme, the built-in self-test method, the built-in self-test device and the system on chip are provided, wherein the system on chip is integrated with an analog/mixed signal circuit, a test control circuit, a test pattern generating circuit, a test response analyzing circuit and a memory; the test response analysis circuit comprises a fault detection module and a parameter calculation module; when monitoring a test mode signal, the test control circuit instructs the test pattern generation circuit to generate a test pattern corresponding to the test mode and instructs the test response analysis circuit to switch to a working mode corresponding to the test mode, wherein the working mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode; the fault detection module is used for judging whether the analog/mixed signal circuit has faults or not; the parameter calculation module is used for calculating parameters corresponding to the analog/mixed signal circuit, and the parameters comprise static parameters and/or dynamic parameters.

In summary, according to the built-in self-test method, device and system on chip provided by the embodiment of the present application, different test mode signals correspond to different working modes of the test response analysis circuit, so that not only fault-based testing but also function-based testing can be performed, or fault-based testing and function-based testing are performed in a mixed manner, thereby implementing multi-mode testing of the analog/mixed signal circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a built-in self-test device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a fault detection module according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a static parameter submodule provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a dynamic parameter submodule provided in an embodiment of the present application;

FIG. 5 is a flow chart of an implementation of a built-in self-test method according to an embodiment of the present application;

fig. 6 is a flowchart of an implementation of determining whether a mixed signal circuit has a fault according to response information of the mixed signal circuit to a test pattern generated by a test pattern generation circuit according to the embodiment of the present application;

fig. 7 is a flowchart of an implementation of calculating parameters corresponding to a mixed signal circuit according to response information of the mixed signal circuit to a test pattern generated by a test pattern generation circuit according to an embodiment of the present application;

fig. 8 is a flowchart of another implementation of calculating parameters corresponding to a mixed signal circuit according to response information of the mixed signal circuit to a test pattern generated by a test pattern generation circuit according to the embodiment of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be practiced otherwise than as specifically illustrated.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The built-in self-test device and the method provided by the embodiment of the application are applied to a system on chip, wherein an analog circuit or a digital-analog mixed signal circuit (hereinafter referred to as an analog/mixed signal circuit) is integrated in the system on chip, and the built-in self-test device provided by the embodiment of the application is used for testing the analog/mixed signal circuit.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a built-in self-test device according to an embodiment of the present application, which may include:

a test control circuit 11, a test pattern generation circuit 12, a test response analysis circuit 13, and a memory 14; wherein,

the test control circuit 11 is respectively connected with the test pattern generating circuit 12, the test response analyzing circuit 13 and the analog/mixed signal circuit;

the test pattern generation circuit 12 and the test response analysis circuit 13 are also connected to the analog/mixed signal circuit, respectively;

the test pattern generating circuit 12 may adopt a test pattern generating circuit of a linear feedback shift register structure, and the test pattern generating circuit 12 may generate various test waveforms including a pseudo random wave, a ramp wave, a sawtooth wave, a triangular wave, a step wave, a square wave, and a sine wave of a certain frequency.

The test response analysis circuit 13 includes a fault detection module 131 and a parameter calculation module 132; wherein,

the fault detection module 131 is configured to determine whether the analog/mixed signal circuit has a fault according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, that is, when the fault detection module 131 is in a working state, a fault-based test may be implemented.

The parameter calculating module 132 is configured to calculate parameters corresponding to the analog/mixed signal circuit according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generating circuit, where the parameters include static parameters and/or dynamic parameters, that is, when the parameter calculating module 132 is in an operating state, a function-based test may be implemented.

In the embodiment of the present application, when the static parameters need to be calculated, the test control circuit 11 may control the test pattern generation circuit 12 to generate a linear waveform signal, such as a triangular wave signal or a ramp wave signal, and when the dynamic parameters need to be calculated, the test control circuit 11 may control the test pattern generation circuit 12 to generate a sine wave signal.

The operation mode of the test response analyzing circuit 13 may include: the fault detection module 131 is in an independent start mode, the parameter calculation module 132 is in an independent start mode, or both the fault detection module 131 and the parameter calculation module 132 are in a start mode; the specific selection of which operating mode is selected can be determined by user selection according to actual requirements.

In both the starting modes of the fault detection module 131 and the parameter calculation module 132, after the fault detection module 131 finishes working, the parameter calculation module 132 performs corresponding work; alternatively, after the parameter calculation module 132 completes its operation, the fault detection module 131 may perform the corresponding operation. The specific way can be determined according to actual requirements.

Preferably, in order to save the test time of the bad chip, the fault test may be performed first, and then the parameter test is performed after the test is passed, and if the test is not passed, then the parameter test is not performed.

The memory 14 is connected to the test response analysis circuit 13 for storing information that needs to be saved during the built-in self-test.

For example, the memory 14 may store data used in the parameter calculation process.

In the embodiment of the application, the test flow can adopt a sequential test method, and the storage resources can be time-division multiplexed (namely, the same memory is multiplexed in time-division) according to the test flow, so that the area overhead of the memory can be reduced.

For example, in the embodiment of the present invention, the static parameters and the dynamic parameters are tested separately, so that the static parameter test and the dynamic parameter test can time-division multiplex the memory 14.

For another example, when performing dynamic parameter testing, butterfly operations may be used, where data to be stored in one butterfly operation unit includes input data and output data, and then time-division multiplexing may refer to: the first stage starts to sequentially find the 1 st, 2 nd and 3 rd butterfly operations, the first storage area of the memory 14 stores the input of the first stage butterfly operation, the second storage area of the memory 14 stores the output of the first stage butterfly operation, when finding the second stage butterfly operation, the output of the first stage butterfly operation (i.e. the data stored in the second storage area of the memory 14) can be used as the input of the 2 nd stage butterfly operation, the output of the 2 nd stage butterfly operation can be stored in the first storage area of the memory 14, and so on.

The test control circuit 11 is configured to monitor whether a test mode signal is generated, and instruct the test pattern generation circuit 12 to generate a test pattern corresponding to the test mode when the test mode signal is monitored. Each test pattern may correspond to one test pattern, or may correspond to two or more test patterns. When the test pattern is corresponding to two or more types of test patterns, the generation sequence of the two or more types of test patterns and the generation time of the test patterns can be determined according to the test requirements, and the test patterns are generated at the corresponding generation time according to the generation sequence of the test patterns in the test process and output to the analog/mixed signal circuit.

The test control circuit 11 can monitor whether a test mode signal is generated or not through two test pins. Specifically, whether a test mode signal is generated or not may be monitored by a mode configuration manner as described in table 1.

TABLE 1

Serial number	TM2	TM1	On/off state	Mode(s)
					0	0	0	Closing device
1	0	1	Opening device	Start-up fault detection mode
					2	1	0	Opening device	Initiating a parametric test mode

3

1

1

Opening device

Initiating a hybrid test mode

TM1 and TM2 represent two test pins, and in the embodiment of the present application, when both test pins input a low level, it represents that the self-built internal test device is turned off. When the input of one of the two test pins is a high level, it indicates that the self-built internal test device is turned on, specifically, when the TM1 pin inputs a low level (indicated by 0 in table 1) and the TM2 pin inputs a high level (indicated by 1 in table 1), it indicates that the independent start mode of the parameter calculation module is turned on, i.e., the parameter test mode; when a TM1 pin inputs a high level and a TM2 pin inputs a low level, the independent starting mode of the fault detection module is started, namely the fault detection mode; when the TM1 pin and the TM2 pin both input a high level, it indicates that the start-up mode of both the fault detection module and the parameter calculation module is the hybrid test mode.

The test control circuit 11 further instructs the test response analysis circuit 13 to switch the operation mode to the operation mode corresponding to the test mode when the test mode signal is monitored.

In the embodiment of the present application, the test control circuit 11, the test pattern generation circuit 12, the test response analysis circuit 13, and the memory 14 may all be digital circuits.

The embodiment of the application provides a built-in self-test device, which is applied to a system on chip, wherein the system on chip is integrated with an analog/mixed signal circuit, and the device comprises: the test control circuit, the test pattern generating circuit, the test response analyzing circuit and the memory; the test response analysis circuit comprises a fault detection module and a parameter calculation module; when monitoring a test mode signal, the test control circuit controls the test pattern generation circuit to generate a test pattern corresponding to the test mode, and controls the test response analysis circuit to switch to a working mode corresponding to the test mode, wherein the working mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode; the fault detection module is used for judging whether the analog/mixed signal circuit has faults or not; the parameter calculation module is used for calculating parameters corresponding to the analog/mixed signal circuit, and the parameters comprise static parameters and/or dynamic parameters.

In summary, according to the built-in self-test device provided by the embodiment of the present application, different test mode signals correspond to different working modes of the test response analysis circuit, so that not only a fault-based test but also a function-based test can be performed, or the fault-based test and the function-based test are performed in a mixed manner, thereby realizing a multi-mode test on an analog/mixed signal circuit.

In the foregoing embodiment, preferably, the parameter calculation module includes a static parameter calculation sub-module and/or a dynamic parameter calculation sub-module.

The static parameter calculation submodule is used for calculating static parameters; and the dynamic parameter calculation submodule is used for calculating the dynamic parameters.

Specifically, the parameter calculation module may be designed according to an application environment. For example, some analog/mixed signal circuits may only need to calculate static parameters or only need to calculate dynamic parameters, in this case, the parameter calculation module may only design the static parameter calculation submodule or only design the dynamic parameter submodule, so as to reduce the area occupied by the built-in self-test device as much as possible and reduce the area overhead.

In the foregoing embodiment, preferably, when the parameter calculation module includes a static parameter calculation sub-module and a dynamic parameter calculation sub-module, the operation mode of the parameter calculation module includes:

the static parameter calculation submodule is in an independent starting mode, the dynamic parameter calculation submodule is in an independent starting mode, or the static parameter calculation submodule and the dynamic parameter calculation submodule are both in a starting mode.

When the parameter calculation module is in a mode that both the static parameter calculation submodule and the dynamic parameter calculation submodule are started, the static parameters can be calculated through the static parameter calculation submodule, and then the dynamic parameters can be calculated through the dynamic parameter calculation submodule; alternatively, the dynamic parameters may be calculated by the dynamic parameter calculation sub-module first, and then the static parameters may be calculated by the static parameter calculation sub-module.

In the above embodiment, preferably, when the parameter calculation module includes a static parameter calculation submodule and a dynamic parameter calculation submodule, the built-in self-test device provided in the embodiment of the present application may support seven test modes, and the test control circuit 11 may determine whether a test mode signal is generated through three test pins. Specifically, whether a test pattern signal is generated or not may be monitored by a pattern configuration manner as shown in table 2.

TABLE 2

Serial number	TM3	TM2	TM1	On/off state	Mode(s)
						0	0	0	0	Closing device
1	0	0	1	Opening device	Start-up fault detection mode
						2	0	1	0	Opening device	Initiating a static parameter test mode
3	0	1	1	Opening device	Initiating dynamic parametric test mode
						4	1	0	0	Opening device	Start-up fault detection and static parameter testing

5	1	0	1	Opening device	Start-up fault detection and dynamic parameter testing
						6	1	1	0	Opening device	Initiating static parameter and dynamic parameter testing
7	1	1	1	Opening device	Initiating a hybrid test mode

TM1, TM2, and TM3 represent three test pins, and in the embodiment of the present application, when all three test pins input a low level, this indicates that the self-built internal test apparatus is turned off. When the input of one of the three test pins is a high level, it indicates that the self-built internal test device is turned on, and specifically, when the TM1 pin inputs a high level and the TM2 pin and the TM3 pin both input a low level, it indicates that the fault detection module is turned on to be in an independent start mode, i.e., a fault detection mode; when the TM2 pin inputs a high level and the TM1 pin and the TM3 pin both input a low level, the independent starting mode of the static parameter calculation submodule, namely the static parameter test mode, is indicated to be started; when the TM1 pin and the TM2 pin both input high level and the TM3 pin inputs low level, the independent starting mode of the dynamic parameter calculation submodule, namely the dynamic parameter test mode, is indicated to be started; when the TM1 pin and the TM2 pin both input low level and the TM3 pin inputs high level, the fault detection module and the static parameter calculation submodule are started to start in a starting mode, namely a fault detection and static parameter test mode; when the TM1 pin and the TM3 pin both input high level and the TM2 pin inputs low level, the fault detection module and the dynamic parameter calculation sub-module both start mode, namely the fault detection and dynamic parameter test mode, is indicated to be started; when the TM1 pin inputs a low level and the TM2 pin and the TM3 pin both input a high level, the method indicates that the starting mode of both the static parameter calculation submodule and the dynamic parameter calculation submodule is started, namely the static parameter testing mode and the dynamic parameter testing mode are started; when the TM1 pin, the TM2 pin, and the TM3 pin all input a high level, it indicates that the startup fault detection module, the static parameter calculation sub-module, and the dynamic parameter calculation sub-module all start up a mode, i.e., a hybrid test mode.

When the hybrid test mode is started, the implementation procedure for testing the analog/mixed signal circuit may be as follows:

the method comprises the following steps: the test control circuit 11 instructs the test pattern generation circuit 12 to generate a test waveform, and instructs the test response analysis circuit 13 to prepare for response analysis. After the test response analysis circuit receives a digital code (if the mixed signal circuit is an analog-to-digital conversion circuit, the digital code is directly output by the mixed signal circuit, if the mixed signal circuit is an analog-to-digital conversion circuit or the mixed signal circuit is a digital-to-analog conversion circuit, the analog-to-digital conversion circuit performs analog-to-digital conversion on a signal of the analog circuit or the mixed signal circuit and outputs the digital code), fault detection is performed, and if the detection result is 'pass', a second step is executed; if the detection result is 'fail', executing a fourth step;

step two: the test control circuit 11 instructs the test pattern generation circuit 12 to generate a triangular wave signal and instructs the test response analysis circuit 13 to perform response analysis, the test response analysis circuit 13 performs a static parameter test after receiving a digital code (if the mixed signal circuit is an analog-to-digital conversion circuit, the digital code is directly output by the mixed signal circuit, if the mixed signal circuit is an analog-to-digital conversion circuit, the digital code is output by the analog-to-digital conversion circuit through analog-to-digital conversion of a signal of the analog circuit or the mixed signal circuit), outputs a static parameter test result after the test and returns an end signal to the test control circuit 11, and executes the third step;

step three: the test control circuit 11 instructs the test pattern generation circuit 12 to generate a sine wave signal, instructs the test response analysis circuit 13 to perform response analysis, and the test response analysis circuit 13 performs dynamic parameter test after receiving a digital code (if the mixed signal circuit is an analog-to-digital conversion circuit, the digital code is directly output by the mixed signal circuit, and if the analog circuit or the mixed signal circuit is a digital-to-analog conversion circuit, the digital code is output by the analog-to-digital conversion circuit through analog-to-digital conversion of a signal of the analog circuit or the mixed signal circuit), and outputs a dynamic parameter test result after the test is finished and returns a finished signal to the test control circuit.

Step four: and outputting a test result.

With the built-in self-test device provided in the embodiment of the present application, a test engineer may select 3 (as shown in table 1) or 7 (as shown in table 2) test modes as needed, and under different test modes, the test control circuit 11 controls the modules and/or sub-modules corresponding to the selected test mode in the test response analysis circuit to operate, while other modules and/or sub-modules not participating in the test are in an off state, so that power consumption of the built-in self-test device may be reduced.

In the above embodiment, in order to facilitate control of the switching state of the built-in self-test device, an on/off control pin may be added. When the pin inputs a signal meeting a preset condition, the built-in self-test device is determined to be started, for example, when the pin inputs a rising edge signal (firstly, a low level signal is input, and then, a high level signal is input), the built-in self-test device is started.

Specifically, the built-in self-test device provided by the embodiment of the application can be used for built-in self-test of an analog-to-digital conversion (A/DC) IP core or built-in self-test of a digital-to-analog conversion (D/AC) IP core in a mixed signal system on chip.

In the above embodiment, optionally, if the system on chip is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit, the test pattern generating circuit 12 is connected to the mixed signal circuit through a digital-to-analog conversion circuit.

The digital-to-analog conversion circuit converts the test waveform generated by the test pattern generation circuit 12 into analog stimulus, and therefore, the test pattern generation circuit 12 and the digital-to-analog conversion circuit are used in cooperation for the generation of the on-chip analog stimulus. In the embodiment of the application, the precision of the digital-to-analog conversion circuit is at least 2 bits higher than that of the analog-to-digital conversion circuit.

In the above embodiment, optionally, if the system on chip is integrated with a mixed signal circuit, and the mixed signal circuit is a digital-to-analog conversion circuit, the test response analysis circuit is connected to the mixed signal circuit through an analog-to-digital conversion circuit.

The analog-to-digital conversion circuit converts the analog output of the digital-to-analog conversion circuit into digital codes, and therefore the test response analysis circuit 13 and the analog-to-digital conversion circuit cooperate for test response analysis. In the embodiment of the application, the precision of the analog-to-digital conversion circuit is at least 2 bits higher than that of the digital-to-analog conversion circuit.

In the foregoing embodiment, optionally, a schematic structural diagram of the fault detection module 131 is shown in fig. 2, and may include:

a difference circuit 21, an accumulator 22, and a determiner 23; wherein,

the difference circuit 21 is configured to perform difference operation on the signal of the test pattern generated by the test pattern generation circuit and the signal output by the mixed signal circuit in response to the test pattern;

in the embodiment of the application, the test pattern generating circuit and the test response analyzing circuit are digital signal processing circuits.

The accumulator 22 is used for accumulating the absolute value of the difference operation result;

the decision device 23 is used for judging whether the mixed signal circuit has a fault according to the accumulation operation result.

Specifically, the decision device 23 may determine whether the accumulation operation result is within a preset range, if so, it indicates that the mixed signal circuit has no fault, otherwise, it indicates that the mixed signal circuit has a fault. The preset range refers to a range in which the mixed signal circuit can correctly respond to the test waveform under the influence of the variation of the parameters, the voltage and the temperature of the components and the noise.

In the foregoing embodiment, preferably, the parameter calculation module includes a static parameter sub-module, and a schematic structural diagram of the static parameter sub-module is shown in fig. 3, and may include:

a counter 31 and a first operator 32; wherein,

the counter 31 is used for counting the times of occurrence of each digital code of the signal output by the mixed signal circuit;

the number of times each digital code occurs may be stored in memory.

The first arithmetic unit 32 is used for calculating to obtain the static parameters according to the times of occurrence of each digital code of the signals output by the mixed signal circuit.

The static parameters may include: offset error, gain error, integral non-linear error and differential non-linear error; specifically, the calculation method of each static parameter may be:

$\mathrm{DNL}\left(i\right)=\frac{H\left(i\right)}{H_{\mathrm{ave}}}-1---\left(1\right)$

$\mathrm{INL}\left(i\right)=\underset{j=1}{\overset{i}{\mathrm{\Σ}}}\mathrm{DNL}\left(j\right)---\left(2\right)$

$V_{\mathrm{offset}}=H\left(2^N\right)-\frac{H\left(1\right)}{2*H_{\mathrm{ave}}}---\left(3\right)$

$\mathrm{Gain}=\frac{(N_2-N_1)*H_{\mathrm{ideal}}}{\underset{m=N_1}{\overset{N_2}{\mathrm{\Σ}}}H\left(m\right)}---\left(4\right)$

wherein, $H_{\mathrm{ave}}=\frac{\underset{n=2}{\overset{2^N-1}{\mathrm{\Σ}}}H\left(n\right)}{2^N-2};$

h (i) represents the number of times of occurrence of the ith digital code; n represents the precision of the analog-to-digital conversion circuit; dnl (i) represents a differential nonlinear error of the ith digital code; inl (i) represents the integral non-linear error of the ith digital code; v_offsetIndicating a misalignment error; gain represents the Gain error; n is a radical of₁＝1，N₂＝2^N-2；H_idealThe number of times each digital code appears in an ideal case, the slope of the ramp excitation (or triangular wave excitation), the sensitivity LSB of the mixed signal circuit, and the sampling rate f_sAnd the continuous period number X of the period slope, the specific calculation formula is as follows:

$\mathrm{Hideal}=\frac{\mathrm{LSB}}{\mathrm{slope}}\×f_s\×2\×X,\mathrm{LSB}=\frac{\mathrm{FSR}}{2^n},$ slope＝2×FSR_tri×f_triwherein

the FSR is the measuring range of the digital-to-analog conversion module or the analog-to-digital conversion module; FSR_triIs the range of the ramp (or triangle wave); f. of_triThe frequency of the periodic ramp (or triangle wave).

In the foregoing embodiment, preferably, the parameter calculation module includes a dynamic parameter sub-module, and a schematic structural diagram of the dynamic parameter sub-module is shown in fig. 4, and may include:

a converter 41 and a second arithmetic module 42; wherein,

the converter 41 is configured to perform fast fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

the second operation module 42 is configured to calculate a dynamic parameter according to a frequency spectrum of a signal output by the mixed signal circuit.

The dynamic parameters may include: signal-to-noise ratio, spurious-free dynamic range, total harmonic distortion ratio, signal-to-noise-distortion ratio, and significances; specifically, the calculation method of each dynamic parameter may be:

calculating the total power of the signals output by the mixed signal circuit, the signal power of the signals output by the mixed signal circuit and the power of each subharmonic of the signals output by the mixed signal circuit according to the frequency spectrum of the signals output by the mixed signal circuit;

subtracting the signal power and the harmonic power from the total power to obtain noise power;

specifically, when a dynamic parameter needs to be calculated, a certain number of output sampling points are collected under sinusoidal excitation, and a frequency spectrum of an output signal is obtained by Fast Fourier Transform (FFT) of the points, the frequency spectrum records a frequency range from a fundamental frequency to fs/2, the magnitude of signal amplitude in each frequency band (span) is assumed that the number of FFT points is 8192, the number of spans is 4096, and the signal amplitude of each span is D (span _ i), then:

total power: ptotal ═ sum ((D (span _1)²:(D(span_4096)²)；

Signal power: finding the span _ signal at the maximum of the amplitude except for the fundamental span _1, the range of the neighborhood + -5 is the signal power, the signal sum (D (span _ signal-5)²:(D(span_signal+5)²)；

Harmonic power: refers to the sum of the power of each harmonic, the frequency of each harmonic being equal to an integer multiple of the signal frequency, so that the 2 nd harmonic is located around 2 span _ signal and 3 rd harmonic around 3 span _ signal. Due to the constraint of Nyquist sampling theorem, the frequency exceeds span of fs/2, conjugate is mapped into the interval of 1-fs/2, and there are two cases in total: 1 if the harmonic span _ h is greater than 4096 and less than 8192, span _ h will map to the (8192-span _ h) location, 2 if span _ h is greater than 8192 and less than 12288, span _ h will map to the (span _ h-8192) location. And so on. If the harmonic frequency overlaps the fundamental frequency, the subharmonic power is not calculable. After the harmonic span position is obtained, the calculation method is similar to the signal power calculation method.

Specifically, the calculation method of each dynamic parameter may be:

SNR＝10lg(P_signal/P_noise) (5)

SFDR＝10lg(P_signal/P_harmonic-max) (6)

$\mathrm{SNDR}=10\lg (\frac{P_{\mathrm{signal}}}{P_{\mathrm{noise}}}+P_{\mathrm{harmonic}})---\left(7\right)$

THD＝10lg(P_harmonic/P_signal) (8)

ENOB＝(SNDR-1.76)/6.02 (9)

wherein SNR represents a signal-to-noise ratio; p_signalRepresents the signal power; p_noiseRepresenting the noise power; SFDR represents the spurious-free dynamic range; SNDR represents a signal-to-noise-and-distortion ratio; THD represents a total harmonic distortion ratio; ENOB denotes the number of significant digits; p_harmonic-maxThe power of the harmonic wave with the maximum amplitude; p_harmonicIs the total harmonic power.

In the conventional a/DC test, an Automatic Test Equipment (ATE) or an analog test equipment is selected to perform a function-based parametric test on the a/DC test chip. In a system on chip, an A/DC is used as an IP core, the problems of uncontrollable and unobservable signals and the like exist, and in the traditional built-in self-test method based on functions, an analog circuit is used for generating analog excitation, and a Digital Signal Processor (DSP) is used for analyzing the A/DC response depending on whether the DSP exists or not. Typical fault-based analog mixed-signal circuit BIST architectures are more design-intensive and are not capable of function-based testing.

The BIST structure provided by the invention can well solve the problems.

The on-chip test pattern generation circuit and the test response analysis circuit can solve the problems of uncontrollable and unobservable signals, reduce the dependence of the test of an analog mixed signal circuit (comprising an analog-digital conversion circuit and a digital-analog conversion circuit) on test equipment and reduce the test cost.

Not only can the fault-based test be completed, but also the function-based test can be completed.

The test mode can be flexibly selected, a yield test solution can be provided for batch production of a mixed signal system on chip (such as an SoC comprising A/DC), and when the mixed signal circuit is only required to be judged whether to have a fault or not, the fault detection test mode is used, so that the test time can be saved.

In addition to the mixed signal circuit, other modules of the BIST circuit can be described by parameterized VHDL or Verilog, which is beneficial to rapid and convenient synthesis and synthesis, testability design of the BIST circuit and formation of a reusable BIST IP core, and can be applied to any mixed signal on-chip system and an analog/mixed signal system based on FPGA.

In the above embodiment, optionally, if the system on chip is integrated with an analog circuit, the test pattern generating circuit 12 is connected to the analog circuit through a digital-to-analog conversion circuit; the test response analyzing circuit 13 is connected to the analog circuit through an analog-to-digital conversion circuit.

In the foregoing embodiment, preferably, the built-in self-test device provided in the embodiment of the present application may further include a reset pin configured to receive a clear signal and clear the test response analysis circuit.

The embodiment of the application also provides a system on chip, and the system on chip is provided with the built-in self-test device provided by any one of the embodiments.

Corresponding to the device embodiment, the embodiment of the present application further provides a built-in self-test method, which is applied to a system on chip, the system on chip is integrated with an analog/mixed signal circuit, and the system on chip is further integrated with: the test control circuit is connected with the analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; the test response analysis circuit comprises a fault detection module and a parameter calculation module; an implementation flowchart of the built-in self-test method provided in the embodiment of the present application is shown in fig. 5, and may include:

step S51: the test control circuit monitors whether a test mode signal is input;

step S52: when the input of a test mode signal is monitored, the test control circuit instructs the test pattern generating circuit to generate a test pattern corresponding to the test mode and instructs the test response analyzing circuit to switch to a working mode corresponding to the test mode;

the operating mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode;

when the fault detection module is in a working state, judging whether the analog/mixed signal circuit has a fault or not according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, namely when the fault detection module is in the working state, testing based on the fault can be realized;

when the parameter calculation module is in a working state, parameters corresponding to the analog/mixed signal circuit are calculated according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, wherein the parameters comprise static parameters and/or dynamic parameters, namely, when the parameter calculation module is in the working state, the function-based test can be realized.

The test pattern generating circuit 12 may adopt a test pattern generating circuit of a linear feedback shift register structure, and the test pattern generating circuit 12 may generate various test waveforms including a pseudo random wave, a ramp wave, a sawtooth wave, a triangular wave, a step wave, a square wave, and a sine wave of a certain frequency.

Each test pattern may correspond to one test pattern, or may correspond to two or more test patterns. When the test pattern is corresponding to two or more types of test patterns, the generation sequence of the two or more types of test patterns and the generation time of the test patterns can be determined according to the test requirements, and the test patterns are generated at the corresponding generation time according to the generation sequence of the test patterns in the test process and output to the analog/mixed signal circuit.

The built-in self-test method provided by the embodiment of the application is applied to a system on chip, the system on chip is integrated with an analog/mixed signal circuit, and the device comprises: the test control circuit, the test pattern generating circuit, the test response analyzing circuit and the memory; the test response analysis circuit comprises a fault detection module and a parameter calculation module; when monitoring a test mode signal, the test control circuit controls the test pattern generation circuit to generate a test pattern corresponding to the test mode, and controls the test response analysis circuit to switch to a working mode corresponding to the test mode, wherein the working mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode; the fault detection module is used for judging whether the analog/mixed signal circuit has faults or not; the parameter calculation module is used for calculating parameters corresponding to the analog/mixed signal circuit, and the parameters comprise static parameters and/or dynamic parameters.

In summary, according to the built-in self-test method provided by the embodiment of the present application, different test mode signals correspond to different working modes of the test response analysis circuit, so that not only a fault-based test but also a function-based test can be performed, or the fault-based test and the function-based test are performed in a mixed manner, thereby implementing a multi-mode test on an analog/mixed signal circuit.

In the foregoing embodiment, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, the flowchart for determining whether the mixed signal circuit has a fault according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit is shown in fig. 6, and may include:

step S61: carrying out difference operation on the test pattern signal generated by the test pattern generating circuit and the signal output by the mixed signal circuit responding to the test pattern;

step S62: performing accumulation operation on the absolute value of the difference operation result;

step S63: and judging whether the mixed signal circuit has faults or not according to the accumulation operation result.

Specifically, whether the accumulation operation result is within a preset range can be judged, if so, it is indicated that the mixed signal circuit has no fault, otherwise, it is indicated that the mixed signal circuit has a fault. The preset range refers to a range in which the mixed signal circuit can correctly respond to the test waveform under the influence of the variation of the parameters, the voltage and the temperature of the components and the noise.

In the foregoing embodiment, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a static parameter, an implementation flowchart of calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit is shown in fig. 7, and may include:

step S71: counting the occurrence times of each digital code of the signal output by the mixed signal circuit;

the number of times each digital code occurs may be stored in memory.

Step S72: and calculating to obtain static parameters according to the occurrence times of each digital code of the signal output by the mixed signal circuit.

The static parameters may include: offset error, gain error, integral non-linear error and differential non-linear error; specifically, the embodiment shown in fig. 3 can be referred to as a method for calculating each static parameter, and details are not repeated here.

In the foregoing embodiment, preferably, if the soc is integrated with a mixed signal circuit, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a dynamic parameter, another implementation flowchart for calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit is shown in fig. 8, and may include:

step S81: performing fast Fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

step S82: and calculating to obtain dynamic parameters according to the frequency spectrum of the signal output by the mixed signal circuit.

The dynamic parameters may include: signal-to-noise ratio, spurious-free dynamic range, total harmonic distortion ratio, signal-to-noise distortion ratio, and significances; specifically, the embodiment shown in fig. 4 can be referred to as a calculation method of each dynamic parameter, and details are not repeated here.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (14)

1. A built-in self-test apparatus for a system-on-chip integrated with analog/mixed signal circuitry, the apparatus comprising: the test control circuit is connected with the analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; wherein,

the test response analysis circuit comprises a fault detection module and a parameter calculation module;

the test control circuit is configured to instruct the test pattern generation circuit to generate a test pattern corresponding to the test mode and instruct the test response analysis circuit to switch to a working mode corresponding to the test mode when a test mode signal is monitored, where the working mode of the test response analysis circuit includes: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode;

the fault detection module is used for judging whether the analog/mixed signal circuit has faults or not according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit;

the parameter calculation module is used for calculating parameters corresponding to the analog/mixed signal circuit according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, and the parameters comprise static parameters and/or dynamic parameters.

2. The apparatus of claim 1, wherein the parameter calculation module comprises:

a static parameter calculation submodule and/or a dynamic parameter calculation submodule.

3. The apparatus of claim 2, wherein when the parameter calculation module comprises a static parameter calculation sub-module and a dynamic parameter calculation sub-module, the operation mode of the parameter calculation module comprises:

the static parameter calculation submodule is in an independent starting mode, the dynamic parameter calculation submodule is in an independent starting mode, or the static parameter calculation submodule and the dynamic parameter calculation submodule are both in a starting mode.

4. The apparatus of claim 1, wherein if the soc has a mixed signal circuit integrated therein and the mixed signal circuit is an analog-to-digital conversion circuit, the test pattern generation circuit is connected to the mixed signal circuit through the digital-to-analog conversion circuit.

5. The apparatus of claim 1, wherein if the system-on-chip has a mixed-signal circuit integrated therein and the mixed-signal circuit is a digital-to-analog conversion circuit, the test response analyzing circuit is connected to the mixed-signal circuit through an analog-to-digital conversion circuit.

6. The apparatus of claim 4 or 5, wherein the fault detection module comprises:

the differential circuit is used for carrying out differential operation on the test pattern signal generated by the test pattern generating circuit and the signal output by the mixed signal circuit responding to the test pattern;

the accumulator is used for carrying out accumulation operation on the absolute value of the difference operation result;

and the decision device judges whether the mixed signal circuit has faults or not according to the accumulation operation result.

7. The apparatus of claim 4 or 5, wherein the parameter calculation module comprises a static parameter sub-module, the static parameter sub-module comprising:

the counter is used for counting the occurrence times of each digital code of the signal output by the mixed signal circuit;

and the first arithmetic unit is used for calculating to obtain the static parameters according to the occurrence times of each digital code of the signals output by the mixed signal circuit.

8. The apparatus of claim 4 or 5, wherein the parameter calculation module comprises a dynamic parameter sub-module, the dynamic parameter sub-module comprising:

the converter is used for carrying out fast Fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

and the second operation module is used for calculating to obtain dynamic parameters according to the frequency spectrum of the signal output by the mixed signal circuit.

9. The apparatus of claim 1, wherein if the system on a chip is integrated with an analog circuit, the test pattern generating circuit is connected to the analog circuit through a digital-to-analog converting circuit, and the test response analyzing circuit is connected to the analog circuit through an analog-to-digital converting circuit.

10. A system on a chip comprising the built-in self-test apparatus of any one of claims 1-9.

11. A built-in self-test method applied to a system-on-chip, the system-on-chip being integrated with an analog/mixed signal circuit, the system-on-chip further comprising: the test control circuit is connected with the analog/mixed signal circuit; the test pattern generating circuit and the test response analyzing circuit are connected with the test control circuit; a memory coupled to the test response analysis circuit; the test pattern generating circuit and the test response analyzing circuit are also respectively connected with the analog/mixed signal circuit; the test response analysis circuit comprises a fault detection module and a parameter calculation module; the method comprises the following steps:

when the test control circuit monitors that a test mode signal is input, the test control circuit instructs the test pattern generation circuit to generate a test pattern corresponding to the test mode and instructs the test response analysis circuit to switch to a working mode corresponding to the test mode, wherein the working mode of the test response analysis circuit comprises: the fault detection module is in an independent starting mode, the parameter calculation module is in an independent starting mode, or the fault detection module and the parameter calculation module are both in a starting mode;

when the fault detection module is in a working state, judging whether the analog/mixed signal circuit has a fault according to response information of the analog/mixed signal circuit to a test pattern generated by the test pattern generation circuit;

and when the parameter calculation module is in a working state, calculating parameters corresponding to the analog/mixed signal circuit according to response information of the analog/mixed signal circuit to the test pattern generated by the test pattern generation circuit, wherein the parameters comprise static parameters and/or dynamic parameters.

12. The method of claim 11, wherein if the soc has a mixed signal circuit integrated therein, and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, determining whether the mixed signal circuit has a fault according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit comprises:

carrying out difference operation on the test pattern signal generated by the test pattern generating circuit and the signal output by the mixed signal circuit responding to the test pattern;

performing accumulation operation on the absolute value of the difference operation result;

and judging whether the mixed signal circuit has faults or not according to the accumulation operation result.

13. The method of claim 11, wherein if the soc has a mixed signal circuit integrated therein and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a static parameter, calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit comprises:

counting the occurrence times of each digital code of the signal output by the mixed signal circuit;

and calculating to obtain static parameters according to the occurrence times of each digital code of the signal output by the mixed signal circuit.

14. The method of claim 11, wherein if the soc has a mixed signal circuit integrated therein and the mixed signal circuit is an analog-to-digital conversion circuit or a digital-to-analog conversion circuit, when the parameter is a dynamic parameter, calculating a parameter corresponding to the mixed signal circuit according to response information of the mixed signal circuit to the test pattern generated by the test pattern generation circuit comprises:

performing fast Fourier transform on the signal output by the mixed signal circuit to obtain a frequency spectrum of the signal output by the mixed signal circuit;

and calculating to obtain dynamic parameters according to the frequency spectrum of the signal output by the mixed signal circuit.