CN105988077B - Build-in self-test method, device and system on chip - Google Patents
Build-in self-test method, device and system on chip Download PDFInfo
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- CN105988077B CN105988077B CN201510062392.9A CN201510062392A CN105988077B CN 105988077 B CN105988077 B CN 105988077B CN 201510062392 A CN201510062392 A CN 201510062392A CN 105988077 B CN105988077 B CN 105988077B
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Abstract
The embodiment of the invention discloses a kind of build in self test apparatus, including the test control circuit being connected with analog/mixed signal circuit；The test patterns generation circuit and test response analysis circuit being connected with the test control circuit；The memory being connected with the test response analysis circuit；The test patterns generation circuit and the test response analysis circuit are also connected with the analog/mixed signal circuit respectively；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；The test control circuit is used for when monitoring test mode signal, it indicates test patterns generation circuit evolving resolution chart corresponding with the test pattern, and indicates that the test response analysis circuit switches to operating mode corresponding with the test pattern.The multimode test to analog/mixed signal circuit may be implemented.The embodiment of the present application also provides a kind of build-in self-test method and system on chip.
Description
Technical field
The present invention relates to the field of test technology, more specifically to a kind of build-in self-test method, device and on piece system
System.
Background technique
Integrated circuit technique has had evolved to system on chip (System on a Chip, the SoC) stage, and test is SoC
One of key technology.In addition to integrating a large amount of digital circuit intellectual property (Intellectual Property, IP) in SoC
Core is also integrated with analog circuit or digital-to-analogue mixed signal circuit (hereinafter referred to as analog/mixed signal circuit) IP kernel.For mould
Quasi-/mixed signal circuit, since the Testability Design tool mature not as digital integrated electronic circuit is supported, grind
The test structure and self-test method for studying carefully analog/mixed signal circuit in SoC, be in SoC design for Measurability urgently consider and
It solves the problems, such as.
There are two types of basic test methods for analog/mixed signal IP kernel: functional test and structured testing.Functional test is derived from
The test of product specification, it is therefore an objective to check whether circuit meets design requirement, functional test the main contents include DC parameter (
Claim static parameter) and alternating-current parameter (also referred to as dynamic parameter).Structured testing is derived from the test of defect, also referred to as based on failure
Test, existing fault model are critical failure and parametic fault, and critical failure model describes interconnector open circuit or short
The situations such as road, parametic fault model describe component values beyond the situation for allowing variation range.
Built-in self-test (Biuld-In-Self-Test, BIST) is a kind of realization technology of Testability Design.In electricity
Establish Self -adaptive, application, analysis and testing and control structure inside road, circuit enabled to test itself, here it is it is built-in from
Test.Since built-in self-test is to complete test process in piece, it is possible to reduce to the dependence of high-performance test equipment when test
Property, so as to reduce testing time and the testing cost of IP kernel.Therefore, current more and more analog/mixed signal IP kernels
Test use BIST Structure.
However, to the test of analog/mixed signal IP kernel or being surveyed based on function using BIST Structure at present
The BIST Structure of examination or be the BIST Structure based on fault test, test mode is relatively simple.
Summary of the invention
The object of the present invention is to provide a kind of build-in self-test method, device and systems on chip, to realize to analog/hybrid
The multimode of signal circuit is tested.
To achieve the above object, the present invention provides the following technical scheme that
A kind of build in self test apparatus, is applied to system on chip, and the system on chip has analog/mixed signal electric
Road, described device include: the test control circuit being connected with the analog/mixed signal circuit；With the testing and control electricity
The test patterns generation circuit and test response analysis circuit that road is connected；It is deposited with what the test response analysis circuit was connected
Reservoir；The test patterns generation circuit and the test response analysis circuit also respectively with the analog/mixed signal circuit
It is connected；Wherein,
The test response analysis circuit includes fault detection module and parameter calculating module；
The test control circuit is used for when monitoring test mode signal, indicates that the test patterns generation circuit is raw
At resolution chart corresponding with the test pattern, and indicate that the test response analysis circuit switches to and the test mould
The operating mode of the corresponding operating mode of formula, the test response analysis circuit includes: fault detection module independent startup mould
Formula, parameter calculating module independent startup mode, alternatively, fault detection module and the equal start-up mode of parameter calculating module；
The fault detection module is used for raw to the test patterns generation circuit according to the analog/mixed signal circuit
At resolution chart response message, judge the analog/mixed signal circuit with the presence or absence of failure；
The parameter calculating module is used for raw to the test patterns generation circuit according to the analog/mixed signal circuit
At resolution chart response message, calculate corresponding with analog/mixed signal circuit parameter, the parameter includes quiet
State parameter and/or dynamic parameter.
Above-mentioned apparatus, it is preferred that the parameter calculating module includes:
Static parameter computational submodule and/or dynamic parameter computational submodule.
Above-mentioned apparatus, it is preferred that when the parameter calculating module includes static parameter computational submodule and dynamic parameter meter
When operator module, the operating mode of the parameter calculating module includes:
Static parameter computational submodule independent startup mode, dynamic parameter computational submodule independent startup mode, alternatively, quiet
State parameter computation module and the equal start-up mode of dynamic parameter computational submodule.
Above-mentioned apparatus, it is preferred that if the system on chip has mixed signal circuit, and the mixed signal circuit is
Analog to digital conversion circuit, then the test patterns generation circuit is connected by D/A converting circuit with the mixed signal circuit.
Above-mentioned apparatus, it is preferred that if the system on chip has mixed signal circuit, and the mixed signal circuit is
D/A converting circuit, then the test response analysis circuit is connected by analog to digital conversion circuit with the mixed signal circuit.
Above-mentioned apparatus, it is preferred that the fault detection module includes:
Difference channel, for the resolution chart signal of the test patterns generation circuit evolving and the mixed signal is electric
The signal that road responds the resolution chart output does difference operation；
Accumulator, the absolute value for the result to difference operation do accumulating operation；
Decision device judges whether the mixed signal circuit breaks down according to accumulating operation result.
Above-mentioned apparatus, it is preferred that the parameter calculating module includes static parameter submodule, the static parameter submodule
Include:
Counter, the number occurred for counting each digital code of signal of the mixed signal circuit output；
First arithmetic device, based on the number that each digital code of the signal by exporting according to the mixed signal circuit occurs
Calculation obtains static parameter.
Above-mentioned apparatus, it is preferred that the parameter calculating module includes dynamic parameter submodule, the dynamic parameter submodule
Include:
Converter, the signal for exporting to the mixed signal circuit carry out Fast Fourier Transform (FFT), obtain described mixed
Close the frequency spectrum of the signal of signal circuit output；
Second computing module, dynamic, which is calculated, in the frequency spectrum of the signal for exporting according to the mixed signal circuit joins
Number.
Above-mentioned apparatus, it is preferred that if the system on chip has analog circuit, the test patterns generation circuit is logical
D/A converting circuit is crossed to be connected with the analog circuit, the test response analysis circuit by analog to digital conversion circuit with it is described
Analog circuit is connected.
A kind of system on chip, including build in self test apparatus described in any one as above.
A kind of build-in self-test method, is applied to system on chip, and the system on chip has analog/mixed signal electric
Road, the system on chip further include: the test control circuit being connected with the analog/mixed signal circuit；With the test
The test patterns generation circuit and test response analysis circuit that control circuit is connected；It is connected with the test response analysis circuit
The memory connect；The test patterns generation circuit and the test response analysis circuit are also believed with the analog/hybrid respectively
Number circuit is connected；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；The method
Include:
When the test control circuit monitors test mode signal input, the test patterns generation circuit evolving is indicated
Resolution chart corresponding with the test pattern, and indicate that the test response analysis circuit switches to and the test pattern
The operating mode of corresponding operating mode, the test response analysis circuit includes: fault detection module independent startup mode,
Parameter calculating module independent startup mode, alternatively, fault detection module and the equal start-up mode of parameter calculating module；
When the fault detection module is in running order, according to the analog/mixed signal circuit to the test chart
The response message for the resolution chart that shape generative circuit generates judges the analog/mixed signal circuit with the presence or absence of failure；
When the parameter calculating module is in running order, according to the analog/mixed signal circuit to the test chart
The response message for the resolution chart that shape generative circuit generates calculates parameter corresponding with the analog/mixed signal circuit, institute
Stating parameter includes static parameter and/or dynamic parameter.
The above method, it is preferred that if the system on chip has mixed signal circuit, and the mixed signal circuit is
Analog to digital conversion circuit or D/A converting circuit, then according to the mixed signal circuit to the test patterns generation circuit evolving
The response message of resolution chart judges that the mixed signal circuit includes: with the presence or absence of failure
The resolution chart signal of the test patterns generation circuit evolving and the mixed signal circuit are responded into the survey
The signal of examination images outputting does difference operation；
Accumulating operation is done to the absolute value of the result of difference operation；
Judge whether the mixed signal circuit breaks down according to accumulating operation result.
The above method, it is preferred that if the system on chip has mixed signal circuit, and the mixed signal circuit is
Analog to digital conversion circuit or D/A converting circuit, then when the parameter is static parameter, according to the mixed signal circuit to institute
The response message of the resolution chart of test patterns generation circuit evolving is stated, parameter corresponding with the mixed signal circuit is calculated
Include:
Count the number that each digital code of the signal of the mixed signal circuit output occurs；
Static parameter is calculated in the number that each digital code of signal according to mixed signal circuit output occurs.
The above method, it is preferred that if the system on chip has mixed signal circuit, and the mixed signal circuit is
Analog to digital conversion circuit or D/A converting circuit, then when the parameter is dynamic parameter, according to the mixed signal circuit to institute
The response message of the resolution chart of test patterns generation circuit evolving is stated, parameter corresponding with the mixed signal circuit is calculated
Include:
Fast Fourier Transform (FFT) is carried out to the signal of mixed signal circuit output, it is defeated to obtain the mixed signal circuit
The frequency spectrum of signal out；
Dynamic parameter is calculated in the frequency spectrum of signal according to mixed signal circuit output.
By above scheme it is found that a kind of build-in self-test method, device and system on chip provided by the present application, described
The upper system integration has analog/mixed signal circuit, test control circuit, and test patterns generation circuit tests response analysis circuit
And memory；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；Test control circuit
When monitoring test mode signal, test patterns generation circuit evolving test chart corresponding with the test pattern is indicated
Shape, and indicate that the test response analysis circuit switches to operating mode corresponding with the test pattern, the test is rung
The operating mode that circuit should be analyzed includes: fault detection module independent startup mode, parameter calculating module independent startup mode, or
Person, fault detection module and the equal start-up mode of parameter calculating module；The fault detection module is for judging the analog/hybrid
Signal circuit whether there is failure；The parameter calculating module is corresponding with the analog/mixed signal circuit for calculating
Parameter, the parameter include static parameter and/or dynamic parameter.
To sum up, pass through build-in self-test method provided by the embodiments of the present application, device and system on chip, different test moulds
The different working modes of the corresponding test response analysis circuit of formula signal, to not only can only carry out the test based on failure, but also can
Only to carry out the test based on function, alternatively, the test based on failure and the test based on function are mixed and carried out, realize to mould
The multimode test of quasi-/mixed signal circuit.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of build in self test apparatus provided by the embodiments of the present application；
Fig. 2 is a kind of structural schematic diagram of fault detection module provided by the embodiments of the present application；
Fig. 3 is a kind of structural schematic diagram of static parameter submodule provided by the embodiments of the present application；
Fig. 4 is a kind of structural schematic diagram of dynamic parameter submodule provided by the embodiments of the present application；
Fig. 5 is a kind of implementation flow chart of build-in self-test method provided by the embodiments of the present application；
Fig. 6 is the test chart provided by the embodiments of the present application according to mixed signal circuit to test patterns generation circuit evolving
The response message of shape judges that mixed signal circuit whether there is a kind of implementation flow chart of failure；
Fig. 7 is the test chart provided by the embodiments of the present application according to mixed signal circuit to test patterns generation circuit evolving
The response message of shape calculates a kind of implementation flow chart of parameter corresponding with mixed signal circuit；
Fig. 8 is the test chart provided by the embodiments of the present application according to mixed signal circuit to test patterns generation circuit evolving
The response message of shape calculates another implementation flow chart of parameter corresponding with mixed signal circuit.
Specification and claims and term " first " in above-mentioned attached drawing, " second ", " third " " the 4th " etc. (if
In the presence of) it is part for distinguishing similar, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so that embodiments herein described herein can be in addition to illustrating herein
Sequence in addition is implemented.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Build in self test apparatus provided by the embodiments of the present application and method are applied to system on chip, which has
Analog circuit or digital-to-analogue mixed signal circuit (hereinafter referred to as analog/mixed signal circuit), it is provided by the embodiments of the present application built-in
Self-test device is for testing the analog/mixed signal circuit.
Referring to Fig. 1, Fig. 1 is a kind of structural schematic diagram of build in self test apparatus provided by the embodiments of the present application, it can be with
Include:
Test control circuit 11, test patterns generation circuit 12 test response analysis circuit 13 and memory 14；Wherein,
Test control circuit 11 respectively with test patterns generation circuit 12, test response analysis circuit 13 and analog/hybrid
Signal circuit is connected；
Test patterns generation circuit 12 and test response analysis circuit 13 are also connected with analog/mixed signal circuit respectively
It connects；
Test patterns generation circuit 12 can use the test patterns generation circuit of linear feedback shift register structure, survey
Attempting shape generative circuit 12 can be generated a variety of test waveforms, including pseudorandom wave, slope wave, sawtooth wave, triangular wave, ladder
The sine wave of wave, square wave and certain frequency.
Testing response analysis circuit 13 includes fault detection module 131 and parameter calculating module 132；Wherein,
Fault detection module 131 is used for raw to the test patterns generation circuit according to the analog/mixed signal circuit
At resolution chart response message, judge the analog/mixed signal circuit with the presence or absence of failure, i.e. fault detection module
131 it is in running order when, the test based on failure may be implemented.
Parameter calculating module 132 is used for raw to the test patterns generation circuit according to the analog/mixed signal circuit
At resolution chart response message, calculate corresponding with analog/mixed signal circuit parameter, the parameter includes quiet
When that is, parameter calculating module 132 is in running order, the test based on function is may be implemented in state parameter and/or dynamic parameter.
In the embodiment of the present application, when needing to calculate static parameter, test chart can be controlled by test control circuit 11
Shape generative circuit 12 generates linear waveform signal, such as triangular signal or slope wave signal, and works as and need to calculate dynamic parameter
When, test patterns generation circuit 12 can be controlled by test control circuit 11 and generate sine wave signal.
The operating mode for testing response analysis circuit 13 may include: 131 independent startup mode of fault detection module, parameter
132 independent startup mode of computing module, alternatively, fault detection module 131 and the equal start-up mode of parameter calculating module 132；Specifically
Select which kind of operating mode that can select to determine by user according to actual needs.
It wherein, can be in fault detection mould under fault detection module 131 and the equal start-up mode of parameter calculating module 132
After the completion of block 131 works, parameter calculating module 132 carries out relevant work again；Alternatively, can work in parameter calculating module 132
After the completion, fault detection module 131 carries out relevant work again.Specially which kind of mode can determine according to actual needs.
Preferably, in order to save testing time of bad piece, fault test can be first carried out, test has passed through carrying out parameter again
Test, if test does not pass through, no longer progress parameter testing.
Memory 14 is connected with test response analysis circuit 13, needs to save during built-in self-test for storing
Information.
For example, can store the data used in parameter calculation procedure in memory 14.
Testing process can take sequential testing method in the embodiment of the present application, storage resource can according to testing process into
Row time-sharing multiplex (i.e. time segment is multiplexed the same memory), can reduce the area overhead of memory in this way.
For example, static parameter and dynamic parameter are separately tested in the embodiment of the present invention, then, static parameter test
It can time-sharing multiplex memory 14 with dynamic parametric test.
For another example butterfly computation may be used when carrying out dynamic parametric test, wherein a butterfly processing element,
The data for needing to save include input data and output data, then time-sharing multiplex can refer to: the first order starts successively to ask the 1st
A, the 2nd, the 3rd ... butterfly operation, what the first storage region of memory 14 saved is the defeated of first order butterfly computation
Enter, what the second storage region of memory 14 saved is the output of first order butterfly computation, when seeking second level butterfly computation, the
The output (i.e. the data of the second storage region preservation of memory 14) of level-one butterfly computation can be used as the 2nd grade of butterfly computation
Input, the output of the 2nd grade of butterfly computation can be stored in the first storage region of memory 14, and so on.
Test control circuit 11 is for having monitored whether test mode signal generation, when monitoring test mode signal,
Indicate that test patterns generation circuit 12 generates resolution chart corresponding with the test pattern.Wherein, each test pattern
A kind of lower possible corresponding resolution chart, it is also possible to two or more corresponding resolution charts.When two or more corresponding tests
When figure, the generation of the genesis sequence and resolution chart of described two or more resolution charts can be determined according to testing requirement
Opportunity generates resolution chart on corresponding generation opportunity according to the genesis sequence of resolution chart during the test and exports to mould
Quasi-/mixed signal circuit.
The application belongs to offline built-in self-test, and test control circuit 11 can have been monitored whether by two test pins
Test mode signal generates.Specifically, can monitor whether that test mode signal is raw by pattern configurations mode as described in Table 1
At.
Table 1
| Serial number | TM2 | TM1 | Open/close state | Mode |
| 0 | 0 | 0 | It closes | |
| 1 | 0 | 1 | It opens | Startup separator detection pattern |
| 2 | 1 | 0 | It opens | Start-up parameter test pattern |
| 3 | 1 | 1 | It opens | Start hybrid test mode |
TM1 and TM2 indicate two test pins, in the embodiment of the present application, when the equal input low level of two test pins,
Indicate that self-built interior survey device is closed.In two test pins, as long as the input for having a pin is high level, then it represents that self-built
Interior survey device is opened, specifically, working as TM1 pin input low level (being indicated in table 1 with 0), and TM2 pin input high level (table 1
It is middle to be indicated with 1) when, it indicates to open parameter calculating module independent startup mode, i.e. parameter testing mode；When TM1 pin inputs height
Level, and when TM2 pin input low level, it indicates to open fault detection module independent startup mode, i.e. fault detection mode；When
When TM1 pin and the equal input high level of TM2 pin, indicate to open fault detection module and the equal start-up mode of parameter calculating module,
That is hybrid test mode.
Test control circuit 11 also indicates test response analysis circuit 13 for Working mould when monitoring test mode signal
Formula switches to operating mode corresponding with the test pattern.
In the embodiment of the present application, test control circuit 11, test patterns generation circuit 12, test 13 and of response analysis circuit
Memory 14 can be digital circuit.
A kind of build in self test apparatus provided by the embodiments of the present application, is applied to system on chip, and system on chip has mould
Quasi-/mixed signal circuit, described device include: test control circuit, test patterns generation circuit, test response analysis circuit and
Memory；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；Test control circuit prison
When measuring test mode signal, test patterns generation circuit evolving test chart corresponding with the test pattern is controlled
Shape, and control the test response analysis circuit and switch to operating mode corresponding with the test pattern, the test is rung
The operating mode that circuit should be analyzed includes: fault detection module independent startup mode, parameter calculating module independent startup mode, or
Person, fault detection module and the equal start-up mode of parameter calculating module；The fault detection module is for judging the analog/hybrid
Signal circuit whether there is failure；The parameter calculating module is corresponding with the analog/mixed signal circuit for calculating
Parameter, the parameter include static parameter and/or dynamic parameter.
To sum up, pass through build in self test apparatus provided by the embodiments of the present application, the corresponding test of different test mode signals
The different working modes of response analysis circuit to not only can only carry out the test based on failure, but also can only carry out being based on function
The test of energy realizes alternatively, the test based on failure and the mixing of the test based on function carry out to analog/mixed signal electricity
The multimode on road is tested.
In above-described embodiment, it is preferred that the parameter calculating module includes that static parameter computational submodule and/or dynamic are joined
Number computational submodule.
Static parameter computational submodule is for calculating static parameter；Dynamic parameter computational submodule is joined for calculating dynamic
Number.
Specifically, parameter calculating module can be designed according to application environment.For example, some analog/mixed signal electricity
Road may only need to calculate static parameter or only need to calculate dynamic parameter, and in this case, parameter calculating module can only be set
Static parameter computational submodule is counted, or only designs dynamic parameter submodule, to minimize occupied by built-in self-test device
Area, reduce area overhead.
In above-described embodiment, it is preferred that when the parameter calculating module includes that static parameter computational submodule and dynamic are joined
When number computational submodule, the operating mode of the parameter calculating module includes:
Static parameter computational submodule independent startup mode, dynamic parameter computational submodule independent startup mode, alternatively, quiet
State parameter computation module and the equal start-up mode of dynamic parameter computational submodule.
When parameter calculating module is in static parameter computational submodule and the equal start-up mode of dynamic parameter computational submodule,
Static parameter computational submodule can be first passed through and calculate static parameter, dynamic is then calculated by dynamic parameter computational submodule again
Parameter；Alternatively, can first pass through dynamic parameter computational submodule calculates dynamic parameter, submodule is then calculated by static parameter again
Block calculates static parameter.
In above-described embodiment, it is preferred that when the parameter calculating module includes that static parameter computational submodule and dynamic are joined
When number computational submodule, build in self test apparatus provided by the embodiments of the present application can support seven kinds of test patterns, testing and control
Circuit 11 can really monitor whether test mode signal generation by three test pins.Specifically, such as 2 institute of table can be passed through
Show that pattern configurations mode has monitored whether test mode signal generation.
Table 2
| Serial number | TM3 | TM2 | TM1 | Open/close state | Mode |
| 0 | 0 | 0 | 0 | It closes | |
| 1 | 0 | 0 | 1 | It opens | Startup separator detection pattern |
| 2 | 0 | 1 | 0 | It opens | Start static parameter test mode |
| 3 | 0 | 1 | 1 | It opens | Start dynamic parametric test mode |
| 4 | 1 | 0 | 0 | It opens | Startup separator detection and static parameter test |
| 5 | 1 | 0 | 1 | It opens | Startup separator detection and dynamic parametric test |
| 6 | 1 | 1 | 0 | It opens | Start static parameter and dynamic parametric test |
| 7 | 1 | 1 | 1 | It opens | Start hybrid test mode |
TM1, TM2 and TM3 indicate three test pins, in the embodiment of the present application, when three test pins input low electricity
Usually, indicate that self-built interior survey device is closed.In three test pins, as long as the input for having a pin is high level, table
Show that self-built interior survey device is opened, specifically, working as TM1 pin input high level, and TM2 pin and the equal input low level of TM3 pin
When, it indicates to open fault detection module independent startup mode, i.e. fault detection mode；When TM2 pin input high level, and TM1
When pin and the equal input low level of TM3 pin, indicate to open static parameter computational submodule independent startup mode, i.e. static parameter
Test pattern；When TM1 pin and the equal input high level of TM2 pin, and when TM3 pin input low level, indicate that opening dynamic joins
Number computational submodule independent startup mode, i.e. dynamic parametric test mode；When TM1 pin and the equal input low level of TM2 pin, and
When TM3 pin input high level, indicate to open fault detection module and the equal start-up mode of static parameter computational submodule, i.e. failure
Detection and static parameter test mode；When TM1 pin and the equal input high level of TM3 pin, and when TM2 pin input low level,
It indicates to open fault detection module and the equal start-up mode of dynamic parameter computational submodule, i.e. fault detection and dynamic parametric test mould
Formula；When TM1 pin input low level, and when TM2 pin and the equal input high level of TM3 pin, indicate that opening static parameter calculates
Submodule and the equal start-up mode of dynamic parameter computational submodule, i.e. starting static parameter and dynamic parametric test mode；When TM1 draws
When foot, TM2 pin and the equal input high level of TM3 pin, indicate to open fault detection module, static parameter computational submodule and dynamic
The equal start-up mode of state parameter computation module, i.e. hybrid test mode.
When starting hybrid test mode, the implementation process tested to analog/mixed signal circuit can be with are as follows:
Step 1: test control circuit 11 indicates that test patterns generation circuit 12 generates test waveform, and indicates that test is rung
Circuit 13 should be analyzed and be ready for response analysis.Test response analysis circuit receives digital code (if mixed signal circuit is mould
Number conversion circuit, then the digital code is directly exported by mixed signal circuit, is digital-to-analogue if analog circuit or mixed signal circuit
Conversion circuit, then the digital code carries out modulus turn by signal of the analog to digital conversion circuit to analog circuit or mixed signal circuit data
Change output) after, fault detection is carried out, if testing result is " passing through ", thens follow the steps two；If testing result is " not passing through ",
Then follow the steps four；
Step 2: test control circuit 11 indicates that test patterns generation circuit 12 generates triangular signal, and indicates to test
Response analysis circuit 13 carries out response analysis, and test response analysis circuit 13 is receiving digital code (if mixed signal circuit is
Analog to digital conversion circuit, then the digital code is directly exported by mixed signal circuit, is number if analog circuit or mixed signal circuit
Analog conversion circuit, then the digital code carries out modulus by signal of the analog to digital conversion circuit to analog circuit or mixed signal circuit data
Conversion output) after, static parameter test is carried out, static parameter test result is exported after test and returns to end signal to survey
Control circuit 11 is tried, and executes step 3；
Step 3: test control circuit 11 indicates that test patterns generation circuit 12 generates sine wave signal, and indicates to test
Response analysis circuit 13 carries out response analysis, and test response analysis circuit 13 is receiving digital code (if mixed signal circuit is
Analog to digital conversion circuit, then the digital code is directly exported by mixed signal circuit, is number if analog circuit or mixed signal circuit
Analog conversion circuit, then the digital code carries out modulus by signal of the analog to digital conversion circuit to analog circuit or mixed signal circuit data
Conversion output) after, dynamic parametric test is carried out, dynamic parametric test result is exported after test and returns to end signal to survey
Try control circuit.
Step 4: output test result.
By build in self test apparatus provided by the embodiments of the present application, Test Engineer can according to need 3 kinds of selection (such as
Shown in table 1) or 7 kinds of (as shown in table 2) test patterns, under different test patterns, the control of testing and control control circuit 11 is surveyed
Module corresponding with selected test pattern and/or submodule work in response analysis circuit are tried, and other is not involved in test
Module and/or submodule be then in close state, the power consumption of build in self test apparatus can be reduced in this way.
In above-described embodiment, controlled for the ease of the switch state to build in self test apparatus, can also increase open/
Close control pin.It when pin input meets the signal of preset condition, determines and opens build in self test apparatus, for example, when should
When pin inputs rising edge signal (first input low level signal again input high level signal), build in self test apparatus is opened.
Specifically, build in self test apparatus provided by the embodiments of the present application can be used for modulus in mixed signal system on chip
Convert the built-in self-test of (A/DC) IP kernel or the built-in self-test of digital-to-analogue conversion (D/AC) IP kernel.
In above-described embodiment, optionally, if the system on chip has mixed signal circuit, and mixed signal electricity
Road is analog to digital conversion circuit, then the test patterns generation circuit 12 passes through D/A converting circuit and the mixed signal circuit phase
Connection.
The test waveform that test patterns generation circuit 12 generates is converted to analog stimulus by D/A converting circuit, therefore, is surveyed
Attempt shape generative circuit 12 and D/A converting circuit cooperation is used for the generation of on piece analog stimulus.In the embodiment of the present application, digital-to-analogue
The precision of conversion circuit is at least 2bit higher than the precision of analog to digital conversion circuit.
In above-described embodiment, optionally, if the system on chip has mixed signal circuit, and mixed signal electricity
Road is D/A converting circuit, then the test response analysis circuit is connected by analog to digital conversion circuit with the mixed signal circuit
It connects.
The simulation output of the D/A converting circuit is converted to digital code by analog to digital conversion circuit, therefore, test response point
Circuit 13 and analog to digital conversion circuit cooperation are analysed for testing response analysis.In the embodiment of the present application, the precision of analog to digital conversion circuit
It is at least 2bit higher than the precision of D/A converting circuit.
In above-described embodiment, optionally, a kind of structural schematic diagram of the fault detection module 131 is as shown in Fig. 2, can be with
Include:
Difference channel 21, accumulator 22 and decision device 23；Wherein,
Difference channel 21 is used to the signal of the resolution chart of the test patterns generation circuit evolving mixing letter with described
The signal that number circuit responds the resolution chart output does difference operation；
In the embodiment of the present application, test patterns generation circuit and test response analysis circuit are digital signal processing circuit.
Accumulator 22 is used to do accumulating operation to the absolute value of the result of difference operation；
Decision device 23 is used to judge whether the mixed signal circuit breaks down according to accumulating operation result.
Specifically, decision device 23 may determine that accumulating operation result whether in default range, if it is, explanation is mixed
Closing signal circuit does not have failure, otherwise illustrates that the circuit of mixed signal breaks down.Wherein, the preset range refers in member
Under the influence of device parameters, voltage, the variation of temperature and noise, mixed signal circuit can be to the area that test waveform correctly responds
Between.
In above-described embodiment, it is preferred that the parameter calculating module includes static parameter submodule, static parameter
A kind of structural schematic diagram of module is as shown in figure 3, may include:
Counter 31 and first arithmetic device 32；Wherein,
Counter 31 is used to count the number that each digital code of the signal of the mixed signal circuit output occurs；
The number that each digital code occurs can store into memory.
The number that each digital code for the signal that first arithmetic device 32 is used to export according to the mixed signal circuit occurs
Static parameter is calculated.
Wherein, static parameter may include: that offset error, gain error, integral non-linear error and differential nonlinearity miss
Difference；Specifically, the calculation method of each static parameter can be with are as follows:
Wherein,
H (i) indicates the number that i-th digital code occurs；The precision of N expression analog to digital conversion circuit；DNL (i) is indicated i-th
The differential nonlinearity error of digital code；The integral non-linear error of INL (i) expression i-th digital code；VoffsetIndicate that imbalance misses
Difference；Gain indicates gain error；N1=1, N2=2N-2；HidealFor the number that ideally each digital code occurs, with slope
Motivate the slope slope, the sensitivity LSB of mixed signal circuit, sampling rate f of (or triangle wave excitation)sAnd period slope
Durations number X it is related, specific formula for calculation are as follows:
Slope=2 × FSRtri×ftri, wherein
FSR is the range of D/A converter module or analog-to-digital conversion module；FSRtriFor the range of slope (or triangular wave)；ftri
For the frequency of period slope (or triangular wave).
In above-described embodiment, it is preferred that the parameter calculating module includes dynamic parameter submodule, dynamic parameter
A kind of structural schematic diagram of module is as shown in figure 4, may include:
Converter 41 and the second computing module 42；Wherein,
The signal that converter 41 is used to export the mixed signal circuit carries out Fast Fourier Transform (FFT), obtains described mixed
Close the frequency spectrum of the signal of signal circuit output；
Dynamic is calculated in the frequency spectrum for the signal that second computing module 42 is used to export according to the mixed signal circuit
Parameter.
Wherein, dynamic parameter may include: signal-to-noise ratio, spurious-free dynamic range, total harmonic distortion ratio, signal noise distortion
Than and number of significant digit；Specifically, the calculation method of each dynamic parameter can be with are as follows:
The frequency spectrum of signal according to mixed signal circuit output calculates the signal of the mixed signal circuit output
Total power, the signal power of the signal of mixed signal circuit output and the letter of mixed signal circuit output
Number each harmonic power；
Noise power is obtained by general power subtraction signal power and harmonic power；
Specifically, a certain number of output sampled points are acquired under sinusoidal excitation, this when needing to calculate dynamic parameter
A little points obtain the frequency spectrum of output signal, the frequency by Fast Fourier Transform (FFT) (Fast Fourier Transform, FFT)
Spectrum has recorded from fundamental frequency to fs/2 frequency range, the size of (span) signal amplitude in each frequency band, it is assumed that FFT, which counts, is
8192, span quantity are 4096, and the signal amplitude of each span is D (span_i), then:
General power: Ptotal=sum ((D (span_1)2:(D(span_4096)2)；
Signal power: finding span_signal at the Amplitude maxima other than fundamental frequency span_1, model nearby+- 5
It encloses for signal power, Psignal=sum (D (span_signal-5)2:(D(span_signal+5)2)；
Harmonic power: referring to the sum of each harmonic power, and the frequency of each harmonic is equal to the integral multiple of signal frequency, therefore 2
The position of subharmonic is about near 2*span_signal, near 3 subharmonic 3*span_signal.Due to nyquist sampling
The constraint of theorem, frequency are more than the span of fs/2, and by the section of Conjugate Mapping to 1~fs/2, there are two types of situations in total: 1 such as
Fruit harmonic wave span_h, which is greater than 4096, can be mapped to the position (8192-span_h) less than 8192, span_h, if 2 span_h are greater than
8192 can be mapped to the position (span_h-8192) less than 12288, span_h.And so on.If harmonic frequency has with fundamental frequency
If overlapping, then the subharmonic power is imponderable.After obtaining the position harmonic wave span, calculation method and signal power are calculated
Method is similar.
Specifically, the calculation method of each dynamic parameter can be with are as follows:
SNR=10lg (Psignal/Pnoise) (5)
SFDR=10lg (Psignal/Pharmonic-max) (6)
THD=10lg (Pharmonic/Psignal) (8)
ENOB=(SNDR-1.76)/6.02 (9)
Wherein, SNR indicates signal-to-noise ratio；PsignalIndicate signal power；PnoiseIndicate noise power；SFDR is indicated without spuious
Dynamic range；SNDR indicates that signal noise is distorted ratio；THD indicates total harmonic distortion ratio；ENOB indicates number of significant digit；
Pharmonic-maxFor the power of harmonic wave at amplitude maximum one；PharmonicFor total harmonic power.
In traditional A/DC test, be all selection using based on ATE (Automatic Test Equipment, automatically
Test machine) or simulation test equipment to A/DC test chip carry out the parameter testing based on function.In system on chip, A/DC makees
For an IP kernel, there are signal it is uncontrollable and not observable the problems such as, traditional build-in self-test method based on function uses
Analog circuit generates analog stimulus, analyzes A/DC using digital signal processor (Digtal Signal Processor, DSP)
Response, whether there is dependent on DSP.Analog mixed-signal circuit BIST structure of the typical case based on failure, additional design is more, and
And it not can be carried out the test based on function.
BIST structure proposed by the invention, can be very good to solve the above problems.
On-chip testing graphic hotsopt circuit and test response analysis circuit can solve that signal is uncontrollable and not observable
Problem, reduce analog mixed-signal circuit (including analog to digital conversion circuit and D/A converting circuit) test to test equipment according to
Rely, reduces testing cost.
Not only the test based on failure can be completed, but also the test based on function can be completed.
Test pattern can be with flexible choice, can be raw for the batch of mixed signal system on chip (SoC as included A/DC)
It produces and yield test Solution is provided, when only needing to judge mixed signal circuit with the presence or absence of failure, surveyed using fault detection
Die trial formula can save the testing time.
In addition to mixed signal circuit, the VHDL or Verilog of other module available parameters of BIST circuit are described, and are had
Conducive to fast, easily synthesis and synthesis, be conducive to carry out design for Measurability to BIST circuit, and advantageously form reusable
BIST IP kernel may be used on arbitrary mixed signal system on chip, be also applied to the analog/mixed signal system based on FPGA
System.
In above-described embodiment, optionally, if the system on chip has analog circuit, test patterns generation circuit 12
It is connected by D/A converting circuit with the analog circuit；It tests response analysis circuit 13 and then passes through analog to digital conversion circuit and institute
Analog circuit is stated to be connected.
In above-described embodiment, it is preferred that build in self test apparatus provided by the embodiments of the present application can also be arranged reset and draw
Foot is zeroed out test response analysis circuit for receiving reset signal.
The embodiment of the present application also provides a kind of system on chip, which has the interior of as above any one embodiment offer
Build self-test device.
Corresponding with Installation practice, the embodiment of the present application also provides a kind of build-in self-test method, the embodiment of the present application
The build-in self-test method of offer is applied to system on chip, and the system on chip has analog/mixed signal circuit, the on piece
System is also integrated with: the test control circuit being connected with the analog/mixed signal circuit；With the test control circuit phase
The test patterns generation circuit and test response analysis circuit of connection；The storage being connected with the test response analysis circuit
Device；The test patterns generation circuit and the test response analysis circuit also respectively with the analog/mixed signal circuit phase
Connection；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；The embodiment of the present application provides
Build-in self-test method a kind of implementation flow chart as shown in figure 5, may include:
Step S51: test control circuit has monitored whether test mode signal input；
Step S52: when monitoring test mode signal input, test control circuit indicates the test patterns generation electricity
Road generates resolution chart corresponding with the test pattern, and indicates that the test response analysis circuit switches to and the survey
The corresponding operating mode of die trial formula；
The operating mode of the test response analysis circuit includes: fault detection module independence open mode, and parameter calculates
Module independence open mode, alternatively, fault detection module and the equal open mode of parameter calculating module；
When the fault detection module is in running order, according to the analog/mixed signal circuit to the test chart
The response message for the resolution chart that shape generative circuit generates judges the analog/mixed signal circuit with the presence or absence of failure, i.e. event
When barrier detection module is in running order, the test based on failure may be implemented；
When the parameter calculating module is in running order, according to the analog/mixed signal circuit to the test chart
The response message for the resolution chart that shape generative circuit generates calculates parameter corresponding with the analog/mixed signal circuit, institute
Stating parameter includes static parameter and/or dynamic parameter, i.e., when parameter calculating module is in running order, may be implemented based on function
Test.
Test patterns generation circuit 12 can use the test patterns generation circuit of linear feedback shift register structure, survey
Attempting shape generative circuit 12 can be generated a variety of test waveforms, including pseudorandom wave, slope wave, sawtooth wave, triangular wave, ladder
The sine wave of wave, square wave and certain frequency.
Wherein, a kind of resolution chart may be corresponded under each test pattern, it is also possible to two or more corresponding tests
Figure.When two or more corresponding resolution charts, described two or more test charts can be determined according to testing requirement
It the genesis sequence of shape and the generation opportunity of resolution chart, is given birth to during the test according to the genesis sequence of resolution chart accordingly
Resolution chart is generated at opportunity to export to analog/mixed signal circuit.
A kind of build-in self-test method provided by the embodiments of the present application, is applied to system on chip, and system on chip has mould
Quasi-/mixed signal circuit, described device include: test control circuit, test patterns generation circuit, test response analysis circuit and
Memory；Wherein, the test response analysis circuit includes fault detection module and parameter calculating module；Test control circuit prison
When measuring test mode signal, test patterns generation circuit evolving test chart corresponding with the test pattern is controlled
Shape, and control the test response analysis circuit and switch to operating mode corresponding with the test pattern, the test is rung
The operating mode that circuit should be analyzed includes: fault detection module independent startup mode, parameter calculating module independent startup mode, or
Person, fault detection module and the equal start-up mode of parameter calculating module；The fault detection module is for judging the analog/hybrid
Signal circuit whether there is failure；The parameter calculating module is corresponding with the analog/mixed signal circuit for calculating
Parameter, the parameter include static parameter and/or dynamic parameter.
To sum up, pass through build-in self-test method provided by the embodiments of the present application, the corresponding test of different test mode signals
The different working modes of response analysis circuit to not only can only carry out the test based on failure, but also can only carry out being based on function
The test of energy realizes alternatively, the test based on failure and the mixing of the test based on function carry out to analog/mixed signal electricity
The multimode on road is tested.
In above-described embodiment, it is preferred that if the system on chip has mixed signal circuit, and mixed signal electricity
Road is analog to digital conversion circuit or D/A converting circuit, then it is described according to the mixed signal circuit to test patterns generation electricity
The response message for the resolution chart that road generates judges that the mixed signal circuit whether there is a kind of implementation flow chart of failure such as
Shown in Fig. 6, may include:
Step S61: the resolution chart signal of the test patterns generation circuit evolving and the mixed signal circuit are rung
The signal of the resolution chart output is answered to do difference operation；
Step S62: accumulating operation is done to the absolute value of the result of difference operation；
Step S63: judge whether the mixed signal circuit breaks down according to accumulating operation result.
Specifically, may determine that accumulating operation result whether in default range, if it is, illustrating mixed signal electricity
Road does not have failure, otherwise illustrates that the circuit of mixed signal breaks down.Wherein, the preset range refers to joins in component
Under the influence of number, voltage, the variation of temperature and noise, mixed signal circuit can be to the section that test waveform correctly responds.
In above-described embodiment, it is preferred that if the system on chip has mixed signal circuit, and mixed signal electricity
Road be analog to digital conversion circuit or D/A converting circuit, then when the parameter be static parameter when, it is described according to the mixed signal
Circuit calculates opposite with the mixed signal circuit response message of the resolution chart of the test patterns generation circuit evolving
A kind of implementation flow chart for the parameter answered is as shown in fig. 7, may include:
Step S71: the number that each digital code of the signal of the mixed signal circuit output occurs is counted；
The number that each digital code occurs can store into memory.
Step S72: the number that each digital code of the signal according to mixed signal circuit output occurs is calculated
Static parameter.
Wherein, static parameter may include: that offset error, gain error, integral non-linear error and differential nonlinearity miss
Difference；Specifically, the calculation method of each static parameter may refer to embodiment illustrated in fig. 3, which is not described herein again.
In above-described embodiment, it is preferred that if the system on chip has mixed signal circuit, and mixed signal electricity
Road be analog to digital conversion circuit or D/A converting circuit, then when the parameter be dynamic parameter when, it is described according to the mixed signal
Circuit calculates opposite with the mixed signal circuit response message of the resolution chart of the test patterns generation circuit evolving
Another implementation flow chart for the parameter answered is as shown in figure 8, may include:
Step S81: carrying out Fast Fourier Transform (FFT) to the signal of mixed signal circuit output, obtains the mixing letter
The frequency spectrum of the signal of number circuit output；
Step S82: dynamic parameter is calculated in the frequency spectrum of the signal according to mixed signal circuit output.
Wherein, dynamic parameter may include: signal-to-noise ratio, spurious-free dynamic range, total harmonic distortion ratio, signal noise distortion
Than and number of significant digit；Specifically, the calculation method of each dynamic parameter may refer to embodiment illustrated in fig. 4, it is no longer superfluous here
It states.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (14)
1. a kind of build in self test apparatus is applied to system on chip, the system on chip has analog/mixed signal circuit,
It is characterized in that, described device includes: the test control circuit being connected with the analog/mixed signal circuit；With the survey
The test patterns generation circuit and test response analysis circuit that examination control circuit is connected；With the test response analysis circuit phase
The memory of connection；The test patterns generation circuit and the test response analysis circuit also respectively with the analog/hybrid
Signal circuit is connected；Wherein,
The test response analysis circuit includes fault detection module and parameter calculating module；
The test control circuit is used to monitor whether test mode signal generation by test pin, is monitoring to test mould
When formula signal, test patterns generation circuit evolving resolution chart corresponding with the test pattern is indicated, and indicate institute
It states test response analysis circuit and switches to operating mode corresponding with the test pattern, the test response analysis circuit
Operating mode includes: fault detection module independent startup mode, parameter calculating module independent startup mode, alternatively, fault detection
Module and the equal start-up mode of parameter calculating module；
The fault detection module is used for according to the analog/mixed signal circuit to the test patterns generation circuit evolving
The response message of resolution chart judges the analog/mixed signal circuit with the presence or absence of failure；
The parameter calculating module is used for according to the analog/mixed signal circuit to the test patterns generation circuit evolving
The response message of resolution chart, calculates parameter corresponding with the analog/mixed signal circuit, and the parameter includes static ginseng
Several and/or dynamic parameter.
2. the apparatus according to claim 1, which is characterized in that the parameter calculating module includes:
Static parameter computational submodule and/or dynamic parameter computational submodule.
3. the apparatus of claim 2, which is characterized in that when the parameter calculating module includes that static parameter calculates son
When module and dynamic parameter computational submodule, the operating mode of the parameter calculating module includes:
Static parameter computational submodule independent startup mode, dynamic parameter computational submodule independent startup mode, alternatively, static ginseng
Number computational submodule and the equal start-up mode of dynamic parameter computational submodule.
4. the apparatus according to claim 1, which is characterized in that if the system on chip has mixed signal circuit, and
The mixed signal circuit is analog to digital conversion circuit, then the test patterns generation circuit is mixed by D/A converting circuit with described
Signal circuit is closed to be connected.
5. the apparatus according to claim 1, which is characterized in that if the system on chip has mixed signal circuit, and
The mixed signal circuit is D/A converting circuit, then the test response analysis circuit is mixed by analog to digital conversion circuit with described
Signal circuit is closed to be connected.
6. device according to claim 4 or 5, which is characterized in that the fault detection module includes:
Difference channel, for ringing the resolution chart signal of the test patterns generation circuit evolving and the mixed signal circuit
The signal of the resolution chart output is answered to do difference operation；
Accumulator, the absolute value for the result to difference operation do accumulating operation；
Decision device judges whether the mixed signal circuit breaks down according to accumulating operation result.
7. device according to claim 4 or 5, which is characterized in that the parameter calculating module includes static parameter submodule
Block, the static parameter submodule include:
Counter, the number occurred for counting each digital code of signal of the mixed signal circuit output；
First arithmetic device, the number that each digital code of the signal for exporting according to the mixed signal circuit occurs calculate
To static parameter.
8. device according to claim 4 or 5, which is characterized in that the parameter calculating module includes dynamic parameter submodule
Block, the dynamic parameter submodule include:
Converter, the signal for exporting to the mixed signal circuit carry out Fast Fourier Transform (FFT), obtain the mixing letter
The frequency spectrum of the signal of number circuit output；
Dynamic parameter is calculated in the frequency spectrum of second computing module, the signal for exporting according to the mixed signal circuit.
9. the apparatus according to claim 1, which is characterized in that described if the system on chip has analog circuit
Test patterns generation circuit is connected by D/A converting circuit with the analog circuit, and the test response analysis circuit passes through
Analog to digital conversion circuit is connected with the analog circuit.
10. a kind of system on chip, which is characterized in that including build in self test apparatus as described in any one of claims 1-9.
11. a kind of build-in self-test method is applied to system on chip, the system on chip has analog/mixed signal circuit,
It is characterized in that, the system on chip further include: the test control circuit being connected with the analog/mixed signal circuit；With
The test patterns generation circuit and test response analysis circuit that the test control circuit is connected；With the test response analysis
The memory that circuit is connected；The test patterns generation circuit and the test response analysis circuit also respectively with the mould
Quasi-/mixed signal circuit is connected；Wherein, the test response analysis circuit includes that fault detection module and parameter calculate mould
Block；The described method includes:
The test control circuit has monitored whether test mode signal generation by test pin, monitors test mode signal
When input, test patterns generation circuit evolving resolution chart corresponding with the test pattern is indicated, and described in instruction
Test response analysis circuit switches to operating mode corresponding with the test pattern, the work of the test response analysis circuit
Operation mode includes: fault detection module independent startup mode, parameter calculating module independent startup mode, alternatively, fault detection mould
Block and the equal start-up mode of parameter calculating module；
It is raw to the resolution chart according to the analog/mixed signal circuit when fault detection module is in running order
At the response message of the resolution chart of circuit evolving, judge the analog/mixed signal circuit with the presence or absence of failure；
It is raw to the resolution chart according to the analog/mixed signal circuit when parameter calculating module is in running order
At the response message of the resolution chart of circuit evolving, parameter corresponding with the analog/mixed signal circuit, the ginseng are calculated
Number includes static parameter and/or dynamic parameter.
12. according to the method for claim 11, which is characterized in that if the system on chip has mixed signal circuit,
And the mixed signal circuit is analog to digital conversion circuit or D/A converting circuit, then according to the mixed signal circuit to the survey
The response message for attempting the resolution chart of shape generative circuit generation, judges that the mixed signal circuit includes: with the presence or absence of failure
The resolution chart signal of the test patterns generation circuit evolving and the mixed signal circuit are responded into the test chart
The signal of shape output does difference operation；
Accumulating operation is done to the absolute value of the result of difference operation；
Judge whether the mixed signal circuit breaks down according to accumulating operation result.
13. according to the method for claim 11, which is characterized in that if the system on chip has mixed signal circuit,
And the mixed signal circuit is analog to digital conversion circuit or D/A converting circuit, then when the parameter is static parameter, foundation
The mixed signal circuit is calculated and is mixed with described to the response message of the resolution chart of the test patterns generation circuit evolving
The corresponding parameter of signal circuit includes:
Count the number that each digital code of the signal of the mixed signal circuit output occurs；
Static parameter is calculated in the number that each digital code of signal according to mixed signal circuit output occurs.
14. according to the method for claim 11, which is characterized in that if the system on chip has mixed signal circuit,
And the mixed signal circuit is analog to digital conversion circuit or D/A converting circuit, then when the parameter is dynamic parameter, foundation
The mixed signal circuit is calculated and is mixed with described to the response message of the resolution chart of the test patterns generation circuit evolving
The corresponding parameter of signal circuit includes:
Fast Fourier Transform (FFT) is carried out to the signal of mixed signal circuit output, obtains the mixed signal circuit output
The frequency spectrum of signal；
Dynamic parameter is calculated in the frequency spectrum of signal according to mixed signal circuit output.
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| CN106685423A (en) * | 2016-11-18 | 2017-05-17 | 上海精密计量测试研究所 | Method for testing static parameters of analog-digital converters by aid of sinusoidal waves |
| JP6920836B2 (en) * | 2017-03-14 | 2021-08-18 | エイブリック株式会社 | Semiconductor device |
| US10425068B1 (en) * | 2018-06-14 | 2019-09-24 | Nxp B.V. | Self-testing of an analog mixed-signal circuit using pseudo-random noise |
| CN111913097B (en) * | 2020-08-26 | 2022-11-29 | 西安微电子技术研究所 | Test circuit and test method for testing SoC function and SoC |
| CN111766509B (en) * | 2020-09-02 | 2020-12-25 | 深圳芯邦科技股份有限公司 | Chip testing method and related equipment |
| CN112130651B (en) * | 2020-10-28 | 2022-06-07 | 北京百瑞互联技术有限公司 | Reset method and device of SOC (System on chip) system and storage medium thereof |
| CN115078968A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Chip test circuit, self-test chip and chip test system |
| CN115694502A (en) * | 2023-01-03 | 2023-02-03 | 成都爱旗科技有限公司 | Data processing method and device and electronic equipment |
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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