CN103185859A - In-chip mixed testing device and in-chip mixed testing method - Google Patents
In-chip mixed testing device and in-chip mixed testing method Download PDFInfo
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- CN103185859A CN103185859A CN2011104446056A CN201110444605A CN103185859A CN 103185859 A CN103185859 A CN 103185859A CN 2011104446056 A CN2011104446056 A CN 2011104446056A CN 201110444605 A CN201110444605 A CN 201110444605A CN 103185859 A CN103185859 A CN 103185859A
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Abstract
The invention provides an in-chip mixed testing device and an in-chip mixed testing method. Control on different testing flows is accomplished by arranging a programmable engine in a circuit system of a chip, uniformly specifying the testing flows of to-be-tested circuits as operations such as read-write and relevant computation and judgment for different registers, testing an instruction of a control engine corresponding to each step, and writing different instruction sequences. According to the device and the method, the testing engine can be controlled by writing programs according to different requirements, so that testing and verification of a circuit parameter can be accomplished more comprehensively and efficiently.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) design technology, particularly a kind of designing technique of chip built-in test.
Background technology
When existing simulation or digital-analog mixed type chip design, tend to reserve some adjustable parameters, particularly in Design of Simulating Circuits, reason is following points at least:
(1) technological factor: the discreteness of manufacturing process causes the parameter of side circuit (as resistance value, capacitance etc.) inconsistent with the designing requirement value, so need when design, do a plurality of adjustable parameters, after chip manufacturing finishes, by testing the error of proofreading and correct actual parameter.
(2) environmental factor: because the difference of chip environment for use (as temperature, humidity, pressure, supply voltage etc.) causes actual parameter value and design load that deviation is arranged, need be according to these parameter values of environmental correction of reality use.
(3) encapsulation factor: factors such as the encapsulation of chip, binding line also can influence the parameter (as inductance) of circuit, need be after encapsulation finish, proofread and correct by testing.
(4) design factor: some parameter can't be determined its exact value when design, can only judge it in a scope, so design the time leaves a plurality of possible selections, when using according to actual conditions, by testing which selects to use select (as emissive power, receiving sensitivity etc.).
After chip manufacturing finishes, according to different application, select one or more suitable parameters by test.
This mode will be brought some difficulty to the test job of chip, and the complicacy of test job shows:
(1) combinatory possibility of various parameters is big, and the test job amount is big, the testing cost height.
(2) change that needs of partial parameters has sequential to require (revising once certain parameter as each 10us), and the real-time of test is required than higher.
Therefore the testing cost of chip becomes a kind of very important cost factor, and it is very significant seeking a kind of method of testing efficiently.
Application number is: the Chinese patent application of CN01816231.2 discloses a kind of built-in testing method of analog filter circuit.Its way will be done with measurand at test circuit, the chip imput output circuit of measurand and be in the same place.Adopt this mode, need be by external means, perhaps the least possible by external means, the simple cutoff frequency of test filter has just improved the testing efficiency of mimic channel, has reduced testing cost.
For the simulation/radio circuit design proposal of existing no built-in testing auxiliary circuit, after chip manufacturing finishes, by external unit control parameter and the correlated performance of mimic channel are tested; This method need be reserved the interface that external unit can be visited mimic channel, and testing efficiency is lower, and testing cost is higher.
For the simulation/radio circuit design proposal of existing built-in complete test circuit, when design, just at each parameter designing one cover test circuit of circuit, circuit-under-test and test are bound together.This scheme can improve the testing efficiency of concrete certain parameter, but because test circuit solidifies, does not possess dirigibility, and the test circuit of different circuit can not be multiplexing, so can increase the cost of design greatly.The test circuit that this mode is solidified can not be changed, in case testing scheme changes, then whole test circuit might complete failure.
Summary of the invention
The technical matters that the present invention solves is to have proposed a kind of interior hybrid test apparatus and method, different test control engine datas can be provided according to different testing requirements, by in sheet, carrying out test control engine data, test and checking to the circuit under test correlation parameter have been realized finishing more comprehensively, more efficiently during test.
Hybrid test device in the sheet that the present invention proposes comprises: be arranged on circuit under test unit, control register unit, status register unit and unit of testing and controlling in the chip; Described control register unit is connected between the control signal input port and described unit of testing and controlling test signal transmitting terminal of described circuit under test unit; Described status register unit is connected between the status signal delivery outlet and described unit of testing and controlling test signal receiving end of described circuit under test unit; Described unit of testing and controlling is used for carrying out the processing procedure of test control engine data, and by the value of changing in the described control register unit described circuit under test unit is sent the test steering order, and read the status information that value in the described mode control register unit is obtained described circuit under test unit.
Further, described circuit under test unit comprises a plurality of circuit under test modules, and described control register unit comprises a plurality of control register groups, and described status register unit comprises a plurality of status register groups; A described circuit under test module connects a described control register group and at least one described status register group.
Further, described unit of testing and controlling comprises: test control engine modules and engine memory module; Described engine memory module is used for the described test control of storage engine data; Described test control engine modules is finished test control by the test control engine data that calls described engine memory module.
Further, the hybrid test device also comprises the engine loading interface that links to each other with described engine memory module in the sheet, is used for loading test control engine data to described engine memory module.
Further, described engine memory module is: trigger memory module, register-stored module, random access storage device, ROM (read-only memory) and nonvolatile memory terminal any one.
Further, the hybrid test device also comprises the universal input/output interface that links to each other with described test control engine modules in the sheet, is used for realizing the information interaction of described test control engine modules and sheet external equipment.
Further, arbitrary described circuit under test module be in mimic channel and the digital circuit any one.
Mixed test method in the sheet that the present invention also proposes comprises following processing procedure: unit of testing and controlling is carried out the processing of test control engine data; Unit of testing and controlling is carried out the processing of following steps at least one times to control register unit and status register unit in test process: unit of testing and controlling writes the test steering order to the control register unit, and the control register unit sends to the circuit under test unit with described test steering order; The circuit test setting is finished according to the information of test steering order in the circuit under test unit, and with status information write state register cell, the status information in the unit of testing and controlling read status register unit.
Further, before carrying out the processing of testing the control engine data, described unit of testing and controlling also comprises following processing procedure: call test control engine data from the engine memory module.
Further, also comprise following processing procedure after described unit of testing and controlling is carried out the processing of test control engine data: unit of testing and controlling exports outside sheet by universal input/output interface that detecting information or unit of testing and controlling send control information by universal input/output interface testing apparatus outside sheet or unit of testing and controlling is passed through input signal outside the universal input/output interface receiving sheet.
Further, before or after described test process, also comprise following processing procedure: unit of testing and controlling is carried out the processing of function control data; Unit of testing and controlling is carried out the processing of following steps at least one times to control register unit and status register unit in the function control procedure: unit of testing and controlling is to control register unit write-in functions steering order, and the control register unit sends to the circuit under test unit with described function steering order; The circuit test setting is finished according to the information of test steering order in the circuit under test unit, and with status information write state register cell, the status information in the unit of testing and controlling read status register unit.
Adopt of the present invention interior hybrid test apparatus and method, have the following advantages:
1, inner module testing control flow is realized robotization, compare with the method for testing by external unit control, improved testing efficiency.
2, based on the method for built-in testing control engine, test macro and concrete circuit under test are independent of one another, and test macro can be by a plurality of module reuses in a plurality of digital-to-analogue commingled systems, the same system; The test macro utilization factor improves.
3, adopt programmable control flow, the test control flow can be updated flexibly, makes test more flexible; Testing scheme can be formulated according to actual conditions after the chip production manufacturing finishes.
4, can use built-in testing control engine to control outside test relevant device, realize full automatic test.
Description of drawings
Fig. 1 is the schematic diagram of the interior hybrid test device of sheet of the embodiment of the invention one;
Fig. 2 is the structural representation of the interior hybrid test device of sheet of the embodiment of the invention two.
Embodiment
Below in conjunction with accompanying drawing, and by specific embodiment realization of the present invention is elaborated.
Main inventive concept of the present invention be by a built-in programmable engine in the Circuits System of chip, and control testing engine according to different demand codings, to realize finishing more comprehensively, more efficiently test and the checking to circuit parameter.
Embodiment one
Hybrid test device in the sheet as shown in Figure 1 comprises being arranged in the sheet: circuit under test unit 104, control register unit 102, status register unit 103 and unit of testing and controlling 101.Wherein relevant control signal input port and status signal delivery outlet reserved in circuit under test unit 104.Control register unit 102 is connected with the control signal of circuit under test unit 104 is corresponding with status signal with status register unit 103.Unit of testing and controlling 101 realizes the test of circuit under test unit 104 is controlled by the value of change control register unit 102 during test.Unit of testing and controlling 101 is judged the state of circuit under test unit 104 by the value of read status register unit 103 during test.Will be to the testing process of circuit under test unit 104, carry out the processing of test control engine datas by unit of testing and controlling 101, and standard is unified in test action be the read-write operation to different registers.
Introduce in detail the sheet build-in test process that the proving installation based on Fig. 1 carries out below again.
Basic test process comprises following treatment step:
(1) unit of testing and controlling 101 is carried out the processing of test control engine data;
(2) 101 pairs of control register unit 102 of unit of testing and controlling and status register unit 103 carry out handling below the one or many in test process:
Unit of testing and controlling 101 writes the test steering order to control register unit 102, and control register unit 102 sends to circuit under test unit 104 with described test steering order;
The circuit test setting is finished according to the information of test steering order in circuit under test unit 104, and with status information write state register cell 103, the status information in the unit of testing and controlling 101 read status register unit 104.
For the situation of prior offhand test control engine data in the unit of testing and controlling 101, can before carrying out the processing of testing the control engine data, unit of testing and controlling 101 carry out following processing: call test control engine data from the engine memory module.
Need carry out the situation that data interaction is handled with the outside for unit of testing and controlling 101, also comprise following processing procedure after unit of testing and controlling 101 is carried out the processing of test control engine datas: unit of testing and controlling 101 exports outside sheet by universal input/output interface that detecting information or unit of testing and controlling 101 send control information by universal input/output interface testing apparatus outside sheet or unit of testing and controlling 101 is passed through input signal outside the universal input/output interface receiving sheet.
Based on above-mentioned test philosophy, if in unit of testing and controlling 101, carry out the processing of function control data, then can realize the correlation function of chip.Its processing procedure is identical with above-mentioned basic test process, all be the processing of in unit of testing and controlling 101, carrying out earlier data, and then by unit of testing and controlling 101 and control register unit 102, status register unit 103 at least one times interaction data realize specific business function.The processing procedure that this function realizes can be independent of above-mentioned test process, for example: before or after the basic test process.
Embodiment two
Be illustrated in figure 2 as hybrid test device in the sheet under many circuit under test situation.The circuit under test unit comprises n+1 circuit under test module among the figure.Comprise a plurality of control register groups and a plurality of status register group in control register unit and the status register unit 203.The corresponded manner of each register group and circuit under test module can be a corresponding control register group of circuit under test module and a status register group, the perhaps corresponding a plurality of control register groups of circuit under test module and a plurality of status register groups etc.It is test control engine program that test control engine data is saved, by the execution of executive routine realization to test control engine data.
In one embodiment, unit of testing and controlling comprises test control engine modules 201 and engine memory module 202.Engine memory module 202 is used for the described test control of storage engine program, can form for a plurality of triggers, it also can be register file, can also be various types of random access storage devices (RAM), or ROM (read-only memory) (ROM), various forms of nonvolatile memories (NVM), and any device that can store Digital Logic.Test control engine modules 201 is finished test control by the test control engine program that calls described engine memory module.Corresponding register group is carried out read-write operation in 201 pairs of register cells 203 of test control engine modules, finishes the control of the testing process of each circuit under test module and the judgement of correlated results.Different test control engine programs is provided in the engine memory module 202, can finishes different test control flows, test control engine modules is finished test process by the test control engine program that calls and carry out in the engine memory module 202.The behavioral test of test control engine modules 201 comprises: write certain address register, read certain address register, judge certain address register some or the value of certain several bit, certain address that jumps to test control program, arithmetical operation, logical operation, shift operation, pop down and bullet stack, subroutine call and return, delay time wait, dummy instruction etc.
In another embodiment, can also increase an engine loading interface 204 that links to each other with engine memory module 202, be not solidificated in for test procedure under the situation of engine memory module 202, can load, upgrade or revise test control engine program to engine memory module 202 by engine loading interface 204.
In another embodiment, also arrange and test the universal input/output interface 205 that control engine modules 201 links to each other in the sheet, realize the information interaction outside test control engine modules and the sheet.Concrete mutual situation comprises: to the necessary detecting information of chip exterior output; Transmit control signal the work of control external test facility; With signal of receiving external unit etc.
Above-mentioned circuit under test module can be mimic channel, digital circuit or modulus hybrid circuit etc.
In sum, the present invention is mainly by will be to the testing process of circuit-under-test, unified standard is to the read-write of different registers and relevant operations such as calculating judgement, an instruction of the corresponding test control of each step operation engine, by writing different instruction sequences, finish different testing process control.Based on inventive concept of the present invention, the function control program can also be set, in unit of testing and controlling, by carrying out the function control program, realize the correlation function of chip, the mode of its signal controlling is identical with testing process of the present invention.
The above embodiment; it only is preferred embodiments of the present invention; be not for limiting protection scope of the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace or improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the interior hybrid test device of sheet is characterized in that, comprising: be arranged on circuit under test unit, control register unit, status register unit and unit of testing and controlling in the chip; Described control register unit is connected between the control signal input port and described unit of testing and controlling test signal transmitting terminal of described circuit under test unit; Described status register unit is connected between the status signal delivery outlet and described unit of testing and controlling test signal receiving end of described circuit under test unit; Described unit of testing and controlling is used for carrying out the processing procedure of test control engine data, and by the value of changing in the described control register unit described circuit under test unit is sent the test steering order, and read the status information that value in the described mode control register unit is obtained described circuit under test unit.
2. according to claim 1 interior hybrid test device, it is characterized in that, described circuit under test unit comprises a plurality of circuit under test modules, and described control register unit comprises a plurality of control register groups, and described status register unit comprises a plurality of status register groups; A described circuit under test module connects at least one described control register group and at least one described status register group.
3. according to claim 1 and 2 interior hybrid test device is characterized in that described unit of testing and controlling comprises: test control engine modules and engine memory module; Described engine memory module is used for the described test control of storage engine data; Described test control engine modules is finished test control by the test control engine data that calls described engine memory module.
4. according to claim 3 interior hybrid test device is characterized in that, also comprises the engine loading interface that links to each other with described engine memory module, is used for loading test control engine data to described engine memory module.
5. according to claim 3 interior hybrid test device, it is characterized in that described engine memory module is: any one in trigger memory module, register-stored module, random access storage device, ROM (read-only memory) and the nonvolatile memory.
6. according to claim 3 interior hybrid test device is characterized in that, also comprises the universal input/output interface that links to each other with described test control engine modules, is used for realizing the information interaction of described test control engine modules and sheet external equipment.
7. according to claim 2 interior hybrid test device is characterized in that, arbitrary described circuit under test module be in mimic channel and the digital circuit any one.
8. the interior mixed test method of sheet is characterized in that, comprises following processing procedure:
Unit of testing and controlling is carried out the processing of test control engine data;
Unit of testing and controlling is handled below carrying out at least one times in test process to control register unit and status register unit:
Unit of testing and controlling writes the test steering order to the control register unit, and the control register unit sends to the circuit under test unit with described test steering order;
The circuit test setting is finished according to the information of test steering order in the circuit under test unit, and with status information write state register cell, the status information in the unit of testing and controlling read status register unit.
9. according to claim 8 interior mixed test method is characterized in that, also comprises following processing procedure before the processing of described unit of testing and controlling execution test control engine data: call test control engine data from the engine memory module.
10. according to Claim 8 or 9 described interior mixed test methods, it is characterized in that, also comprise following processing procedure after described unit of testing and controlling is carried out the processing of test control engine data: unit of testing and controlling exports outside sheet by universal input/output interface that detecting information or unit of testing and controlling send control information by universal input/output interface testing apparatus outside sheet or unit of testing and controlling is passed through input signal outside the universal input/output interface receiving sheet.
11. according to Claim 8 or 9 described interior mixed test methods, it is characterized in that, before or after described test process, also comprise following processing procedure:
Unit of testing and controlling is carried out the processing of function control data;
Unit of testing and controlling is handled below carrying out at least one times in the function control procedure to control register unit and status register unit:
Unit of testing and controlling is to control register unit write-in functions steering order, and the control register unit sends to the circuit under test unit with described function steering order;
The circuit test setting is finished according to the information of test steering order in the circuit under test unit, and with status information write state register cell, the status information in the unit of testing and controlling read status register unit.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105137330A (en) * | 2014-05-22 | 2015-12-09 | 炬芯（珠海）科技有限公司 | Verification device of multiple-voltage domain digital circuit and operation method thereof |
| CN105988077A (en) * | 2015-02-06 | 2016-10-05 | 中国科学院微电子研究所 | Built-in self-testing method and device and system on chip |
| CN108241117A (en) * | 2016-12-23 | 2018-07-03 | 台湾福雷电子股份有限公司 | System and method for testing semiconductor devices |
| CN109239586A (en) * | 2018-08-17 | 2019-01-18 | 国营芜湖机械厂 | A kind of detection method of 1032 CPLD of LATTICE |
| CN111781488A (en) * | 2020-06-24 | 2020-10-16 | 芯佰微电子（北京）有限公司 | Chip and chip test system |
| CN112578271A (en) * | 2020-11-12 | 2021-03-30 | 北京中电华大电子设计有限责任公司 | Method for improving test efficiency of analog filter circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576603A (en) * | 2008-05-07 | 2009-11-11 | 环隆电气股份有限公司 | Testing device |
| CN101592706A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Digital and analog mixed signal chip test card |
-
2011
- 2011-12-27 CN CN201110444605.6A patent/CN103185859B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576603A (en) * | 2008-05-07 | 2009-11-11 | 环隆电气股份有限公司 | Testing device |
| CN101592706A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Digital and analog mixed signal chip test card |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105137330A (en) * | 2014-05-22 | 2015-12-09 | 炬芯（珠海）科技有限公司 | Verification device of multiple-voltage domain digital circuit and operation method thereof |
| CN105137330B (en) * | 2014-05-22 | 2018-09-25 | 炬芯（珠海）科技有限公司 | The verification device and its operation method of multiple voltage domain digital circuit |
| CN105988077A (en) * | 2015-02-06 | 2016-10-05 | 中国科学院微电子研究所 | Built-in self-testing method and device and system on chip |
| CN105988077B (en) * | 2015-02-06 | 2019-03-15 | 中国科学院微电子研究所 | Build-in self-test method, device and system on chip |
| CN108241117A (en) * | 2016-12-23 | 2018-07-03 | 台湾福雷电子股份有限公司 | System and method for testing semiconductor devices |
| CN108241117B (en) * | 2016-12-23 | 2021-02-05 | 台湾福雷电子股份有限公司 | System and method for testing semiconductor devices |
| CN109239586A (en) * | 2018-08-17 | 2019-01-18 | 国营芜湖机械厂 | A kind of detection method of 1032 CPLD of LATTICE |
| CN111781488A (en) * | 2020-06-24 | 2020-10-16 | 芯佰微电子（北京）有限公司 | Chip and chip test system |
| CN111781488B (en) * | 2020-06-24 | 2023-04-07 | 芯佰微电子（北京）有限公司 | Chip and chip test system |
| CN112578271A (en) * | 2020-11-12 | 2021-03-30 | 北京中电华大电子设计有限责任公司 | Method for improving test efficiency of analog filter circuit |
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