CN108205306B - Method and apparatus for calibrating a controller - Google Patents
Method and apparatus for calibrating a controller Download PDFInfo
- Publication number
- CN108205306B CN108205306B CN201711351904.9A CN201711351904A CN108205306B CN 108205306 B CN108205306 B CN 108205306B CN 201711351904 A CN201711351904 A CN 201711351904A CN 108205306 B CN108205306 B CN 108205306B
- Authority
- CN
- China
- Prior art keywords
- memory
- memory unit
- interface
- controller
- access mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015654 memory Effects 0.000 claims abstract description 68
- 238000011161 development Methods 0.000 claims description 7
- 238000004590 computer program Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 239000000523 sample Substances 0.000 claims 1
- 230000018109 developmental process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0426—Programming the control sequence
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention relates to a method (10) for calibrating a controller having a first memory unit, a second memory unit and an interface, wherein the first memory unit and the second memory unit have a common memory address, characterized by the following features: -writing a first value to the first memory unit and a second value deviating from the first value to the second memory unit in a configuration operation (11), -optionally switching the controller between a first access mode and a second access mode via the interface in a calibration operation (12), wherein in the first access mode the first memory unit is accessible at the memory address and in the second access mode the second memory unit is accessible at the memory address and-in an application operation (13) the first memory unit and the second memory unit are regularly occupied by a common value.
Description
Technical Field
The present invention relates to a method for calibrating a controller. The invention further relates to a corresponding device, a corresponding computer program and a corresponding storage medium.
Background
The parameterization (Parametrierung) of the software for the vehicle electronic control unit (SG) is carried out according to the prior art in a manner that allows the characteristics (Verhalten) of the control function, the regulating function and the diagnostic function to be easily adapted to a large number of system variants or vehicle models (fahrzeugmod ll) without having to change the calculation program. Within the scope of this adaptation, the characteristic values of the different functional algorithms are set by means of suitable tools (tools). The resulting vehicle characteristics (Fahrzeugverhalten) are determined together by the quality (gute) of the so-called application (application), which thus proves to be an important development step for novel motors.
In addition to logic analyzers, which are only rarely used, so-called test adapters (ICEs) are used for this purpose in modern microcontrollers with integrated memory. In this development phase, the microcontroller (μc) provided for series operation (seriebeteb) is mostly replaced by a version modified for use with ICE or other embedded-calibration-interfaces, such as XCP. Such emulation devices (emulation devices), which are as compatible as possible with the underlying serial model, are available according to the prior art even for modern multi-core-on-a-chip systems (socs), and typically include additional emulation memory in addition to complex filter-logic and trigger-logic and possibly trace-interfaces. This large emulation memory of up to several megabytes can be superimposed (uberlagern) with the primary flash memory (flashpeicher) of the microcontroller for calibration purposes, but increases the single-piece cost of the corresponding device and remains unused during the application run of the controller.
DE3018275C2 discloses a device for optimizing data and/or programs for a programmed controller, in particular for controlling ignition, fuel injection or transmission shift processes in a motor vehicle, said device comprising: having two program-and-data memories with changeable contents, to which the program and data of the controller are loaded; and having a control unit (Kontrolleinheit) which is provided for changing the program or the data, and which is optionally connected to one of the program and the data memory; and having a converter via which the programmed controller for processing the program can be connected to a program and data memory of the two program and data memories which is not connected to the control unit.
Disclosure of Invention
The invention provides a method for calibrating a controller, a corresponding device, a corresponding computer program and a corresponding storage medium according to the independent claims.
Nonvolatile memory technology, such as so-called phase-change memory (PCM), uses redundant memory cells for describing values for long-term data protection. If these redundant memory cells can be written to and read from separately, this enables the following use according to the invention.
In this regard, the EEProm simulation field (Emulation bereiche) of 40nm Renesas and IFX processors today is an example. Here, 0/1 information is allocated to 2 memory locations—for example, 0 logic is the first memory location 0 and the second memory location 1—for 1 logic the first memory location 1 and the second memory location 0. Thereby improving the Read Margin and the cell holds the data longer or can be made smaller. Another advantage is improved stability in terms of physical effects that affect only the logic 1 state or only the logic 0 state-thereby also improving the read margin.
In the development phase of the controller, one of the redundant memory cells is written with the initially set value and the other memory cell is written with the biased value. If this way of processing is extended to the whole data item, it appears as if a second storage side is constituted, which can be used similarly to the emulation memory of the conventional ICE: in case of control by an interface, switching between the sides is possible.
In addition to the calibration, the use of the second memory side can also be given (ubertragen) to program code components within the scope of an internal rapid prototypes (Rapid Prototyping) (Bypass). In this case, a new software part to be tested (Bypass software) is to be written into the second memory side. In contrast to the calibration, the entire memory side is not converted under control by the interface (by means of a hardware or software mechanism), but only at the location where the program code to be present (umgehend) begins. The new software component to be tested (Bypass software) uses the address space of the second memory side for executing the program stream.
The second storage side can extend over the entire storage area, and can also be divided into a plurality of sections, each of these sections being able to be converted separately from the other sections under control by an interface. This can also represent more than just one further calibration data item and can also test a plurality of software parts that can be switched on and off independently of one another at the same time.
The advantage of this solution is an unrestricted online simulation (In-Circuit-simulation) of the embedded (eingebetet) system without using separate development devices or tandem resources. The solution according to the invention does not incur additional costs for serial operation, since the redundant stored information is used there for data protection or OTA upgrades of serial functions, such as flash memories; expensive emulation memory can be eliminated.
Advantageous developments and improvements of the basic idea described in the independent claims can be achieved by the measures recited in the dependent claims.
Drawings
Embodiments of the invention are illustrated in the accompanying drawings and further explained in the following description. In the accompanying drawings:
fig. 1 shows a flow chart of a method 10 according to a first embodiment.
Fig. 2 schematically shows a controller according to a second embodiment.
Detailed Description
Fig. 1 shows a flow of the calibration according to the invention, which takes place by means of a controller 20 of the vehicle electronics. The memory is divided into two logical memory sides for the purposes of the following embodiments, which can be physically implemented, for example, by two cell arrays (cell arrays) of a redundant (redundancy) designed phase change memory (Phasenwechselspeicher).
The first memory unit comprised by the first memory side and the second memory unit comprised by the second memory side here share a common memory address and are configured such that they always store a consistent value in the application run (13) for protecting (absichenn) the controller against single byte errors (einzelb ithler) of one of the two memory sides. In both modes of operation according to the invention, the memory structure (Speicherarchitektur) is utilized in a biased manner (abweichend), which also enables the use of identical controllers within the scope of the development: for this purpose, in a configuration operation (11), first a first data item is written to the first memory side and a second data item is written to the second memory side, wherein the respective values of the memory cells assigned to one another can absolutely deviate from one another. This can be done, for example, according to the common measurement and calibration protocols (universal measurement and calibration protocol, XCP) known in the art.
In a subsequent calibration operation (12), the controller can then optionally switch between a first access mode (Zugriversodus), in which the first storage side is always accessed, and a second access mode, in which the second storage side is always accessed. In this calibration operation, the second memory side can be accessed not only in a read manner but also in a write manner. As in the configuration run (11), standardized interfaces, such as XCP (or similar products) sold by eta limited, ETK, are preferred for this.
Claims (9)
1. A method (10) for calibrating a controller having a first memory unit, a second memory unit and an interface, wherein the first memory unit and the second memory unit have a common memory address,
the method is characterized by comprising the following steps of:
writing a first value to the first memory cell and a second value deviating from the first value to the second memory cell in a configuration operation (11),
-switching the controller in a calibration run (12) via the interface optionally between a first access mode in which the first memory unit can be accessed at the memory address and a second access mode in which the second memory unit can be accessed at the same memory address, wherein the access mode can also be selected as a part for the entire memory and
-said first memory unit and said second memory unit form a common logical value in an application run (13).
2. The method (10) according to claim 1,
the method is characterized by comprising the following steps of:
the controller comprises a first storage side comprising the first storage unit and a second storage side comprising the second storage unit,
-writing a first data item to the first storage side and a second data item to the second storage side in the configuration run (11) and
-optionally switching the controller via the interface in the calibration run (12) such that the first storage side is accessible in the first access mode and the second storage side is accessible in the second access mode.
3. The method (10) according to claim 1 or 2,
the method is characterized by comprising the following steps of:
writing to the memory cells is performed via a common calibration interface or programming interface.
4. The method (10) according to claim 1 or 2,
the method is characterized by comprising the following steps of:
the interface is a common interface used in calibration.
5. The method (10) according to claim 1 or 2,
characterized by at least one of the following features:
-using the method (10) in a measurement process or
-using the method (10) in a prototype development process.
6. The method (10) according to claim 4,
the method is characterized by comprising the following steps of:
-the interface is an emulator probe.
7. The method (10) according to claim 5,
characterized by at least one of the following features:
-using the method (10) in calibration.
8. A machine-readable storage medium, on which a computer program is stored, which computer program is set up for carrying out the method (10) according to any one of claims 1 to 7.
9. Device in the form of a controller (20) which is designed to carry out the method (10) according to any one of claims 1 to 5.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102016225308.5 | 2016-12-16 | ||
| DE102016225308.5A DE102016225308A1 (en) | 2016-12-16 | 2016-12-16 | Method and device for calibrating a control unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108205306A CN108205306A (en) | 2018-06-26 |
| CN108205306B true CN108205306B (en) | 2023-05-05 |
Family
ID=62251602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711351904.9A Active CN108205306B (en) | 2016-12-16 | 2017-12-15 | Method and apparatus for calibrating a controller |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108205306B (en) |
| DE (1) | DE102016225308A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656607A (en) * | 2019-01-03 | 2019-04-19 | 广西玉柴机器股份有限公司 | A kind of full address scaling method that supporting super large nominal data amount and system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3018275A1 (en) | 1980-05-13 | 1981-11-19 | Robert Bosch Gmbh, 7000 Stuttgart | DEVICE FOR OPTIMIZING DATA AND / OR PROGRAMS FOR PROGRAMMED CONTROL UNITS |
| ATE382894T1 (en) * | 2004-07-27 | 2008-01-15 | Nokia Siemens Networks Gmbh | METHOD AND DEVICE FOR SECURING CONSISTENT MEMORY CONTENTS IN REDUNDANT STORAGE UNITS |
| JP5018074B2 (en) * | 2006-12-22 | 2012-09-05 | 富士通セミコンダクター株式会社 | Memory device, memory controller and memory system |
| WO2009116117A1 (en) * | 2008-03-19 | 2009-09-24 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor memoery, system, method for operating semiconductor memory, and method for manufacturing semiconductor memory |
| KR20110050404A (en) * | 2008-05-16 | 2011-05-13 | 퓨전-아이오, 인크. | Apparatus, system, and method for detecting and replacing failed data storage |
| DE102010031282B4 (en) * | 2010-07-13 | 2022-05-12 | Robert Bosch Gmbh | Method of monitoring a data store |
| JP5902137B2 (en) * | 2013-09-24 | 2016-04-13 | 株式会社東芝 | Storage system |
-
2016
- 2016-12-16 DE DE102016225308.5A patent/DE102016225308A1/en active Pending
-
2017
- 2017-12-15 CN CN201711351904.9A patent/CN108205306B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| DE102016225308A1 (en) | 2018-06-21 |
| CN108205306A (en) | 2018-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105474319B (en) | For configuring the device and method of the I/O of the memory of mixing memory module | |
| US7774382B2 (en) | Method and apparatus for configuring a control device, and corresponding control device | |
| US6393342B2 (en) | Method and device for controlling operating sequences in a vehicle | |
| US6370456B2 (en) | Method for applying control data for an electronic motor vehicle control unit | |
| US7538577B2 (en) | System and method for configuring a field programmable gate array | |
| US20090187305A1 (en) | Method of detecting manipulation of a programmable memory device of a digital controller | |
| WO2007044926A2 (en) | Initialization of flash storage via an embedded controller | |
| CN107690630B (en) | Calculate the bridge configuration in equipment | |
| CN107479918B (en) | Reconfigurable FPGA (field programmable Gate array) model for MCU (microprogrammed control Unit) burning | |
| CN114237122B (en) | Circuit and operation method for configuring, reading back and refreshing SRAM type FPGA | |
| WO2008101318A1 (en) | System and method of page buffer operation for memory devices | |
| US7493519B2 (en) | RRAM memory error emulation | |
| CN110765032A (en) | Method for reading and writing I2C memory based on system management bus interface | |
| CN110658991A (en) | Multi-level cell data load optimization | |
| US20050207232A1 (en) | Access method for a NAND flash memory chip, and corresponding NAND flash memory chip | |
| CN103185859A (en) | In-chip mixed testing device and in-chip mixed testing method | |
| CN108205306B (en) | Method and apparatus for calibrating a controller | |
| CN103117088A (en) | Semiconductor device and method of operating the same | |
| EP2778910B1 (en) | Systems and methods to extend rom functionality | |
| US6735514B2 (en) | Control device for a vehicle engine | |
| KR102434821B1 (en) | Methods and devices for updating programs | |
| CN116259352A (en) | Nonvolatile storage self-adaptive control system | |
| US20210042178A1 (en) | Health characteristics of a memory device | |
| US20220283726A1 (en) | Method for assisting in the identification of blank sectors of a non-volatile memory of a microcontroller | |
| US7502874B2 (en) | Methods and systems for integrating unique information in SAS interface components |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |