CN109239586A - A kind of detection method of 1032 CPLD of LATTICE - Google Patents
A kind of detection method of 1032 CPLD of LATTICE Download PDFInfo
- Publication number
- CN109239586A CN109239586A CN201810941769.1A CN201810941769A CN109239586A CN 109239586 A CN109239586 A CN 109239586A CN 201810941769 A CN201810941769 A CN 201810941769A CN 109239586 A CN109239586 A CN 109239586A
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- China
- Prior art keywords
- cpld
- chip
- detection method
- mouthfuls
- lattice
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
Abstract
The present invention relates to the detection methods of 1032 CPLD of LATTICE a kind of, including register functions test and basic logic functions test, pass through input clock signal, the fractional frequency signal of detection respective pins output judges whether the register functions of CPLD are normal, it is detected by input and output, judges whether the IO input/output function of tested CPLD is normal using light emitting diode.Screening of electric components and the fault detection of LATTICE 1032CPLD may be implemented in the present invention, largely reduces the waste in production process, economizes on resources, reduce cost, and operation of the present invention process is simple, easily operated, has good practicability.
Description
Technical field
The present invention relates to CPLD chip detection field, specifically a kind of detection method of 1032 CPLD of LATTICE.
Background technique
ISP1032 is one of the ISP series online programmable device of Lattice company production, has small in size, appearance
Amount is big, programming is convenient, convenient for the advantages that on-line debugging, it can be achieved that fairly large circuit design and can realize programming encryption.
ISP1032 price is higher, and screening of electric components process is especially lacked after volume procurement, not can guarantee the formedness of device；It is another
Aspect, since ISP1032 internal crosslinking is excessive, if contain multiple ISP1032 and circuit malfunctions in circuit, it is difficult to by event
Barrier navigates to the ISP1032 of a certain determination, and existing literature focuses mostly on for the research of ISP1032 in application, can not
The application special suitable for these is based on this, input/output test is carried out to all I/O ports of CPLD, to guarantee the core
Piece function is intact.
Summary of the invention
Technical problem to be solved by the present invention lies in the detection method of 1032 CPLD of LATTICE a kind of is proposed, lead to
It crosses design associated hardware circuitry and software program realizes all port I/O input/output tests of 1032 CPLD of LATTICE, be applicable in
In the particular applications such as the screening of electric components of the device and fault location, cost and easy to operate can be effectively reduced.
The technical problems to be solved by the invention are realized using following technical scheme:
A kind of detection method of 1032 CPLD of LATTICE, which is characterized in that comprising steps of
S1) register functions are tested；
S2) basic logic functions are tested.
Further, the step s1) it include waveform output test function, the program write is burnt into chip, is led to
The clock signal that the onboard crystal oscillator of process ordered pair provides carries out scaling down processing, exports the square wave of fixed frequency in corresponding output port,
And it is detected with oscillograph.
Further, the step s2) it include level output test function, it is inputted by program in chip input port
Level low/high directly exports high/low level in output port, by showing LED macroscopic examination.
Further, chip I/O is grouped in detection process.
Further, I/O mouthfuls of the odd number of the chip testing interface of number UA are signal input port, and I/O mouthfuls of even number are letter
Number output port.
Further, I/O mouthfuls of the even number of the chip testing interface of number UB are signal input port, and I/O mouthfuls of odd number are letter
Number output port.
The beneficial effects of the present invention are:
(1) screening of electric components and the fault detection of LATTICE 1032CPLD may be implemented in the test method, largely
Ground reduces the waste in production process, economizes on resources, reduces cost；
(2) operating process is simple, easily operated, has good practicability.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 1 is test flow chart of the invention；
Fig. 2 is test board function distribution map of the invention.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below it is right
The present invention is further described.
LATTICE 1032CPLD shares 84 pins: 64 I/O pins, 4 dedicated input pins, 1 reset pin
And dedicated clock signal input pin, since the port I/O is the important component and major function pin of CPLD,
The test method need to be related to the detection of all ports I/O.
For this Function detection of realization, following design has been carried out to its detection method:
A kind of detection method of 1032 CPLD of LATTICE, which is characterized in that comprising steps of
S1) register functions are tested；
S2) basic logic functions are tested.
Further, the step s1) it include waveform output test function, the program write is burnt into chip, is led to
The clock signal that the onboard crystal oscillator of process ordered pair provides carries out scaling down processing, exports the square wave of fixed frequency in corresponding output port,
And it is detected with oscillograph.
Further, the step s2) it include level output test function, it is inputted by program in chip input port
Level low/high directly exports high/low level in output port, by showing LED macroscopic examination.
Since chip I/O pin is more, complex and disunity is directly tested, is examined so chip is divided into two groups
It surveys, is also convenient for directly observing and testing.UA, UB are two groups of chip socket, for completing the test of two groups of ports difference I/O, two
The detection of all ports I/O is completed after the completion of group test
Further, chip I/O is grouped in detection process.
Further, I/O mouthfuls of the odd number of the chip testing interface of number UA are signal input port, and I/O mouthfuls of even number are letter
Number output port.
Further, I/O mouthfuls of the even number of the chip testing interface of number UB are signal input port, and I/O mouthfuls of odd number are letter
Number output port.
The step s1) predominantly test chip interior gate circuit and sequence circuit it is whether working properly, and waveform whether
It is consistent with the waveform pre-set.If after testing two groups, the waveform of output port is consistent with the waveform pre-set,
Then the chip is normal.
The step s2) predominantly directly whether observation chip is normal as the port of output, if corresponding is all
When the display LED of output port is bright, illustrate that this group of port I/O is normal.After testing two groups, if whole diode be all it is bright,
Then the chip is normal.
Here is one embodiment of the present of invention:
Test board function distribution map as shown in Figure 2:
UA, UB are two chip carrier sockets, and CPLD chip, which needs to do two groups of tests respectively, could complete all port I/O inspections
It surveys, but two test groups are independent of each other, it can while testing two panels chip.
S1 is functional select switch, and dialling upwards is level detecting, to setting aside as waveform testing；S3 is lever selection switch,
Dialling upwards is high level, to setting aside as low level.
Crystal oscillator provides clock signal, and light emitting diode instruction area is that level detecting shows and divide test display.
Test flow chart as shown in Figure 1:
When testing chip register function, the good scaling down processing program of burning, switching S1 are switched to waveform in the chip in advance
Gear is tested, provides clock signal by crystal oscillator, be powered test on UA chip carrier socket, detects even number I/O mouthfuls using oscillograph
Output signal whether be frequency dividing after waveform, after the completion of test by chip be placed on UB chip carrier socket be powered test, use
Oscillograph detect odd number I/O mouthful output signal whether be frequency dividing after waveform, then carry out detection record, judge all I/O
Register functions quality.
When testing chip basic logic functions, the good input/output routine of burning in the chip in advance, it is defeated for making I/O mouthful of odd number
Entrance, I/O mouthfuls of even number are delivery outlet, and when I/O mouthfuls of input high levels of odd number, corresponding even number I/O mouthfuls also export high level, cut
S1 switch is changed to level detecting gear, chip under test is placed into be powered on UA chip carrier socket and is tested, switching S3 switch is to VCC grades
I/O mouthfuls of odd number of position, UA chip carrier socket are signal input port, are entered high level signal at this time, corresponding even number I/O mouthfuls are answered
The light emitting diode that high level signal is drivingly connected is exported, indicates that area indicates lamp on/off feelings accordingly by statistics light emitting diode
Condition can obtain corresponding one group I/O mouthfuls of input and output of fine or not situation；
Identically as above-mentioned steps, the good input/output routine of burning in the chip in advance, make I/O mouthfuls of even number for input port,
I/O mouthfuls of odd number are delivery outlet, and when I/O mouthfuls of input high levels of even number, corresponding odd number I/O mouthfuls also export high level, switch S1
Level detecting gear is switched, chip under test is placed into be powered on UB chip carrier socket and is tested, switching S3 switch to VCC gear,
I/O mouthfuls of even number of UA chip carrier socket are signal input port, are entered high level signal at this time, corresponding odd number I/O mouthfuls answer it is defeated
The light emitting diode that high level signal is drivingly connected out indicates that area indicates lamp on/off situation accordingly by statistics light emitting diode
Corresponding one group I/O mouthfuls of input and output of fine or not situation can be obtained.
After the completion of two tests, by recording test process, a certain I/O mouthfuls of input/output function and register can be determined
Whether function is normal.
The basic principles, main features and advantages of the present invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and what is described in the above embodiment and the description is only the present invention
Principle, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these variation and
Improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its equivalent
Object defines.
Claims (6)
1. a kind of detection method of 1032 CPLD of LATTICE, which is characterized in that comprising steps of
S1) register functions are tested；
S2) basic logic functions are tested.
2. the detection method of 1032 CPLD of LATTICE according to claim 1 a kind of, it is characterised in that: the step
S1 include) waveform output test function, the program write is burnt into chip, the clock that onboard crystal oscillator is provided by program
Signal carries out scaling down processing, in the square wave of corresponding output port output fixed frequency, and is detected with oscillograph.
3. the detection method of 1032 CPLD of LATTICE according to claim 1 a kind of, it is characterised in that: the step
S2) include level output test function, level low/high is inputted in chip input port by program, it is directly defeated in output port
High/low level out, by showing LED macroscopic examination.
4. the detection method of 1032 CPLD of LATTICE according to claim 2 or 3 a kind of, it is characterised in that: detected
Chip I/O is grouped in journey.
5. the detection method of 1032 CPLD of LATTICE according to claim 4 a kind of, it is characterised in that: number UA's
I/O mouthfuls of odd number of chip testing interface are signal input port, and I/O mouthfuls of even number are signal output port.
6. the detection method of 1032 CPLD of LATTICE according to claim 4 a kind of, it is characterised in that: number UB's
I/O mouthfuls of even number of chip testing interface are signal input port, and I/O mouthfuls of odd number are signal output port.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810941769.1A CN109239586A (en) | 2018-08-17 | 2018-08-17 | A kind of detection method of 1032 CPLD of LATTICE |
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| CN201810941769.1A CN109239586A (en) | 2018-08-17 | 2018-08-17 | A kind of detection method of 1032 CPLD of LATTICE |
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4320528A1 (en) * | 1992-06-22 | 1993-12-23 | Mitsubishi Electric Corp | Integrated circuit on-chip automatic test function circuit - has decoder for receiving data from control register describing test pattern generator to be used and which functional block is to be tested, and data bus for transferring test data to block. |
| CN1841079A (en) * | 2005-03-28 | 2006-10-04 | 大唐移动通信设备有限公司 | Detection method for configuration of programmable logic device |
| JP2007201802A (en) * | 2006-01-26 | 2007-08-09 | Oki Electric Ind Co Ltd | Data transfer circuit |
| US20080005634A1 (en) * | 2006-06-29 | 2008-01-03 | Grise Gary D | Scan chain circuitry that enables scan testing at functional clock speed |
| CN201637820U (en) * | 2009-12-31 | 2010-11-17 | 芯通科技（成都）有限公司 | Low-cost programmable logic array logic analyzing device |
| CN202285042U (en) * | 2011-10-25 | 2012-06-27 | 成都芯通科技股份有限公司 | Automatic test system for complex programmable logic device (CPLD) |
| CN102928766A (en) * | 2012-10-26 | 2013-02-13 | 福州瑞芯微电子有限公司 | Device and method for configuring parameters in high-speed test of chips |
| CN103185859A (en) * | 2011-12-27 | 2013-07-03 | 国民技术股份有限公司 | In-chip mixed testing device and in-chip mixed testing method |
| CN103323768A (en) * | 2013-06-09 | 2013-09-25 | 苏州大学 | Designated high-speed DA chip performance parameter testing method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN104035846A (en) * | 2014-05-21 | 2014-09-10 | 青岛歌尔声学科技有限公司 | Method and device for detecting burning state of CPLD firmware |
| CN104678292A (en) * | 2015-03-09 | 2015-06-03 | 杭州华三通信技术有限公司 | Test method and device for CPLD (Complex Programmable Logic Device) |
| CN108089964A (en) * | 2017-12-07 | 2018-05-29 | 郑州云海信息技术有限公司 | A kind of device and method by BMC monitoring server CPLD states |
-
2018
- 2018-08-17 CN CN201810941769.1A patent/CN109239586A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4320528A1 (en) * | 1992-06-22 | 1993-12-23 | Mitsubishi Electric Corp | Integrated circuit on-chip automatic test function circuit - has decoder for receiving data from control register describing test pattern generator to be used and which functional block is to be tested, and data bus for transferring test data to block. |
| CN1841079A (en) * | 2005-03-28 | 2006-10-04 | 大唐移动通信设备有限公司 | Detection method for configuration of programmable logic device |
| JP2007201802A (en) * | 2006-01-26 | 2007-08-09 | Oki Electric Ind Co Ltd | Data transfer circuit |
| US20080005634A1 (en) * | 2006-06-29 | 2008-01-03 | Grise Gary D | Scan chain circuitry that enables scan testing at functional clock speed |
| CN201637820U (en) * | 2009-12-31 | 2010-11-17 | 芯通科技（成都）有限公司 | Low-cost programmable logic array logic analyzing device |
| CN202285042U (en) * | 2011-10-25 | 2012-06-27 | 成都芯通科技股份有限公司 | Automatic test system for complex programmable logic device (CPLD) |
| CN103185859A (en) * | 2011-12-27 | 2013-07-03 | 国民技术股份有限公司 | In-chip mixed testing device and in-chip mixed testing method |
| CN102928766A (en) * | 2012-10-26 | 2013-02-13 | 福州瑞芯微电子有限公司 | Device and method for configuring parameters in high-speed test of chips |
| CN103323768A (en) * | 2013-06-09 | 2013-09-25 | 苏州大学 | Designated high-speed DA chip performance parameter testing method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN104035846A (en) * | 2014-05-21 | 2014-09-10 | 青岛歌尔声学科技有限公司 | Method and device for detecting burning state of CPLD firmware |
| CN104678292A (en) * | 2015-03-09 | 2015-06-03 | 杭州华三通信技术有限公司 | Test method and device for CPLD (Complex Programmable Logic Device) |
| CN108089964A (en) * | 2017-12-07 | 2018-05-29 | 郑州云海信息技术有限公司 | A kind of device and method by BMC monitoring server CPLD states |
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Application publication date: 20190118 |