CN105652182B - A kind of board failure positioning system and method based on circuit network and graph search - Google Patents
A kind of board failure positioning system and method based on circuit network and graph search Download PDFInfo
- Publication number
- CN105652182B CN105652182B CN201511000975.5A CN201511000975A CN105652182B CN 105652182 B CN105652182 B CN 105652182B CN 201511000975 A CN201511000975 A CN 201511000975A CN 105652182 B CN105652182 B CN 105652182B
- Authority
- CN
- China
- Prior art keywords
- test
- node
- test node
- failure
- fault
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
Abstract
The board failure positioning system based on circuit network and graph search that the invention discloses a kind of, the system include：Test node attribute acquisition module, the attribute information for obtaining test node, the attribute information include：Circuit interface attribute and test execution attribute；Routing file acquisition module, for obtaining routing file, the routing file is used to describe the line relationship between the channel of test equipment and test node；Optimal node selecting module, for being screened to manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter；Test logic generation module, the test logic for generating the optimal node set interior joint that screening obtains based on test node attribute information and routing file；Test result output module for being tested the test point of selection based on obtained test logic, and then completes the fault location of circuit board.
Description
Technical field
It is the invention belongs to circuit board testing and diagnostic techniques field, more particularly to a kind of based on circuit network and graph search
Board failure localization method.
Background technology
Circuit board needs to measure acquisition to the data of intermediate node in fault location, and is carried out according to measurement result
The judgement and analysis of circuit state are inferred to the Test Strategy of next step；At present in board failure positioning, depend on
It is manually entered corresponding test node information and determines the testing sequence of node, heavy workload, the degree of automation be not high and leads
Cause quantity and distribution not enough optimization, the topological logic of test node not strong.
It proposes to grind on the basis of existing TP development approaches with the efficiency for diagnosing TP exploitations to improve circuit board testing
It is then very necessary to make the board failure localization method based on circuit network and graph search.
Invention content
It is an object of the present invention in order to solve the above technical problems, the present invention provide it is a kind of based on circuit network and
The board failure positioning system and method for graph search.
To achieve the goals above, the present invention provides a kind of based on the board failure of circuit network and graph search positioning system
System, the system include：
Test node attribute acquisition module, the attribute information for obtaining test node, the attribute information include：Circuit
Interface attributes and test execution attribute；
Routing file acquisition module, for obtaining routing file, the routing file is used to describe the channel of test equipment
Line relationship between test node；
Optimal node selecting module, for being carried out to manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter
Screening, and then several nodes is selected to form optimal test node set, wherein the Fault Isolation degree characterization test point pair event
The separating capacity of barrier；
Test logic generation module, it is optimal for being obtained based on test node attribute information and routing file generation screening
The test logic of node set interior joint, or generate based on test node attribute information and routing file the survey of automatic test node
Try logic；The wherein described test logic relationship includes：Sequentially, it selects, recycle or redirects；
Test result output module, for being tested the test point of selection based on obtained test logic, so that it is complete
At the fault location of circuit board.
Optionally, above system also includes：
Configuration module, the testing attribute of the test node for inputting the circuit board under test needed to configure, the test belong to
Property includes：Circuit interface attribute and test execution attribute；
Routing file generation module, the attribute information for the test node based on input generate test node and tester
The routing file of device, wherein the routing file is used to describe the line relationship between the channel of test equipment and test node.
Optionally, above system also includes：
Storage and interface module, for storing fault location result and being used for and the testing and diagnosing based on intelligent algorithm
The interface of knowledge；
Image management module, importing, editor, attribute setting for completing schematic diagram and PCB to institute's test circuit plate
And preservation.
Further alternative, above-mentioned optimal node selecting module further includes：
First processing submodule, the difference degree factor for calculating each test node to be selected, and according to obtain difference degree because
The value of son resequences test node to be selected by descending order；
Second processing submodule is sky for initializing optimal test node collection N*, and marks the survey to be selected after reordering
The collection of examination node is combined into P={ P0, P1 ..., Pi ... Pk }, while the value of initiation parameter i is i=1, the value model of wherein i
Enclose for：I=1 ..., K, wherein K is the total number of node to be tested；
Third handles submodule, for selecting node Pi from the set of test node to be selected, to test node Pi's
Fault signature data set carries out failure and sorts out calculating；
And according to the result of calculation of all test samples, the Fault Isolation group of test node Pi is calculatedWith failure every
From degree
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node PiIt is whether true, if equation meets, test node Pi is added to verification set N*, and drive end submodule
Block；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1, restarting third handle submodule
Block is handled；Otherwise, test Pi is added to verification set N*, opens third processing submodule；
Terminate submodule, the optimal test node for judging when selection can distinguish faulty, then optimal set of node
The screening process of conjunction terminates.
Optionally, said program obtains the value of the difference degree factor with the following method：
First, the inter- object distance d of i-th of test node jth class fault sample is definedijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；The meaning of j=1,2 ..., M, m and n is；N is sample
Number, K are the total number of node to be tested, and M is failure classes total number, Pij(m) and Pij(n) i-th of test point is indicated respectively
Characteristic value of the j classes failure for m-th and n-th sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D of the between class distance of M class of i-th of test pointi' be：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωμ and the ω class of i-th of test point are indicated respectively
N number of sample average value；
Then, it is based on above-mentioned parameter, defines the difference degree α of test node iiCalculation formula be：
αi=(D 'i/Di)·(min(Rbi)/max(Rwi)) (5)
Wherein, min (Rbi) and max (Rwi) indicate respectively between the infima species of i-th of test node sample data centrifugal pump and
Centrifugal pump in maximum kind.
Optionally, said program obtains the Fault Isolation degree of test node Pi with the following method：
Candidate test node after reordering is denoted as Pi, M class fault modes are denoted as failure collection F={ F0,F1,…,
FM-1, wherein F0For non-failure conditions；It provides as follows：
1) if all fault samples are accurately identified under certain fault mode Fm in F, and to arbitrary under remaining fault mode
The case where being misdiagnosed as Fm is not present in fault sample, then provides Fault Isolation group：It is the one of test node Pi
A Fault Isolation group, and only include an element Fm in the failure collection；
If 2) the partial fault sample in fault mode Fm is misdiagnosed as failure Fn, remember that Fm and Fn belong to test node Pi
A failure ambiguity group, and be denoted as：If the part sample in Fm be misdiagnosed as fault mode Fn and
Fq then remembers that Fm, Fn and Fq are a failure ambiguity group of test node Pi, is denoted asClass successively
It pushes away；
Middle m, n, q=0,1 ..., M-1 wherein defined above；m≠n≠q；
Definition power set ρ (F) indication circuit failure collection F=F0, F1 ..., FM-1 }；It is all for test node Pi
The set of failure ambiguity group；For the set of all Fault Isolation groups of test node Pi；
It is obtained according to above-mentioned definition：
Wherein, | | to take element number, i.e. failure number in set；
Isolation is defined, for test node Pi and M class fault mode, the Fault Isolation degree for defining test node is：
Obviously,
The Fault Isolation degree of all test nodes is calculated using K nearest neighbor algorithms.
In addition, the present invention also provides a kind of board failure localization method based on circuit network and graph search, described
Method includes：
Step 101) obtains the attribute information of test node, and the testing attribute includes：Circuit interface attribute and test are held
Row attribute；
Step 102) obtains routing file, and the routing file is for describing between the channel of test equipment and test node
Line relationship；
Step 103) screens manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter, and then selects
Several nodes form optimal test node set：Wherein, separating capacity of the Fault Isolation degree characterization test point to failure；
Step 104) is generated in the optimal node set that screening obtains based on test node attribute information and routing file and is saved
The test logic of point, or generate based on test node attribute information and routing file the test logic of automatic test node；Wherein
The test logic includes：The logical relation includes：Sequentially, it selects, recycle or redirects；
Step 105) tests test node based on obtained test logic, and then the failure for completing circuit board is fixed
Position.
Optionally, above-mentioned steps 101) also include before：
The testing attribute of the test node of the circuit board under test needed to configure is inputted, the testing attribute includes：Circuit connects
Mouth attribute and test execution attribute；
The attribute information of test node based on input generates the routing file of test node and test equipment, wherein institute
Routing file is stated for describing the line relationship between the channel of test equipment and test node.
Optionally, above-mentioned steps 103) it further includes：
Step 103-1) calculate the difference degree factor of each test node to be selected, and according to obtain the value of the difference degree factor by from
It arrives small sequence greatly test node to be selected is resequenced；
Step 103-2) the optimal test node collection N* of initialization is sky, and marks the collection of the test node to be selected after reordering
It is combined into P={ P0, P1 ..., Pk }, while the value of initiation parameter i is i=1, the wherein value range of i is：I=1 ..., K,
Wherein, K is the total number of node to be tested；
Step 103-3) node Pi is selected from the set of test node to be selected, to the fault signature data set of node Pi
It carries out failure and sorts out calculating；
And according to the result of calculation of all test samples, the Fault Isolation group of test node Pi is calculatedWith failure every
From degree
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node PiIt is whether true, if equation meets, test node Pi is added to verification set N*, and be transferred to step 103-
4)；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1 is transferred to step 103-3)；Otherwise,
Test Pi is added to verification set N*, is transferred to step 103-3)；
Step 103-4) faulty, the then screening of optimal node set can be distinguished when the optimal test node of selection
Journey terminates.
Optionally, said program also obtains the value of the difference degree factor with the following method：
Define the inter- object distance d of i-th of test node jth class fault sampleijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；The meaning of j=1,2 ..., M, m and n are (m and n：Greatly
In 1 and be natural number)；N is number of samples, and K is test node total number, and M is failure classes total number, Pij(m),Pij(n) respectively
Indicate characteristic value of i-th of test point jth class failure for m-th and n-th sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D of the between class distance of M class of i-th of test pointi' be：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωμ and the ω class of i-th of test point are indicated respectively
N number of sample average value；
Define the difference degree α of test node iiFor：
αi=(D 'i/Di)·(min(Rbi)/max(Rwi)) (5)
Wherein, min (Rbi) and max (Rwi) indicate respectively between the infima species of i-th of test node sample data centrifugal pump and
Centrifugal pump in maximum kind.
Compared with prior art, the beneficial effects of the present invention are：
The present invention is on the basis of existing TP develops software, and emphasis improves the ease for use and development efficiency of TP exploitations.It is main
Solve the problems, such as following various aspects：TP writes, debugs and tests not intuitive；TP writes heavy workload；TP durabilities are poor；TP
It changes relatively complicated；The offline debugging functions of TP are weak；It is independent mutually between TP and intelligent diagnostics algorithm.
Description of the drawings
Fig. 1 is the flow diagram of method provided by the invention；
Fig. 2 is the groundwork flow chart of technical solution of the present invention.
Specific implementation mode
The present invention will be described in detail in the following with reference to the drawings and specific embodiments.
The present invention provides a kind of board failure positioning system based on circuit network and graph search, and the system includes：
Test node attribute acquisition module, the attribute information for obtaining test node, the attribute information include：Circuit
Interface attributes and test execution attribute；
Routing file acquisition module, for obtaining routing file, the routing file is used to describe the channel of test equipment
Line relationship between test node；
Optimal node selecting module, for being carried out to manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter
Screening, and then several nodes is selected to form optimal test node set, wherein the Fault Isolation degree characterization test point pair event
The separating capacity of barrier；
Test logic generation module, it is optimal for being obtained based on test node attribute information and routing file generation screening
The test logic of node set interior joint, or generate based on test node attribute information and routing file the survey of automatic test node
Try logic；The wherein described test logic includes：The logical relation includes：Sequentially, it selects, recycle or redirects；
Test result output module, for being tested the test point of selection based on obtained test logic, so that it is complete
At the fault location of circuit board.
Optionally, above system also includes：
Configuration module, the testing attribute of the test node for inputting the circuit board under test needed to configure, the test belong to
Property includes：Circuit interface attribute and test execution attribute；
Routing file generation module, the attribute information for the test node based on input generate test node and tester
The routing file of device, wherein the routing file is used to describe the line relationship between the channel of test equipment and test node.
Optionally, above system also includes：
Storage and interface module, for storing fault location result and being used for and the testing and diagnosing based on intelligent algorithm
The interface of knowledge；
Image management module, importing, editor, attribute setting for completing schematic diagram and PCB to institute's test circuit plate
And preservation.
Further alternative, above-mentioned optimal node selecting module further includes：
First processing submodule, the difference degree factor for calculating each test node to be selected, and according to obtain difference degree because
The value of son resequences test node to be selected by descending order；
Second processing submodule is sky for initializing optimal test node collection N*, and marks the survey to be selected after reordering
The collection of examination node is combined into P={ P0, P1 ..., Pi ... Pk }, while the value of initiation parameter i is i=1, the value model of wherein i
Enclose for：I=1 ..., K, wherein K is the total number of node to be tested；
Third handles submodule, for selecting node Pi from the set of test node to be selected, to test node Pi's
Fault signature data set carries out failure and sorts out calculating；
And according to the result of calculation of all test samples, the Fault Isolation group of test node Pi is calculatedWith failure every
From degree
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node PiIt is whether true, if equation meets, test node Pi is added to verification set N*, and drive end submodule
Block；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1, restarting third handle submodule
Block is handled；Otherwise, test Pi is added to verification set N*, opens third processing submodule；
Terminate submodule, the optimal test node for judging when selection can distinguish faulty, then optimal set of node
The screening process of conjunction terminates.
Optionally, said program obtains the value of the difference degree factor with the following method：
First, the inter- object distance d of i-th of test node jth class fault sample is definedijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；The meaning of j=1,2 ..., M, m and n is；N is sample
Number, K are the total number of node to be tested, and M is failure classes total number, Pij(m) and Pij(n) i-th of test point is indicated respectively
Characteristic value of the j classes failure for m-th and n-th sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D of the between class distance of M class of i-th of test pointi' be：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωμ and the ω class of i-th of test point are indicated respectively
N number of sample average value；
Then, it is based on above-mentioned parameter, defines the difference degree α of test node iiCalculation formula be：
αi=(D 'i/Di)·(min(Rbi)/max(Rwi)) (5)
Wherein, min (Rbi) and max (Rwi) indicate respectively between the infima species of i-th of test node sample data centrifugal pump and
Centrifugal pump in maximum kind.
Optionally, said program obtains the Fault Isolation degree of test node Pi with the following method：
Candidate test node after reordering is denoted as Pi, M class fault modes are denoted as failure collection F={ F0,F1,…,
FM-1, wherein F0For non-failure conditions；It provides as follows：
1) if all fault samples are accurately identified under certain fault mode Fm in F, and to arbitrary under remaining fault mode
The case where being misdiagnosed as Fm is not present in fault sample, then provides Fault Isolation group：It is the one of test node Pi
A Fault Isolation group, and only include an element Fm in the failure collection；
If 2) the partial fault sample in fault mode Fm is misdiagnosed as failure Fn, remember that Fm and Fn belong to test node Pi
A failure ambiguity group, and be denoted as：If the part sample in Fm be misdiagnosed as fault mode Fn and
Fq then remembers that Fm, Fn and Fq are a failure ambiguity group of test node Pi, is denoted asClass successively
It pushes away；
Middle m, n, q=0,1 ..., M-1 wherein defined above；m≠n≠q；
Definition power set ρ (F) indication circuit failure collection F=F0, F1 ..., FM-1 }；It is all for test node Pi
The set of failure ambiguity group；For the set of all Fault Isolation groups of test node Pi；
It is obtained according to above-mentioned definition：
Wherein, | | to take element number, i.e. failure number in set；
Isolation is defined, for test node Pi and M class fault mode, the Fault Isolation degree for defining test node is：
Obviously,
The Fault Isolation degree of all test nodes is calculated using K nearest neighbor algorithms.
In addition, the present invention also provides a kind of board failure localization method based on circuit network and graph search, described
Method includes：
Step 101) obtains the attribute information of test node, and the testing attribute includes：Circuit interface attribute and test are held
Row attribute；
Step 102) obtains routing file, and the routing file is for describing between the channel of test equipment and test node
Line relationship；
Step 103) screens manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter, and then selects
Several nodes form optimal test node set：Wherein, separating capacity of the Fault Isolation degree characterization test point to failure；
Step 104) is generated in the optimal node set that screening obtains based on test node attribute information and routing file and is saved
The test logic of point, or generate based on test node attribute information and routing file the test logic of automatic test node；Wherein
The test logic includes：The logical relation includes：Sequentially, it selects, recycle or redirects；
Step 105) tests test node based on obtained test logic, and then the failure for completing circuit board is fixed
Position.
Optionally, above-mentioned steps 101) also include before：
The testing attribute of the test node of the circuit board under test needed to configure is inputted, the testing attribute includes：Circuit connects
Mouth attribute and test execution attribute；
The attribute information of test node based on input generates the routing file of test node and test equipment, wherein institute
Routing file is stated for describing the line relationship between the channel of test equipment and test node.
Optionally, above-mentioned steps 103) it further includes：
Step 103-1) calculate the difference degree factor of each test node to be selected, and according to obtain the value of the difference degree factor by from
It arrives small sequence greatly test node to be selected is resequenced；
Step 103-2) the optimal test node collection N* of initialization is sky, and marks the collection of the test node to be selected after reordering
It is combined into P={ P0, P1 ..., Pk }, while the value of initiation parameter i is i=1, the wherein value range of i is：I=1 ..., K,
Wherein, K is the total number of node to be tested；
Step 103-3) node Pi is selected from the set of test node to be selected, to the fault signature data set of node Pi
It carries out failure and sorts out calculating；
And according to the result of calculation of all test samples, the Fault Isolation group of test node Pi is calculatedWith failure every
From degree
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node PiIt is whether true, if equation meets, test node Pi is added to verification set N*, and be transferred to step 103-
4)；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1 is transferred to step 103-3)；Otherwise,
Test Pi is added to verification set N*, is transferred to step 103-3)；
Step 103-4) faulty, the then screening of optimal node set can be distinguished when the optimal test node of selection
Journey terminates.
Optionally, said program also obtains the value of the difference degree factor with the following method：
Define the inter- object distance d of i-th of test node jth class fault sampleijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；The meaning of j=1,2 ..., M, m and n are (m and n：Greatly
In 1 and be natural number)；N is number of samples, and K is test node total number, and M is failure classes total number, Pij(m),Pij(n) respectively
Indicate characteristic value of i-th of test point jth class failure for m-th and n-th sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D of the between class distance of M class of i-th of test pointi' be：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωμ and the ω class of i-th of test point are indicated respectively
N number of sample average value；
Define the difference degree α of test node iiFor：
αi=(D 'i/Di)·(min(Rbi)/max(Rwi)) (5)
Wherein, min (Rbi) and max (Rwi) indicate respectively between the infima species of i-th of test node sample data centrifugal pump and
Centrifugal pump in maximum kind.
Embodiment
The general frame of development approach that the present invention is studied includes：It realizes testing attribute configuration, circuitous pattern management, survey
Try node configuration, test logic is realized, virtual online debugging, on-line debugging executes, data preserve and the functions such as data-interface.
The specific implementation principle of the present invention is as shown in Figure 1：
Technical scheme of the present invention realize test configurations, circuit diagram management, test program (test program, below
Referred to as：TP) exploitation with execute, virtually with the functions such as on-line debugging, and have and know with the testing and diagnosing based on intelligent algorithm
The interface of knowledge.The basic procedure of method provided by the invention is as shown in Fig. 2, detailed process step includes：
1, testing attribute configures
Testing attribute configuration mainly includes the content of three aspects：Circuit interface attribute setting, test execution attribute configuration and
Test execution interface.
Foregoing circuit interface attributes are mainly used for describing the interface message of circuit, and the interface message of circuit includes circuit
The testability etc. of the internal test nodes of the connector node of interface and the interface of circuit；If test node belongs to connector section
Otherwise point uses manual test then using automatic test；And node configure link to can not test node carry out related letter
Breath prompts and probe pen testing attribute is forbidden to configure.
Test execution attribute mainly completes the configuration that circuit test executes type, for generating test logic example；Test
Execute type mainly and include functional test based on fault tree with diagnostic test, the classes such as the intelligent diagnostics reasoning based on diagnostic knowledge
Type.
The configuration at the interfaces UI when test execution interface is mainly completed to test execution, according to the existing exploitation sides TP
Method is completed, and test data, step are interacted with the node of circuit board schematic/PCB when emphasis is completion test.
2, circuitous pattern management
Circuitous pattern management belongs to the subfunction of exploitation configuration management, it is main complete the schematic diagram to institute's test circuit plate,
The management of PCB etc. is such as imported, is edited, attribute is arranged and preserves function.
Development approach has the compatibility to the mainstreams circuit design method output file such as Protel, Altium Designer
Ability can realize the secondary editor of circuit diagram progress generated to the above method, drafting, member such as schematic diagram by importeding into mode
The functions such as the drafting of component graphics symbol and movement.
Development approach have individual circuit diagram draw function, it can be achieved that test node generation and configuration, realize to figure
The attribute configuration function of shape element such as component, line etc..
3, test node configures
Test node configuration belongs to the subfunction of exploitation configuration management, the main category completed to needing circuit node to be tested
Property setting and the routing file of test node and test equipment generate.The attribute of test node includes mainly the test node
Test information description, test signal attribute, test equipment attribute and test logic attribute etc..Wherein, test logic attribute provides
This node and other nodes logical relation (sequence, select, recycle and redirect in one kind).
Test routing file is mainly used for describing the line relationship between the channel and test node of test equipment, can be used for
Subsequent test logic generates.By in the attribute configuration of automatically testing node, extracting corresponding test equipment and channel
Attribute automatically generates the routing file based on XML format.
4, test logic is realized
Test logic realizes that function belongs to the subfunction of exploitation configuration management, realizes configuration management and the logic of test logic
Preview function.This part includes that nodal community configuration information obtains, routing file obtains, optimal test node set is generated, patrolled
It collects to generate and realizes function with TP.
Nodal community configuration information obtains, main extraction test information description, test signal attribute etc.；Wherein, test letter
Breath description is for being described the information of current test node in the TP of generation；Test signal attribute is surveyed for practical to TP
The range of signal obtained in examination is judged.
Routing file obtains：The routing file generated based on nodal community configuration is read in, for establishing test equipment and survey
The software description relationship between node is tried, realizes the automatic test to connector node.
Optimal test node set generates：In order to reduce the quantity of manual test node, in addition to connector node
Manual test node optimize, build optimal test node set：
On the basis of considering the indexs such as Fault-Sensitive degree and Fault Isolation degree, research more comprehensively test point failure inspection
The optimization algorithm of ability integration weighting evaluation is surveyed, reaching keeps the minimum spacing between different faults fuzzy set big, and same fault set
Between maximum kind in closely spaced purpose.
Failure difference degree defines：
Regard each fault mode as failure classes, of all categories can distinguish is because failure classes are located at different response areas
Domain.Feature samples under the corresponding all kinds of fault modes of some test point, if smaller to of a sort average inter- object distance, no
Similar average between class distance is bigger, then the test point is stronger to the distinction of failure.In sample minimum between class distance it is big and most
The small sample of big inter- object distance, corresponding test point is strong to the discrimination of failure (alternatively referred to as sensitive to failure), i.e. failure
Difference degree is big.
Define the inter- object distance d of i-th of test point jth class fault sampleijFor
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；J=1,2 ..., M.N is number of samples, and K is test point
Number, M are failure classes number, Pij(m),Pij(n) i-th test point jth class failure is indicated respectively m-th and n-th of sample is special
Value indicative.
The average value Di of the inter- object distance of M class of i-th of test point is
The average value q of i-th of N number of sample of test point jth class failureij
The average value D of the between class distance of M class of i-th of test pointi' be
μ in formula, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωμ and the ω class N of i-th of test point are indicated respectively
The average value of a sample.
Define test point i difference degree αiFor
αi=(D 'i/Di)·(min(Rbi)/max(Rwi)) (5)
min(Rbi) and max (Rwi) centrifugal pump and maximum kind between the infima species of i-th of test point sample data are indicated respectively
Interior centrifugal pump.
αiSize reflect the complexity that i-th of test point classifies to M class failures, αiIt is bigger to indicate i-th of survey
Pilot is more sensitive to fault signature, and the ability for distinguishing failure is stronger.Test point to be selected is reset according to test point Sensitivity Factor
Sequence can ensure that optimal test point is preferentially selected in test point set, avoid test point from selecting blindness, reduce subsequent algorithm calculation amount.
Fault Isolation degree defines：
Fault Isolation degree characterization test point is that the test node after reordering is selected in optimal test to the separating capacity of failure
One important Rule of judgment of point set.
Candidate test node after reordering is denoted as Pi=(i=1,2 ..., K), M class fault modes are denoted as fault set
F={ F0, F1 ..., FM-1 } is closed, wherein F0 is non-failure conditions.It provides as follows：
1) if all fault samples are accurately identified under certain fault mode Fm in F, and to arbitrary under remaining fault mode
Fault sample is then provided there is no Fm is misdiagnosed as：It is a Fault Isolation of test point Pi
Group only includes an element Fm in the set；
If 2) the partial fault sample in fault mode Fm is misdiagnosed as failure Fn, remember that Fm and Fn belong to the one of node Pi
A failure ambiguity group, and be denoted as：If the part sample in Fm is misdiagnosed as fault mode Fn, Fq, then
Remember that Fm, Fn, Fq are a failure ambiguity group of node Pi, is denoted asAnd so on.
In defined above, m, n, q=0,1 ..., M-1；m≠n≠q.
Definition power set ρ (F) indication circuit failure collection F=F0, F1 ..., FM-1 }；For all events of test point Pi
Hinder the set of ambiguity group；For the set of all Fault Isolation groups of test point Pi.It is obtained according to above-mentioned definition：
Wherein, | | to take element (i.e. failure) number in set.
Define isolation.For test point Pi (i=1,2 ..., K) and M class fault modes, define its test point failure every
From degree
Obviously,
The Fault Isolation degree of all test points can be calculated using K arest neighbors (K-nearest-neighbor, KNN).
Test node optimization algorithm flow chart is as shown in Figure 1, be specially：
A. each test point difference degree factor to be selected is calculated, and carries out test point again by descending order according to its value
Sequence；
B. it is sky to initialize optimal test point set N*, and marks and wait for that the collection of preferred test node is combined into P=after reordering
{ P0, P1 ..., Pk } initializes i=1, i=1 ..., K；
C. test point Pi is selected, carrying out failure to the test point fault signature data set using KNN sorts out calculating.According to institute
The result of calculation for having test sample calculates the test point Fault Isolation groupWith Fault Isolation degree
D. the union isolation of set N* and test point Pi Fault Isolation groups are verifiedIt is whether true, if waited
Formula meets, then Pi is added to N*, goes to e；IfGive up Pi (i=i+1), goes to c；Otherwise, Pi is added to
N* goes to c；
E. test point can be isolated institute it is faulty, algorithm terminates.
By above-mentioned algorithm, failure difference degree, Fault Isolation degree, test point detection cost can be combined, and
The factors such as failure probability of occurrence are combined, optimal test node set is constructed.
Test logic generates and TP is realized：In node configuration, the test logic attribute of each node is configured；
By the test node after optimization according to the logical attribute and testing sequence configured, genesis sequence, selection are recycled or are redirected and patrol
Volume, further, construct the logic tree based on optimal test node set；Software generates four classes for above-mentioned logical relation
Logic software block, logic-based tree, it is established that TP.
By the way that the test node number in schematic diagram is dragged to the configuration that test logic configuring area realizes test logic, and
Relevant test logic criterion such as cycle-index, jump target etc. is configured.
5, virtual online is debugged
Online simulation debugging function when virtual online debugging function is mainly realized to ATE off-line states.Virtual online tune
When examination, TP operating statuses are completely identical as on-line debugging；Development approach provides the execution such as single step, continuous, section, breakpoint, annotation
Mode has the control modes such as operation, stopping, pause；Runnable interface has schematic diagram/PCB test nodes flicker, test information
The functions such as reading, test logic sequence display；Relevant information or reading are manually entered by commissioning staff when running to test equipment
The script information set in advance is taken, the simulation to device information is completed；, it can be achieved that patrolling test under pause or halted state
Volume, the adjustment function of test information etc..
6, on-line debugging executes
On-line debugging execution is almost the same with virtual online debugging function, but it is based on existing TP development approaches, realization pair
The control of ATE；When response data acquires, node data is all stored according to certain format.
By the TP being run multiple times, the configuration of diagnostic knowledge generation can be carried out in testing attribute configuration section, according to multiple
Conclusion, data, nodal information of operation etc. are automatically analyzed whether to have producible diagnostic knowledge and call when condition has and be examined
Disconnected knowledge module completes the generation of relevant knowledge, can prompt to complete testing and diagnosing according to correlation when on-line debugging executes.
It is parallel that wherein the 5th step and 6 steps, that is, virtual online debugging and on-line debugging, which execute the two steps,.
7, data preservation and data-interface
The data of development approach output include mainly TP data compatible with existing TP development approaches, circuit data, test
Data, exploitation configuration data, test logic data etc..Development approach provides and existing TP development approaches, diagnostic knowledge software mould
The compatible data-interface such as block, mainstream EDA environment, and can be used as multiple independent dynamic link libraries and called by other software.
Certain type circuit board in being equipped using certain type is developed as example based on the development approach, is saved to test therein
Point configuration is illustrated as follows：
The setting to the attribute for needing circuit node to be tested in the circuit is completed, includes mainly following 4 points：1, to surveying
The test information of examination node is described；2, test signal attribute is set；3, test equipment attribute；4, test logic attribute.Tool
Body is described as follows：
1, test information description is carried out to the circuit, include to the node number of circuit interior joint, to the company of related component
Relationship, test purpose, test equipment and possible test result is connect to be described respectively.It tests information and is directed to different test feelings
Border is divided into multigroup, is selected in different situations；
2, test signal attribute is set, the relevant interface based on signal testing is reserved.Based on instrument test, signal Analysis category
Property include mainly signal attribute under the test point normal condition, such as sinusoidal, parameter value such as voltage, frequency, duty ratio and respectively
The tolerance of parameter, and the tolerance function for the type signals type such as set TTL, CMOS, LVTTL.
3, test equipment attribute setup is carried out to the instrument of circuit interior joint test, includes mainly two category informations：Excitation
With acquisition instrument information and test routing iinformation.
4, test logic attribute mainly completes the setting of the logical relation between test node and upper lower node.
It is last that it should be noted that example described herein is only used for, explanation is of the invention, and the present invention does not limit concrete intelligence end
Type, class of service, the transformation done to the above content is held also to fall within the scope and spirit of the invention.
Claims (10)
1. a kind of board failure positioning system based on circuit network and graph search, which is characterized in that the system includes：
Test node attribute acquisition module, the attribute information for obtaining test node, the attribute information include：Circuit interface
Attribute and test execution attribute；
Routing file acquisition module, for obtaining routing file, the routing file is used to describe channel and the survey of test equipment
Try the line relationship between node；
Optimal node selecting module, for being screened to manual test node according to Fault Isolation degree parameter, and if then selecting
Dry node forms optimal test node set, wherein separating capacity of the Fault Isolation degree characterization test node to failure；
Test logic generation module, for generating the optimal node that screening obtains based on test node attribute information and routing file
Gather the test logic of interior joint, or generates based on test node attribute information and routing file the test of automatic test node and patrol
Volume；The wherein described test logic relationship includes：Sequentially, it selects, recycle or redirects；
Test result output module for being tested the test point of selection based on obtained test logic, and then completes electricity
The fault location of road plate.
2. the board failure positioning system according to claim 1 based on circuit network and graph search, which is characterized in that
The system also includes：
Configuration module, the testing attribute of the test node for inputting the circuit board under test needed to configure, the testing attribute packet
Contain：Circuit interface attribute and test execution attribute；
Routing file generation module, the attribute information for the test node based on input generate test node and test equipment
Routing file, wherein the routing file is used to describe the line relationship between the channel of test equipment and test node.
3. the board failure positioning system according to claim 1 based on circuit network and graph search, which is characterized in that
The system also includes：
Storage and interface module, for storing fault location result and providing the testing and diagnosing knowledge based on intelligent algorithm
Interface；
Image management module, importing, editor, attribute setting and guarantor for completing schematic diagram and PCB to institute's test circuit plate
It deposits.
4. the board failure positioning system according to claim 1 based on circuit network and graph search, which is characterized in that
The optimal node selecting module further includes：
First processing submodule, the difference degree factor for calculating each test node to be selected, and foundation obtains the difference degree factor
Value resequences test node to be selected by descending order；
Second processing submodule is sky for initializing optimal test node set N*, and marks the test to be selected after reordering
The collection of node is combined into P={ P1 ... ... PK }, wherein K is the total number of node to be tested；
Third handles submodule, and for selecting node Pi from the set of test node to be selected, the value of initiation parameter i is i
=1, the wherein value range of i is：I=1 ..., K carry out failure to the fault signature data set of test node Pi and sort out meter
It calculates；
And according to the result of calculation of all test samples, the Fault Isolation group IG of test node Pi is calculatedPiWith Fault Isolation degree
IDPi；
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node PiIt is
Test node Pi is added to set N*, and drive end submodule by no establishment if equation meets；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1, restarting third handle submodule into
Row processing；Otherwise, test Pi is added to set N*, opens third processing submodule；
Terminate submodule, optimal test node for judging when selection can distinguish faulty, then optimal node set
Screening process terminates.
5. the board failure positioning system according to claim 4 based on circuit network and graph search, which is characterized in that
The value of the difference degree factor is obtained with the following method：
First, the inter- object distance d of i-th of test node jth class fault sample is definedijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；J=1,2 ..., M, N are number of samples, and K is node to be tested
Total number, M be failure classes total number, Pij(m) and Pij(n) indicate i-th of test point jth class failure for m-th of He respectively
The characteristic value of n-th of sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D ' of the between class distance of M class of i-th of test pointiFor：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωThe N number of of μ and the ω classes of i-th of test point is indicated respectively
The average value of sample；
Then, it is based on above-mentioned parameter, defines the difference degree factor-alpha of test node iiCalculation formula be：
Wherein, min (Rbi) and max (Rwi) centrifugal pump and maximum between the infima species of i-th of test node sample data are indicated respectively
Centrifugal pump in class.
6. the board failure positioning system according to claim 4 based on circuit network and graph search, which is characterized in that
The Fault Isolation degree of test node Pi is obtained with the following method：
Candidate test node after reordering is denoted as Pi, M class fault modes are denoted as failure collection F={ F0,F1,…,FM-1,
Middle F0For non-failure conditions；It provides as follows：
1) if all fault samples are accurately identified under certain fault mode Fm in F, and to the Arbitrary Fault under remaining fault mode
The case where being misdiagnosed as Fm is not present in sample, then provides Fault Isolation group：It is a failure of test node Pi
Isolation group, and only include an element Fm in the failure collection；
If 2) the partial fault sample in fault mode Fm is misdiagnosed as failure Fn, remember that Fm and Fn belong to the one of test node Pi
A failure ambiguity group, and be denoted as：If the part sample in Fm is misdiagnosed as fault mode Fn and Fq, remember
Fm, Fn and Fq are a failure ambiguity group of test node Pi, are denoted asAnd so on；
Middle m, n, q=0,1 wherein defined above ..., M-1；m≠n≠q；
Definition power set ρ (F) indication circuit failure collection F=F0, F1 ..., FM-1 }；AGPiFor the faulty moulds of test node Pi
The set of paste group；IGPiFor test node Pi Fault Isolation groups；
It is obtained according to above-mentioned definition：
Wherein, | | to take element number, i.e. failure number in set；
Isolation is defined, for test node Pi and M class fault mode, the Fault Isolation degree for defining test node is：
IDPi=| IGPi| (7)
Obviously, 1≤IGPi≤M；
The Fault Isolation degree of all test nodes is calculated using K nearest neighbor algorithms.
7. a kind of board failure localization method based on circuit network and graph search, the method include：
Step 101) obtains the attribute information of test node, and the testing attribute includes：Circuit interface attribute and test execution category
Property；
Step 102) obtains routing file, and the routing file is used to describe the company between the channel of test equipment and test node
Line relationship；
Step 103) screens manual test node according to Fault-Sensitive degree and Fault Isolation degree parameter, and then selects several
A node forms optimal test node set：Wherein, separating capacity of the Fault Isolation degree characterization test point to failure；
Step 104) is generated based on test node attribute information and routing file and screens obtained optimal node set interior joint
Test logic, or generate based on test node attribute information and routing file the test logic of automatic test node；It is wherein described
Test logic includes：The logical relation includes：Sequentially, it selects, recycle or redirects；
Step 105) tests test node based on obtained test logic, and then completes the fault location of circuit board.
8. the board failure localization method according to claim 7 based on circuit network and graph search, which is characterized in that
Also include before the step 101)：
The testing attribute of the test node of the circuit board under test needed to configure is inputted, the testing attribute includes：Circuit interface category
Property and test execution attribute；
The attribute information of test node based on input generates the routing file of test node and test equipment, wherein the road
It is used to describe the line relationship between the channel of test equipment and test node by file.
9. the board failure localization method according to claim 7 based on circuit network and graph search, which is characterized in that
The step 103) further includes：
Step 103-1) calculate the difference degree factor of each test node to be selected, and according to obtain the value of the difference degree factor by from greatly to
Small sequence resequences test node to be selected；
Step 103-2) the optimal test node collection N* of initialization is sky, and the collection of the test node to be selected after reordering is marked to be combined into
P={ P1 ..., PK }, wherein K is the total number of node to be tested；
Step 103-3) node Pi is selected from the set of test node to be selected, while the value of initiation parameter i is i=1,
The value range of middle i is：I=1 ..., K carry out failure to the fault signature data set of node Pi and sort out calculating；
And according to the result of calculation of all test samples, the Fault Isolation group IG of test node Pi is calculatedPiWith Fault Isolation degree
IDPi；
Differentiate submodule, the union isolation of the Fault Isolation group for verifying set N* and test node Pi
It is whether true, if equation meets, test node Pi is added to set N*, and be transferred to step 103-4)；IfThe value for then giving up test node Pi and arrange parameter i is：I=i+1 is transferred to step 103-3)；Otherwise, it will survey
Examination Pi is added to set N*, is transferred to step 103-3)；
Step 103-4) when the optimal test node of selection faulty, the then screening process knot of optimal node set that can distinguish institute
Beam.
10. the board failure localization method according to claim 9 based on circuit network and graph search, feature exist
In, with the following method obtain the difference degree factor value：
Define the inter- object distance d of i-th of test node jth class fault sampleijFor：
Wherein, m, n=1,2 ..., N, m ≠ n；I=1,2 ..., K；J=1,2 ..., M；N is number of samples, and K is that test node is total
Number, M are failure classes total number, Pij(m),Pij(n) indicate i-th of test point jth class failure for m-th and n-th respectively
The characteristic value of sample；
The average value Di of the inter- object distance of M class of i-th of test node is：
The average value q of N number of sample of i-th of test node jth class failureij：
The average value D ' of the between class distance of M class of i-th of test pointiFor：
Wherein, μ, ω=1,2 ..., M, μ ≠ ω；qiμ,qiωThe N number of of μ and the ω classes of i-th of test point is indicated respectively
The average value of sample；
Define the difference degree factor-alpha of test node iiCalculation formula be：
Wherein, min (Rbi) and max (Rwi) centrifugal pump and maximum between the infima species of i-th of test node sample data are indicated respectively
Centrifugal pump in class.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000975.5A CN105652182B (en) | 2015-12-28 | 2015-12-28 | A kind of board failure positioning system and method based on circuit network and graph search |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000975.5A CN105652182B (en) | 2015-12-28 | 2015-12-28 | A kind of board failure positioning system and method based on circuit network and graph search |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105652182A CN105652182A (en) | 2016-06-08 |
| CN105652182B true CN105652182B (en) | 2018-10-02 |
Family
ID=56476966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511000975.5A Active CN105652182B (en) | 2015-12-28 | 2015-12-28 | A kind of board failure positioning system and method based on circuit network and graph search |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105652182B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106526460B (en) * | 2016-12-29 | 2019-06-04 | 北京航天测控技术有限公司 | A kind of fault localization method and device |
| CN111814289B (en) * | 2020-09-08 | 2020-12-22 | 成都同飞科技有限责任公司 | Water supply pipe network pipe burst analysis method and analysis system based on schema theory |
| CN116736091A (en) * | 2023-08-10 | 2023-09-12 | 湖南遥光科技有限公司 | Electronic system test point expansion method and system, and fault diagnosis method and system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4114093A (en) * | 1976-12-17 | 1978-09-12 | Everett/Charles, Inc. | Network testing method and apparatus |
| CN101533061A (en) * | 2009-04-09 | 2009-09-16 | 浙江大学 | Large power transmission network fault locating method based on sparse PMU configuration |
| CN101714184A (en) * | 2009-11-20 | 2010-05-26 | 北京航空航天大学 | Behavioral level modeling system for circuit board level electromagnetic compatible sensitivity |
| CN102520341A (en) * | 2011-12-05 | 2012-06-27 | 南京航空航天大学 | Analog circuit fault diagnosis method based on Bayes-KFCM (Kernelized Fuzzy C-Means) algorithm |
| CN102565623A (en) * | 2011-12-21 | 2012-07-11 | 北京交通大学 | Method and device for online fault search positioning of multi-branch complex distribution network |
| CN103728551A (en) * | 2013-01-30 | 2014-04-16 | 中国人民解放军海军航空工程学院 | Analog circuit fault diagnosis method based on cascade connection integrated classifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8161434B2 (en) * | 2009-03-06 | 2012-04-17 | Synopsys, Inc. | Statistical formal activity analysis with consideration of temporal and spatial correlations |
-
2015
- 2015-12-28 CN CN201511000975.5A patent/CN105652182B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4114093A (en) * | 1976-12-17 | 1978-09-12 | Everett/Charles, Inc. | Network testing method and apparatus |
| CN101533061A (en) * | 2009-04-09 | 2009-09-16 | 浙江大学 | Large power transmission network fault locating method based on sparse PMU configuration |
| CN101714184A (en) * | 2009-11-20 | 2010-05-26 | 北京航空航天大学 | Behavioral level modeling system for circuit board level electromagnetic compatible sensitivity |
| CN102520341A (en) * | 2011-12-05 | 2012-06-27 | 南京航空航天大学 | Analog circuit fault diagnosis method based on Bayes-KFCM (Kernelized Fuzzy C-Means) algorithm |
| CN102565623A (en) * | 2011-12-21 | 2012-07-11 | 北京交通大学 | Method and device for online fault search positioning of multi-branch complex distribution network |
| CN103728551A (en) * | 2013-01-30 | 2014-04-16 | 中国人民解放军海军航空工程学院 | Analog circuit fault diagnosis method based on cascade connection integrated classifier |
Non-Patent Citations (1)
| Title |
|---|
| 基于敏感度因子与故障隔离度的模拟电路测点选择;赵鹏等;《传感器与微系统》;20100630;第29卷(第6期);正文第80-83、86页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105652182A (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106529090B (en) | A kind of aerospace electron class Reliability Assessment method | |
| CN101173972B (en) | Method and apparatus for testing to determine minimum operating voltages in electronic devices | |
| CN109344905A (en) | A kind of transmission facility automatic fault recognition methods based on integrated study | |
| CN101169465B (en) | Iterative test generation and diagnostic method based on modeled and unmodeled faults | |
| CN105572572B (en) | Analog-circuit fault diagnosis method based on WKNN-LSSVM | |
| Boppana et al. | Multiple error diagnosis based on Xlists | |
| CN86101612A (en) | Area of computer aided fault isolation in the circuit board testing | |
| CN106650942B (en) | Fault diagnosis method based on electronic equipment testability model | |
| CN109324601A (en) | The test platform of robot controller or control system based on hardware in loop | |
| CN105652182B (en) | A kind of board failure positioning system and method based on circuit network and graph search | |
| CN102156255A (en) | A method of and an arrangement for testing connections on a printed circuit board | |
| CN113759200B (en) | Digital plug-in general automatic test system based on image processing | |
| CN107966648B (en) | A kind of embedded failure diagnosis method based on correlation matrix | |
| CN105334451A (en) | Boundary scanning and testing system | |
| CN106610462A (en) | Electronic system, system diagnostic circuit and operation method thereof | |
| CN105843744B (en) | Transformation relation preference grade sort method for concurrent program metamorphic testing | |
| CN101894073B (en) | Defect automatic positioning device based on control flow intersection and automatic positioning method thereof | |
| CN106526460B (en) | A kind of fault localization method and device | |
| CN105022864B (en) | A kind of system testing point choosing method that matrix is relied on based on extension | |
| Melgara et al. | Automatic Location of IC Design Errors Using Beam System. | |
| CN110008072A (en) | A kind of method and device of testing hard disk performance and programming count result | |
| WO2023110478A1 (en) | Method for automatically exploring states and transitions of a human machine interface (hmi) device | |
| CN115165332A (en) | Integrated design method and system for built-in test and comprehensive test of equipment | |
| CN115827353A (en) | Fault diagnosis method and device | |
| CN105487035B (en) | The verification method and device of FPGA border scanning systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |