CN114443530B - TileLink-based chip interconnection circuit and data transmission method - Google Patents

TileLink-based chip interconnection circuit and data transmission method Download PDF

Info

Publication number
CN114443530B
CN114443530B CN202210005373.2A CN202210005373A CN114443530B CN 114443530 B CN114443530 B CN 114443530B CN 202210005373 A CN202210005373 A CN 202210005373A CN 114443530 B CN114443530 B CN 114443530B
Authority
CN
China
Prior art keywords
data
module
tilelink
serdes
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210005373.2A
Other languages
Chinese (zh)
Other versions
CN114443530A (en
Inventor
虞致国
洪广伟
顾晓峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangnan University
Original Assignee
Jiangnan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangnan University filed Critical Jiangnan University
Priority to CN202210005373.2A priority Critical patent/CN114443530B/en
Publication of CN114443530A publication Critical patent/CN114443530A/en
Application granted granted Critical
Publication of CN114443530B publication Critical patent/CN114443530B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/36—Arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

The invention discloses a TileLink-based chip interconnection circuit and a data transmission method, and belongs to the technical field of chip interconnection. The interconnection circuit of the present invention includes: a transmitting end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip adopting TileLink buses, and the invention can solve the problem that multi-channel data cross-chip transmission cannot be carried out in the prior art by adding the modes of inter-channel arbitration and unifying data formats of all channels, and can flexibly configure a circuit structure according to TileLink buses data width; the serialization circuit is configured through parameterization, so that the interconnection circuit can adapt to SerDes with any interface width; by setting the priority in the arbitration circuit, the message is ensured not to enter a routing loop or a resource deadlock in the transmission process of the TileLink bus network, the occurrence of the bus deadlock phenomenon is avoided, and the chip interconnection structure and the data transmission method are greatly optimized.

Description

TileLink-based chip interconnection circuit and data transmission method
Technical Field
The invention relates to a TileLink-based chip interconnection circuit and a data transmission method, and belongs to the technical field of chip interconnection.
Background
In the coming late molar age, the chip advanced process gradually approaches the physical limit, and on the other hand, the design cost of the advanced process is also the water-rise ship height. Under the background, the SoC system is divided into a plurality of chips, and then the integral scheme advantages are formed through the inter-chip interconnection. How to implement the interconnection between chips and the data transmission between chips are important problems.
TileLink bus is a high-speed, low-latency, high-throughput, scalable on-chip bus designed specifically for RISC-V instruction set CPUs, for interfacing processor cores, caches, DMA and other devices. The TileLink bus supports all communication requirements from a single peripheral to a high throughput complex multi-peripheral, providing consistent access to any number of cached and non-cached masters.
The TileLink bus protocol defines 5 channels, each channel having the following direction and specific functions: a request is transmitted from the master device to the slave device to access the specified address range or to cache the data. Channel B: a request is transmitted from the slave device to the master device to access or write back data at an address cached by the master agent. Channel C: the request from the master to the slave, in response to channel B, is also used to spontaneously write back dirty cache data (DIRTIED CACHED DATA). Channel D: a data reply response or reply message is transmitted from the slave device to the master device to the original requester. Channel E: the final acknowledgement of the buffered block transmission from the original requester is transmitted from the master to the slave for serialization.
For a chip system based on TileLink bus design, no transmission method and architecture scheme capable of flexibly configuring a circuit structure to complete bus data across chips according to TileLink bus and SerDes transmission capability exist at present.
Patent CN113704151a (chip interconnection architecture and interconnection method based on TileLink bus) discloses an interconnection architecture and interconnection method based on TileLink bus, which solves the cross-chip interaction of TileLink bus data and serially transmits parallel TileLink bus data with large bit width in chip to another chip, but the complete TileLink bus comprises 5 channels, including normal access operation and cache consistency operation, and patent CN113704151a only solves the operation of basic access request which can be completed through A, D channels, but cannot solve the operation of cache consistency which needs complete 5 channels, and also cannot flexibly configure circuit structure according to the data transmission bit width of TileLink bus specific channels, channel data bit width and SerDes which need to be transmitted, so the current TileLink bus data cross-chip interconnection scheme also has the defects of incomplete bus channel, incomplete bus operation transmission, incapability of flexible configuration according to TileLink bus specific channels, channel data bit width and SerDes data transmission bit width.
Disclosure of Invention
The invention provides a chip interconnection circuit based on TileLink and a data transmission method, which aim to solve the problems that TileLink bus channels are incomplete, bus operation transmission is incomplete and a circuit structure cannot be flexibly configured according to a TileLink bus channel, channel data bit width and SerDes data transmission bit width which are specifically forwarded in the existing cross-chip transmission process.
A first object of the present invention is to provide a chip interconnection circuit based on TileLink, the interconnection circuit comprising: a transmitting end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt TileLink buses, the first chip and the second chip are connected, and the interconnection circuit realizes the inter-chip interconnection and data transmission of the first chip and the second chip;
The transmitting end comprises: a first TileLink deserializing module and a first Serdes control module; the first TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the first Serdes control module, and recovering the received deserializing data from the first Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the receiving end comprises: a second TileLink deserializing module and a second Serdes control module; the second TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the second Serdes control module, and recovering the received deserialized data from the second Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the first Serdes control module and the second Serdes control module are connected through serial differential lines.
Optionally, the first TileLink deserializing module includes: the device comprises a first channel arbitration module, a first data serialization module and a first data deserialization module; the first Serdes control module includes: a first data FIFO module, a first control module, a first SerDes module;
At the transmitting end, a plurality of channels in TileLink bus A, C, E are connected with the input of the first channel arbitration module; the output of the first channel arbitration module is connected with the input of the first data serialization module; the output of the first data serialization module is connected with a parallel data input port of the first SerDes module; the parallel data output port of the first SerDes module is connected with the data input of the first data FIFO module; the data output of the first data FIFO module is connected with the input of the first data deserializing module; the data quantity output port of the first data FIFO module is connected with the first control module; the first control module is connected with a control port of the first SerDes module; the output of the first data deserializing module is connected with a plurality of channels in the TileLink bus B, D;
The first channel arbitration module is used for arbitrating one channel of channel data for sending after unifying the data formats of a plurality of channels in TileLink buses A, C, E; the first data serialization module is used for serializing the arbitrated channel data according to the transmitting capacity of the first SerDes module; the first data FIFO module is used for caching the data output by the first SerDes module, outputting the data first in first out, and outputting the internal data quantity to the first control module; the first control module is used for controlling the flow of the first SerDes module according to the data quantity in the first FIFO module and controlling the working state of the first SerDes module; the first data deserializing module is used for recovering the serialized data into data of a TileLink bus corresponding channel; the first SerDes module is used for serially transmitting parallel data, receiving serial data from the receiving end and then parallelly outputting the serial data.
Optionally, the second TileLink deserializing module includes: the device comprises a second channel arbitration module, a second data serialization module and a second data deserialization module; the second Serdes control module includes: a second data FIFO module, a second control module, a second SerDes module;
At the receiving end, a plurality of channels in TileLink bus B, D are connected with the input of the second channel arbitration module; the output of the second channel arbitration module is connected with the input of the second data serialization module; the output of the second data serialization module is connected with the parallel data input port of the second SerDes module; the parallel data output port of the second SerDes module is connected with the data input of the second data FIFO module; the data output of the second data FIFO module is connected with the input of the second data deserializing module; the data quantity output port of the second data FIFO module is connected with the second control module; the second control module is connected with a control port of the second SerDes module; the output of the second data deserializing module is connected with a plurality of channels in the TileLink bus A, C, E;
the second channel arbitration module is used for arbitrating one channel of channel data for sending after unifying the data formats of a plurality of channels in TileLink buses B, D; the second data serialization module is used for serializing the arbitrated channel data according to the sending capacity of the second SerDes module; the second data FIFO module is configured to buffer data output by the second SerDes module, where the data is first in first out, and output the internal data amount to the second control module; the second control module is used for controlling the flow of the second SerDes module according to the data quantity in the second data FIFO module and controlling the working state of the second SerDes module; the second data deserializing module is used for recovering the serialized data into data of a TileLink bus corresponding channel; the second SerDes module is used for serially transmitting the parallel data, receiving the serial data from the transmitting end and then parallelly outputting the serial data.
Optionally, the first channel arbitration module and the second channel arbitration module arbitrate the data of the unified channel, and the arbitration policy adopts fixed priority arbitration.
Optionally, the first SerDes module and the second SerDes module support flow control and data CRC checking.
Optionally, a metal connection or a PCB connection or a signal line connection is adopted between the first chip and the second chip.
Optionally, between the TileLink bus and the first channel arbitration module, between the first channel arbitration module and the first data serialization module, between the first data serialization module and the first SerDes module, between the first data FIFO module and the first data deserialization module, between the first data deserialization module and the TileLink bus, between the first control module and the first SerDes module, a VALID and READY handshake mechanism is adopted to transmit data.
Optionally, a VALID and READY handshake mechanism is adopted between the second SerDes module and the second data serialization module, between the second data FIFO module and the second data deserialization module, between the second data deserialization module and TileLink bus, between the second data serialization module and TileLink bus, and between the second control module and the second SerDes module.
The second object of the present invention is to provide a chip interconnection data transmission method based on TileLink buses, wherein the data transmission method is implemented based on the chip interconnection circuit, and when a plurality of channels in a TileLink bus A, C, E in the first chip initiate requests, the method includes the following steps:
Step one: the first channel arbitration module in the first chip unifies the formats of the data of a plurality of channels in TileLink buses A, C, E, arbitrates the unified channels, and selects one channel of data to send;
The new data format is shown in table 1:
table 1TileLink bus channel unified data format
Step two: the first data serialization module serializes the selected data according to the parallel data input bit width of the first SerDes module;
step three: the first SerDes module serially transmits parallel data to the second chip;
Step four: after the second SerDes module of the second chip receives serial data, the second SerDes module outputs the data to the second data FIFO module in parallel;
step five: the second data FIFO module receives data in first out, outputs the received data to the second data deserializing module, and outputs the internal data quantity to the second control module;
step six: the second data deserializing module receives and reorganizes the data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the second chip; in this process, if the data amount in the second data FIFO module at the receiving end exceeds a preset value, the second control module controls the second SerDes module; and completing transmission of TileLink bus request messages between the first chip and the second chip once.
Optionally, in the data stream transmission process of the method, when a response message is returned through a plurality of channels in the TileLink bus B, D of the second chip, the method includes the following steps:
step one: the second channel arbitration module in the second chip unifies the formats of the data of a plurality of channels in TileLink bus B, D, arbitrates the channels after unifying the formats, and selects one path of data to send;
step two: the second data serialization module serializes the selected data according to the parallel data input bit width of the second SerDes module;
Step three: the second SerDes module serially transmits parallel data to the first chip;
step four: after the first SerDes module of the first chip receives serial data, the first SerDes module outputs the data to the first data FIFO module in parallel;
Step five: the first data FIFO module receives data in a first-in first-out mode, outputs the received data to the first data deserializing module, and outputs the internal data quantity to the first control module;
Step six: the first data deserializing module receives and reorganizes data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the first chip; in this process, if the data amount in the first data FIFO module of the transmitting end exceeds a preset value, the first control module controls the first SerDes module; and completing transmission of TileLink bus response messages between the first chip and the second chip once.
The invention has the beneficial effects that:
The invention solves the problem that the prior art cannot carry out multi-channel data cross-slice transmission by adding the inter-channel arbitration and unifying the data formats of all channels, so that an interconnection circuit can completely transmit all channel data and all operation types of TileLink buses, and the circuit structure is flexibly configured according to the TileLink bus data width;
the serialization circuit is configured through parameterization, so that the interconnection circuit can adapt to SerDes with any interface width;
By fixing the priority orders A < C < E and B < D among channels in the arbitration circuit, the priority is set to ensure that messages cannot enter a routing loop or resource deadlock in the transmission process of the TileLink bus network, the occurrence of bus deadlock is avoided, and the transmission process of messages among devices on all channels is kept as a directed acyclic graph.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a chip architecture of a transmitting end of an inter-chip interconnect circuit according to the present invention, wherein (a) is a schematic diagram of a first intra-chip architecture and (b) is a schematic diagram of a second intra-chip architecture.
Fig. 2 is a schematic diagram of the channels of TileLink bus.
Fig. 3 is a waveform diagram of TileLink bus completed one transmission.
Fig. 4 is an input/output waveform diagram of a sender channel arbitration module according to an embodiment of the invention.
Fig. 5 is an input/output waveform diagram of a transmitting-end data serializing module according to an embodiment of the present invention.
Fig. 6 is an input/output waveform diagram of a transmitting-end data deserializing module according to a first embodiment of the present invention.
Fig. 7 is an input/output waveform diagram of a receiver-side channel arbitration module according to an embodiment of the invention.
Fig. 8 is an input/output waveform diagram of a receiving-end data serializing module according to an embodiment of the present invention.
Fig. 9 is an input/output waveform diagram of a receiving end data deserializing module according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
In order to facilitate understanding of the technical scheme of the present application, the TileLink bus is first described as follows:
The TileLink bus contains A, B, C, D and E five channels as shown in fig. 3. Wherein A, D channels are necessary for performing access operation on the equipment, and particularly distinguishing operation types by using opcode signals; B. the C, E channels are optional to support cache coherency operations. The specific function of each channel is as follows, channel a: a request is transmitted to access the specified address range or to cache the data. Channel B: a request is transmitted to access or write back data at an address cached by the master agent. Channel C: in response to the request of channel B, also for spontaneously writing back dirty cache data (DIRTIED CACHED DATA). Channel D: a data reply response or reply message is transmitted to the original requester. Channel E: the final acknowledgement of the buffered block transmission from the original requester is transmitted for serialization.
Each piece of data transmitted on any of the 5 channels is referred to as a transmission. During transmission, an active transmission occurs when both the VALID and READY signals are high and there is a rising edge of the clock. For example, transmission occurs at T3 in fig. 4.
The transmission direction of the a channel is from the master device to the slave device, and the request message is sent to a specific address. The relevant information is shown in table 2.
TABLE 2 channel A Signal
Note that: and z: the bit width of the size field is 4 bits minimum; o: the number of bits required to distinguish the source (master) side; a: the bit width of the address is 32 bits minimum; w: data bus width in bytes.
The transmission direction of the B channel is from the slave device to the master device for sending a request message to the master agent holding a particular cache block. The relevant information is shown in table 3.
TABLE 3 channel B Signal
Note that: and z: the bit width of the size field is 4 bits minimum; o: the number of bits required to distinguish the source (master) side; a: the bit width of the address is 32 bits minimum; w: data bus width in bytes.
The direction of transmission of the C-channel is from the master to the slave for responding to the request message of channel B and also for spontaneously writing back dirty cache data (DIRTIED CACHED DATA). The relevant information is shown in table 4.
TABLE 4 channel C Signal
Note that: and z: the bit width of the size field is 4 bits minimum; o: the number of bits required to distinguish the source (master) side; a: the bit width of the address is 32 bits minimum; w: data bus width in bytes.
The direction of transmission of the D channel is from the slave to the master for a response to the channel a sent to the specific address request, as well as for a response to the channel C spontaneously written back. The relevant information is shown in table 5.
TABLE 5 channel D Signal
Note that: and z: the bit width of the size field is 4 bits minimum; o: the number of bits required to distinguish the source (master) side; i: distinguishing the number of bits required by the terminal (slave); w: data bus width in bytes.
The transmission direction of the E channel is from the master device to the slave device, carrying a response whether the channel D response message has been received. The relevant information is shown in table 6.
TABLE 6 channel E Signal
Note that: i: the number of bits required for the terminating (slave) end is differentiated.
Embodiment one:
The embodiment provides a chip interconnection circuit based on TileLink, the interconnection circuit includes: a transmitting end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt TileLink buses, the first chip and the second chip are connected, and the interconnection circuit realizes the inter-chip interconnection and data transmission of the first chip and the second chip;
The transmitting end comprises: a first TileLink deserializing module and a first Serdes control module; the first TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the first Serdes control module, and recovering the received deserializing data from the first Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the receiving end comprises: a second TileLink deserializing module and a second Serdes control module; the second TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the second Serdes control module, and recovering the received deserialized data from the second Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the first Serdes control module and the second Serdes control module are connected through serial differential lines.
Embodiment two:
The embodiment provides a chip interconnection circuit based on TileLink, which serially transmits data on a plurality of parallel channels of a TileLink bus through SerDes to complete data cross-chip transmission.
The interconnection architecture according to the present embodiment is shown in fig. 1 and fig. 2, where fig. 1 is a schematic diagram of a chip architecture of a transmitting end of an inter-chip interconnection circuit, and fig. 2 is a schematic diagram of a chip architecture of a receiving end of an inter-chip interconnection circuit; the interconnection architecture includes a transmitting end and a receiving end, the transmitting end is respectively arranged on a chip 1 adopting TileLink buses, the receiving end is arranged on a chip 2 adopting TileLink buses, txp of the chip 1 is connected with rxp of the chip 2, txn of the chip 1 is connected with rxn of the chip 2, rxp of the chip 1 is connected with txp of the chip 2, rxn of the chip 1 is connected with txn of the chip 2, and chip-to-chip interconnection and data transmission between the chip 1 and the chip 2 are realized.
The transmitting end comprises a channel arbitration module, a data serialization module, a data deserialization module, a control module, a data FIFO module and a SerDes module; the receiving end comprises a channel arbitration module, a data serialization module, a data deserialization module, a control module, a data FIFO module and a SerDes module; and the control module of the sending end, the data FIFO module and the SerDes module are the same as the control module of the receiving end, and the data FIFO module and the SerDes module are the same.
The connection situation of the transmitting end chip architecture of the interconnection architecture according to the present invention is shown in fig. 1, specifically, in the chip 1: the input of the transmitting end is connected with TileLink three channels of the bus A, C, E, and the output of the transmitting end is connected with two channels of the TileLink bus B, D.
In the transmitting end, the A, C, E channels are connected with the input of the channel arbitration module; the output of the channel arbitration module is connected with the input of the data serialization module; the output of the data serialization module is connected with a parallel input data port of the SerDes module; the parallel data output port of the SerDes module is connected with the input of the data FIFO module; the data output of the data FIFO module is connected with the input of the data deserializing module, and the data quantity output port of the data FIFO module is connected with the control module; the control module is connected with a control port of the SerDes module; the output of the data deserializing module is connected with the TileLink bus B, D two channels.
In the chip 2, as shown in fig. 2, the output of the receiving end is connected to three channels of the TileLink bus A, C, E, and the input of the receiving end is connected to two channels of the TileLink bus B, D.
In the receiving end, the B, D channels are connected with the input of the channel arbitration module; the output of the channel arbitration module is connected with the input of the data serialization module; the output of the data serialization module is connected with a parallel input data port of the SerDes module; the parallel data output port of the SerDes module is connected with the input of the data FIFO module; the data output of the data FIFO module is connected with the input of the data deserializing module, and the data quantity output port of the data FIFO module is connected with the control module; the control module is connected with a control port of the SerDes module; the output of the data deserializing module is connected with the TileLink bus A, C, E three channels.
In the transmitting end, the channel arbitration module is used for unifying the data formats of three channels of TileLink buses A, C, E, the unified formats are shown in table 1, then arbitrating the data of the three unified channels, and in order to avoid the occurrence of bus deadlock, the arbitration strategy adopts fixed priority arbitration, priority E > C > A, arbitrating out one channel of data and outputting the data to the data serialization module;
the data serialization module is used for serializing the arbitrated channel data according to the input data bit width of the SerDes module;
The data FIFO module is used for caching the data output by the SerDes module, outputting the data to the control module, and outputting the internal data quantity;
the control module is used for controlling the working state of the SerDes module and controlling the flow of the SerDes module according to the data quantity in the data FIFO module. The high threshold value and the low threshold value exist, when the data quantity in the data FIFO module reaches the high threshold value, the function of the SerDes module is stopped, but data in transmission still exists possibly, and the data FIFO module continues to receive; when the data amount in the data FIFO module is reduced to a low threshold value, the data transceiving function of the SerDes module is restarted.
The data deserializing module is used for recovering the serialized data into data of a TileLink bus corresponding channel;
the SerDes module is used for serially transmitting the parallel data, receiving the serial data of the opposite terminal and then outputting the serial data in parallel, supporting flow control and data CRC check.
In the receiving end, the channel arbitration module is used for unifying the data formats of two channels of TileLink bus B, D, the unified formats are shown in table 1, then arbitrating the data of the two unified channels, and in order to avoid the occurrence of bus deadlock, the arbitration strategy adopts fixed priority arbitration, the priority is D > B, and the data of one channel is arbitrated out and is output to the data serialization module;
According to the interconnection structure of this embodiment, in the receiving end, the data serialization module, the data deserialization module, the SerDes module, the data FIFO module, and the control module function the same as the data serialization module, the data deserialization module, the SerDes module, the data FIFO module, and the control module of the transmitting end.
Embodiment III:
The present embodiment provides a chip interconnection data transmission method based on TileLink bus, which is implemented based on the chip interconnection circuit in the second embodiment, and in the data stream transmission process of the method, when three channels of TileLink bus A, C, E in chip 1 initiate messages, the method includes the following steps:
Step one: the channel arbitration module in the chip 1 unifies the data of three channels of the TileLink bus A, C, E, and the new data format is shown in table 1, including chanId representing the channel from which the message is sent, opcode representing the channel message type, parameter representing parameter number, size representing the logarithm of the size of the carried data, source representing the source device ID, address representing the destination address of the operation, data representing the data carried by the message, corrupt representing whether the message carried the data has errors, union representing different additional data among the channels, last representing the last bit of the unified data. Then arbitrating the unified three channels, adopting fixed priority arbitration by an arbitration strategy, and selecting one channel of data for transmission, wherein the priority E > C > A is adopted by the arbitration strategy to avoid the occurrence of bus deadlock;
Step two: the data serialization module serializes the selected channel data according to the parallel data input bit width of the SerDes module;
step three: the SerDes module sends the parallel data to the chip 2 in series;
step four: after receiving serial data, the SerDes module of the chip 2 outputs bit width to the data FIFO module according to parallel data of the SerDes module;
step five: the data FIFO module receives data in first out, outputs the received data to the data deserializing module, and outputs the internal data quantity to the control module;
Step six: the data deserializing module receives and reorganizes the data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the chip 2; in the process, if the data quantity in the receiving end data FIFO module exceeds a preset value, the control module controls the SerDes module; the transmission of TileLink bus messages from chip 1 to chip 2 is completed once.
In the chip interconnection data transmission method of the present embodiment, when a message is transmitted to the chip 1 through two channels of the TileLink bus B, D of the chip 2, the method further includes the following steps:
Step one: the channel arbitration module in the chip 2 unifies the data of two channels of TileLink buses B, D, the new data format is shown in the table 1, then arbitrates the data of the two unified channels, and in order to avoid the occurrence of bus deadlock, the arbitration strategy adopts fixed priority arbitration, the priority D is greater than B, and one channel of data is selected for transmission;
Step two: the data serialization module serializes the selected channel data according to the parallel data input bit width of the SerDes module;
step three: the SerDes module serially transmits parallel data to the chip 1;
Step four: after receiving serial data, the SerDes module of the chip 1 outputs bit width to the data FIFO module according to parallel data of the SerDes module;
step five: the data FIFO module receives data in first out, outputs the received data to the data deserializing module, and outputs the internal data quantity to the control module;
Step six: the data deserializing module receives and reorganizes the data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the chip 1; in the process, if the data quantity in the data FIFO module of the transmitting end exceeds a preset value, the control module controls the SerDes module; the transmission of TileLink bus messages from chip 2 to chip 1 is completed once.
The interconnection architecture of the embodiment serially transmits the parallel TileLink bus data with the multichannel large bit width in the chip to another chip by adopting SerDes after the parallel TileLink bus data are serialized through arbitration, so that the use of chip pins can be reduced; and the clock is embedded in the data, so that the transmission path clock is not needed, and the problem that the data receiving end cannot correctly receive the data due to different propagation delays of the data and the clock is avoided.
The problem that multi-channel data cross-slice transmission cannot be carried out in the prior art is solved by adding the modes of inter-channel arbitration and unifying data formats of all channels, so that an interconnection circuit can completely transmit all channel data and all operation types of a TileLink bus, and a circuit structure is flexibly configured according to TileLink bus data width. The serialization circuit is configured through parameterization, so that the interconnection circuit can adapt to SerDes with any interface width. By fixing the priority orders A < C < E and B < D among channels in the arbitration circuit, the priority is set to ensure that messages cannot enter a routing loop or resource deadlock in the transmission process of the TileLink bus network, the occurrence of bus deadlock is avoided, and the transmission process of messages among devices on all channels is kept as a directed acyclic graph.
Some steps in the embodiments of the present invention may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (7)

1. A TileLink-based chip interconnect circuit, the interconnect circuit comprising: a transmitting end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt TileLink buses, the first chip and the second chip are connected, and the interconnection circuit realizes the inter-chip interconnection and data transmission of the first chip and the second chip;
The transmitting end comprises: a first TileLink deserializing module and a first Serdes control module; the first TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the first Serdes control module, and recovering the received deserializing data from the first Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the receiving end comprises: a second TileLink deserializing module and a second Serdes control module; the second TileLink deserializing module is used for carrying out format unification and deserializing processing on the received data from the TileLink bus, then sending the data to the second Serdes control module, and recovering the received deserialized data from the second Serdes control module into data of a corresponding channel of the TileLink bus and transmitting the data to the TileLink bus;
the first Serdes control module and the second Serdes control module are connected through a serial differential line;
The first TileLink deserializing module includes: the device comprises a first channel arbitration module, a first data serialization module and a first data deserialization module; the first Serdes control module includes: a first data FIFO module, a first control module, a first SerDes module;
At the transmitting end, a plurality of channels in TileLink bus A, C, E are connected with the input of the first channel arbitration module; the output of the first channel arbitration module is connected with the input of the first data serialization module; the output of the first data serialization module is connected with a parallel data input port of the first SerDes module; the parallel data output port of the first SerDes module is connected with the data input of the first data FIFO module; the data output of the first data FIFO module is connected with the input of the first data deserializing module; the data quantity output port of the first data FIFO module is connected with the first control module; the first control module is connected with a control port of the first SerDes module; the output of the first data deserializing module is connected with a plurality of channels in the TileLink bus B, D;
The first channel arbitration module is used for arbitrating one channel of channel data for sending after unifying the data formats of a plurality of channels in TileLink buses A, C, E; the first data serialization module is used for serializing the arbitrated channel data according to the transmitting capacity of the first SerDes module; the first data FIFO module is used for caching the data output by the first SerDes module, outputting the data first in first out, and outputting the internal data quantity to the first control module; the first control module is used for controlling the flow of the first SerDes module according to the data quantity in the first data FIFO module and controlling the working state of the first SerDes module; the first data deserializing module is used for recovering the serialized data into data of a TileLink bus corresponding channel; the first SerDes module is used for serially transmitting parallel data, receiving serial data from the receiving end and then parallelly outputting the serial data;
The second TileLink-deserializing module includes: the device comprises a second channel arbitration module, a second data serialization module and a second data deserialization module; the second Serdes control module includes: a second data FIFO module, a second control module, a second SerDes module;
At the receiving end, a plurality of channels in TileLink bus B, D are connected with the input of the second channel arbitration module; the output of the second channel arbitration module is connected with the input of the second data serialization module; the output of the second data serialization module is connected with the parallel data input port of the second SerDes module; the parallel data output port of the second SerDes module is connected with the data input of the second data FIFO module; the data output of the second data FIFO module is connected with the input of the second data deserializing module; the data quantity output port of the second data FIFO module is connected with the second control module; the second control module is connected with a control port of the second SerDes module; the output of the second data deserializing module is connected with a plurality of channels in the TileLink bus A, C, E;
The second channel arbitration module is used for arbitrating one channel of channel data for sending after unifying the data formats of a plurality of channels in TileLink buses B, D; the second data serialization module is used for serializing the arbitrated channel data according to the sending capacity of the second SerDes module; the second data FIFO module is configured to buffer data output by the second SerDes module, where the data is first in first out, and output the internal data amount to the second control module; the second control module is used for controlling the flow of the second SerDes module according to the data quantity in the second data FIFO module and controlling the working state of the second SerDes module; the second data deserializing module is used for recovering the serialized data into data of a TileLink bus corresponding channel; the second SerDes module is used for serially transmitting parallel data, receiving serial data from the transmitting end and then parallelly outputting the serial data;
And the first channel arbitration module and the second channel arbitration module arbitrate the unified channel data, and the arbitration strategy adopts fixed priority arbitration.
2. The chip interconnect circuit of claim 1, wherein the first SerDes module and the second SerDes module support flow control and data CRC checking.
3. The chip interconnect circuit of claim 1 wherein the first chip and the second chip are connected using a metal connection or a PCB connection or a signal line connection.
4. The chip interconnect circuit of claim 1 wherein data is transferred between the TileLink bus and the first lane arbitration module, between the first lane arbitration module and the first data serialization module, between the first data serialization module and the first SerDes module, between the first data FIFO module and the first data deserialization module, between the first data deserialization module and TileLink bus, between the first control module and the first SerDes module using a VALID, READY handshake mechanism.
5. The chip interconnect circuit of claim 1 wherein a VALID, READY handshake mechanism is employed between the second SerDes module and the second data serialization module, between the second data FIFO module and the second data deserialization module, between the second data deserialization module and TileLink bus, between the second data serialization module and TileLink bus, and between the second control module and the second SerDes module.
6. A chip interconnection data transmission method based on TileLink bus, wherein the data transmission method is implemented based on the chip interconnection circuit of claim 1, and when a plurality of channels in TileLink bus A, C, E in the first chip initiate a request, the method includes the following steps:
Step one: the first channel arbitration module in the first chip unifies the formats of the data of a plurality of channels in TileLink buses A, C, E, arbitrates the unified channels, and selects one channel of data to send;
step two: the first data serialization module serializes the selected data according to the parallel data input bit width of the first SerDes module;
step three: the first SerDes module serially transmits parallel data to the second chip;
Step four: after the second SerDes module of the second chip receives serial data, the second SerDes module outputs the data to the second data FIFO module in parallel;
step five: the second data FIFO module receives data in first out, outputs the received data to the second data deserializing module, and outputs the internal data quantity to the second control module;
step six: the second data deserializing module receives and reorganizes the data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the second chip; in this process, if the data amount in the second data FIFO module at the receiving end exceeds a preset value, the second control module controls the second SerDes module; and completing transmission of TileLink bus request messages between the first chip and the second chip once.
7. The method of claim 6, wherein the data stream transmission process of the method includes the following steps when a response message is transmitted back through a plurality of channels in TileLink bus B, D of the second chip:
step one: the second channel arbitration module in the second chip unifies the formats of the data of a plurality of channels in TileLink bus B, D, arbitrates the channels after unifying the formats, and selects one path of data to send;
step two: the second data serialization module serializes the selected data according to the parallel data input bit width of the second SerDes module;
Step three: the second SerDes module serially transmits parallel data to the first chip;
step four: after the first SerDes module of the first chip receives serial data, the first SerDes module outputs the data to the first data FIFO module in parallel;
Step five: the first data FIFO module receives data in a first-in first-out mode, outputs the received data to the first data deserializing module, and outputs the internal data quantity to the first control module;
Step six: the first data deserializing module receives and reorganizes data, and restores the data into a request message of a TileLink bus corresponding channel and outputs the request message to a TileLink bus in the first chip; in this process, if the data amount in the first data FIFO module of the transmitting end exceeds a preset value, the first control module controls the first SerDes module; and completing transmission of TileLink bus response messages between the first chip and the second chip once.
CN202210005373.2A 2022-01-05 2022-01-05 TileLink-based chip interconnection circuit and data transmission method Active CN114443530B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210005373.2A CN114443530B (en) 2022-01-05 2022-01-05 TileLink-based chip interconnection circuit and data transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210005373.2A CN114443530B (en) 2022-01-05 2022-01-05 TileLink-based chip interconnection circuit and data transmission method

Publications (2)

Publication Number Publication Date
CN114443530A CN114443530A (en) 2022-05-06
CN114443530B true CN114443530B (en) 2024-04-30

Family

ID=81366083

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210005373.2A Active CN114443530B (en) 2022-01-05 2022-01-05 TileLink-based chip interconnection circuit and data transmission method

Country Status (1)

Country Link
CN (1) CN114443530B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116450569B (en) * 2023-06-14 2023-08-15 苏州浪潮智能科技有限公司 Inter-chip interconnection system and data transmission method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102508808A (en) * 2011-11-14 2012-06-20 北京北大众志微系统科技有限责任公司 System and method for realizing communication of master chip and extended chip
CN109032973A (en) * 2018-07-09 2018-12-18 胡振波 ICB bus system and agreement
CN112866148A (en) * 2021-01-12 2021-05-28 之江实验室 Inter-chip data transmission architecture for brain-like computing chip and implementation method
CN113704151A (en) * 2021-08-19 2021-11-26 江南大学 Chip interconnection framework and interconnection method based on TileLink bus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102508808A (en) * 2011-11-14 2012-06-20 北京北大众志微系统科技有限责任公司 System and method for realizing communication of master chip and extended chip
CN109032973A (en) * 2018-07-09 2018-12-18 胡振波 ICB bus system and agreement
CN112866148A (en) * 2021-01-12 2021-05-28 之江实验室 Inter-chip data transmission architecture for brain-like computing chip and implementation method
CN113704151A (en) * 2021-08-19 2021-11-26 江南大学 Chip interconnection framework and interconnection method based on TileLink bus

Also Published As

Publication number Publication date
CN114443530A (en) 2022-05-06

Similar Documents

Publication Publication Date Title
US11481346B2 (en) Method and apparatus for implementing data transmission, electronic device, and computer-readable storage medium
US10802995B2 (en) Unified address space for multiple hardware accelerators using dedicated low latency links
JP4621604B2 (en) Bus device, bus system, and information transfer method
WO2005091812A2 (en) Pvdm (packet voice data module) generic bus protocol
EP2062147B1 (en) Method and apparatus for conditional broadcast of barrier operations
CN115248796B (en) Bus pipeline structure and chip for core-to-core interconnection
WO2023160192A1 (en) Interconnection apparatus for bus
CN111290986B (en) Bus interconnection system based on neural network
WO2021050763A1 (en) Methods and apparatus for network interface fabric send/receive operations
CN112306924A (en) Data interaction method, device and system and readable storage medium
US20210232520A1 (en) Logical physical layer interface specification support for pcie 6.0, cxl 3.0, and upi 3.0 protocols
CN114443530B (en) TileLink-based chip interconnection circuit and data transmission method
CN112988647A (en) TileLink bus-to-AXI 4 bus conversion system and method
US8090893B2 (en) Input output control apparatus with a plurality of ports and single protocol processing circuit
CN112882986B (en) Application method of many-core processor with supernode and supernode controller
KR100476895B1 (en) Interface device having variable data transfer mode and operating method thereof
CN113704151B (en) Chip interconnection architecture and interconnection method based on TileLink bus
CN115934625B (en) Doorbell knocking method, equipment and medium for remote direct memory access
KR100432701B1 (en) Method and apparatus for an improved interface between computer components
KR100475438B1 (en) Data bus system and method for performing cross-access between buses
CN115633098B (en) Storage management method and device of many-core system and integrated circuit
CN212541322U (en) Master-slave equipment interconnection system
CN113609067B (en) System for realizing 32-channel RS485 interface card
NL2029960B1 (en) Logical physical layer interface specification support for pcie 6.0, cxl 3.0, and upi 3.0 protocols
CN217157097U (en) Double-bus circuit for realizing multi-master priority control output

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: No. 1800 road 214122 Jiangsu Lihu Binhu District City of Wuxi Province

Applicant after: Jiangnan University

Address before: 214122 National University Science Park, Jiangnan University, No. 99 Jinxi Avenue, Binhu District, Wuxi City, Jiangsu Province

Applicant before: Jiangnan University

GR01 Patent grant