CN114443530A - Chip interconnection circuit based on TileLink and data transmission method - Google Patents

Chip interconnection circuit based on TileLink and data transmission method Download PDF

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CN114443530A
CN114443530A CN202210005373.2A CN202210005373A CN114443530A CN 114443530 A CN114443530 A CN 114443530A CN 202210005373 A CN202210005373 A CN 202210005373A CN 114443530 A CN114443530 A CN 114443530A
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data
module
tilelink
serdes
chip
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CN114443530B (en
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虞致国
洪广伟
顾晓峰
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Jiangnan University
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Jiangnan University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/36—Arbitration

Abstract

The invention discloses a chip interconnection circuit based on TileLink and a data transmission method, and belongs to the technical field of chip interconnection. The interconnection circuit of the present invention includes: a sending end and a receiving end; the sending end and the receiving end are respectively arranged in the first chip and the second chip which adopt the TiLELink bus, the invention can solve the problem that multi-channel data cross-chip transmission can not be carried out in the prior art by increasing the way of arbitration among channels and unifying the data formats of the channels, and can flexibly configure a circuit structure according to the data width of the TiLELink bus; the interconnection circuit can be adapted to SerDes with any interface width by parametrically configuring the serialization circuit; the priority is set in the arbitration circuit, so that the message can not enter a routing loop or be deadlocked by resources in the transmission process of the TiLELink bus network, the occurrence of the phenomenon of bus deadlock is avoided, and the chip interconnection structure and the data transmission method are greatly optimized.

Description

Chip interconnection circuit based on TileLink and data transmission method
Technical Field
The invention relates to a chip interconnection circuit based on TileLink and a data transmission method, and belongs to the technical field of chip interconnection.
Background
In the coming post-molarity era, the advanced process of the chip gradually approaches the physical limit, and on the other hand, the design cost of the advanced process is also rising. Under the background, the scheme that the SoC system is divided into a plurality of chips and then the chips are interconnected to form a whole is gradually superior. How to realize interconnection between chips and data transmission between chips are important problems.
The TileLink bus is a high-speed, low-delay, high-throughput and extensible on-chip bus specially designed for RISC-V instruction set CPUs and is used for connecting processor cores, caches, DMA and other equipment. The TileLink bus supports all communication needs from a single peripheral to a high throughput complex multi-peripheral, providing consistent access to any number of cached and non-cached masters.
The TileLink bus protocol defines 5 channels, the direction and specific function of each channel is as follows, channel a: a request is transmitted from the master device to the slave device to access a specified address range or to cache data. And (3) a channel B: the slave device transmits a request to the master device to access or write back data at an address cached by the master agent. And (3) a channel C: the channel B request is also used for autonomous write back of dirty cached data (dirty cached data) by the master to the slave in response. And a channel D: a data reply response or reply message is transmitted from the slave device to the master device to the original requester. And (3) a channel E: the final reply from the original requester's cache block transfer is transmitted by the master to the slave for serialization.
For a chip system designed based on a TileLink bus, at present, there is no transmission method and architecture scheme that can flexibly configure a circuit structure to complete bus data cross-chip transmission according to the TileLink bus and SerDes sending capabilities.
Patent CN113704151A (TileLink bus based chip interconnection architecture and interconnection method) discloses an interconnection architecture and interconnection method based on TileLink bus, which solves the cross-chip interaction of TileLink bus data and serially transmits parallel TileLink bus data with large bit width in a chip to another chip, but the complete TileLink bus comprises 5 channels including common access operation and cache consistency operation, and patent CN113704151A only solves the operation of basic access request which can be completed through A, D channels, cannot solve the operation of cache consistency requiring complete 5 channels, and cannot also flexibly configure the circuit structure according to the specific channel of TileLink bus, channel data bit width and SerDes data transmission bit width required to be transmitted, so the current TileLink bus data cross-chip interconnection scheme also has incomplete bus channel, incomplete bus operation transmission, incomplete bus channel, incomplete bus operation transmission, and data transmission according to the specific channel of TileLink bus, The channel data bit width and the SerDes data transmission bit width are flexibly configured.
Disclosure of Invention
The invention provides a chip interconnection circuit based on TileLink and a data transmission method, aiming at solving the problems that a TileLink bus channel is incomplete, bus operation transmission is incomplete and a circuit structure cannot be flexibly configured according to a specifically forwarded TileLink bus channel, channel data bit width and SerDes data transmission bit width in the existing cross-chip transmission process.
The first purpose of the invention is to provide a chip interconnection circuit based on TileLink, which comprises: a sending end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt a TileLink bus, the first chip and the second chip are connected, and the interconnection circuit realizes interconnection between the first chip and the second chip and data transmission;
the transmitting end comprises: the device comprises a first TileLink serialization deserializing module and a first Serdes control module; the first TiLELink serialization deserialization module is used for carrying out format unification and serialization processing on the received data from the TiLELink bus and then sending the data to the first Serdes control module, and is also used for restoring the received serialized data from the first Serdes control module into data of a channel corresponding to the TiLELink bus and transmitting the data to the TiLELink bus;
the receiving end includes: the second TileLink serialization deserializing module and the second Serdes control module; the second TiLELink serialization deserialization module is used for carrying out format unification and serialization processing on the received data from the TiLELink bus and then sending the data to the second Serdes control module, and is also used for restoring the received serialized data from the second Serdes control module into data of a channel corresponding to the TiLELink bus and transmitting the data to the TiLELink bus;
the first Serdes control module and the second Serdes control module are connected by a serial differential line.
Optionally, the first TileLink serialization deserialization module includes: the device comprises a first channel arbitration module, a first data serialization module and a first data deserializing module; the first Serdes control module comprises: the system comprises a first data FIFO module, a first control module and a first SerDes module;
at the transmitting end, a plurality of channels in a TileLink bus A, C, E are connected with the input of the first channel arbitration module; the output of the first channel arbitration module is connected with the input of the first data serialization module; the output of the first data serialization module is connected with the parallel data input port of the first SerDes module; the parallel data output port of the first SerDes module is connected with the data input of the first data FIFO module; the data output of the first data FIFO module is connected with the input of the first data deserializing module; the data quantity output port of the first data FIFO module is connected with the first control module; the first control module is connected with a control port of the first SerDes module; the output of the first data deserializing module is connected with a plurality of channels in the TileLink bus B, D;
the first channel arbitration module is used for arbitrating a channel of channel data to be sent after unifying the data formats of a plurality of channels in the TileLink bus A, C, E; the first data serialization module is used for serializing the arbitrated channel data according to the sending capability of the first SerDes module; the first data FIFO module is used for caching the data output by the first SerDes module, the data are input first and output first, and the internal data quantity is output to the first control module; the first control module is used for controlling the flow of the first SerDes module according to the data quantity in the first FIFO module and controlling the working state of the first SerDes module; the first data deserializing module is used for recovering the serialized data into data of a channel corresponding to the TileLink bus; and the first SerDes module is used for serially transmitting the parallel data, receiving the serial data from the receiving end and then parallelly outputting the serial data.
Optionally, the second TileLink serialization deserialization module includes: the second channel arbitration module, the second data serialization module and the second data deserializing module; the second Serdes control module comprises: the second data FIFO module, the second control module and the second SerDes module;
at the receiving end, a plurality of channels in the TileLink bus B, D are connected with the input of the second channel arbitration module; the output of the second channel arbitration module is connected with the input of the second data serialization module; an output of the second data serialization module is connected to a parallel data input port of the second SerDes module; the parallel data output port of the second SerDes module is connected with the data input of the second data FIFO module; the data output of the second data FIFO module is connected with the input of the second data deserializing module; the data quantity output port of the second data FIFO module is connected with the second control module; the second control module is connected with a control port of the second SerDes module; the output of the second data deserializing module is connected with a plurality of channels in the TileLink bus A, C, E;
the second channel arbitration module is used for arbitrating a channel of channel data to be sent after unifying the data formats of a plurality of channels in the TileLink bus B, D; the second data serialization module is used for serializing the arbitrated channel data according to the sending capability of the second SerDes module; the second data FIFO module is used for caching the data output by the second SerDes module, the data are input first and output first, and the internal data quantity is output to the second control module; the second control module is used for controlling the flow of the second SerDes module according to the data quantity in the second data FIFO module and controlling the working state of the second SerDes module; the second data deserializing module is used for recovering the serialized data into data of a channel corresponding to the TileLink bus; and the second SerDes module is used for serially transmitting the parallel data, receiving the serial data from the transmitting end and then parallelly outputting the serial data.
Optionally, the first channel arbitration module and the second channel arbitration module arbitrate data of the unified channel, and an arbitration policy adopts fixed priority arbitration.
Optionally, the first SerDes module and the second SerDes module support flow control and data CRC checking.
Optionally, the first chip and the second chip are connected by a metal connection, a PCB connection, or a signal line.
Optionally, data is transmitted between the TileLink bus and the first channel arbitration module, between the first channel arbitration module and the first data serialization module, between the first data serialization module and the first SerDes module, between the first data FIFO module and the first data deserializing module, between the first data deserializing module and the TileLink bus, and between the first control module and the first SerDes module by using VALID and READY handshake mechanisms.
Optionally, data is transmitted between the second SerDes module and the second data serialization module, between the second data FIFO module and the second data deserialization module, between the second data deserialization module and the TileLink bus, between the second data serialization module and the TileLink bus, and between the second control module and the second SerDes module by using VALID and READY handshake mechanisms.
A second object of the present invention is to provide a TileLink bus-based chip interconnection data transmission method, which is implemented based on the above chip interconnection circuit, and when a plurality of channels in the TileLink bus A, C, E in the first chip initiate requests, the method includes the following steps:
the method comprises the following steps: a first channel arbitration module in the first chip unifies the data formats of a plurality of channels in the TileLink bus A, C, E, arbitrates the plurality of unified channels, and selects one channel of data to send;
the new data format is shown in table 1:
table 1TileLink bus channel unified data format
Figure BDA0003456454850000041
Step two: the first data serialization module serializes the selected path of data according to the parallel data input bit width of the first SerDes module;
step three: the first SerDes module serially transmits parallel data to the second chip;
step four: after the second SerDes module of the second chip receives serial data, the second SerDes module outputs the data to the second data FIFO module in parallel;
step five: the second data FIFO module receives data in a first-in first-out mode, outputs the received data to the second data deserializing module and outputs the internal data quantity to the second control module;
step six: the second data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the second chip; in the process, if the data quantity in the second data FIFO module of the receiving end exceeds a preset value, the second control module controls the second SerDes module; and completing the transmission of the TileLink bus request message between the first chip and the second chip once.
Optionally, in the data stream transmission process of the method, when the response message is returned through a plurality of channels in the TileLink bus B, D of the second chip, the method includes the following steps:
the method comprises the following steps: a second channel arbitration module in the second chip unifies the formats of the data of the channels in the TileLink bus B, D, and then arbitrates the channels with unified formats to select one channel of data to send;
step two: the second data serialization module serializes the selected path of data according to the parallel data input bit width of the second SerDes module;
step three: the second SerDes module serially transmits parallel data to the first chip;
step four: after the first SerDes module of the first chip receives serial data, the first SerDes module outputs the data to the first data FIFO module in parallel;
step five: the first data FIFO module receives data in a first-in first-out mode, outputs the received data to the first data deserializing module and outputs the internal data quantity to the first control module;
step six: the first data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the first chip; in the process, if the data quantity in a first data FIFO module of the sending end exceeds a preset value, the first control module controls the first SerDes module; and completing the transmission of the TileLink bus response message between the first chip and the second chip once.
The invention has the beneficial effects that:
the invention solves the problem that multi-channel data cross-chip transmission can not be carried out in the prior art by increasing the way of arbitration among channels and unifying the data formats of all channels, so that an interconnection circuit can completely transmit all channel data and all operation types of a TiLELink bus, and the circuit structure is flexibly configured according to the data width of the TiLELink bus;
the SerDes with any interface width can be adapted to the interconnection circuit by parametrically configuring the serialization circuit;
the priority is set by fixing the priority sequence A < C < E and B < D among the channels in the arbitration circuit, so that the messages cannot enter a routing loop or be deadlocked by resources in the transmission process of the TileLink bus network, the occurrence of the phenomenon of bus deadlock is avoided, and the transmission process of the messages among the devices on all the channels is kept as a directed acyclic graph.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a chip architecture of a transmitting end of an inter-chip interconnection circuit according to the present invention, wherein (a) is a schematic diagram of a first chip architecture, and (b) is a schematic diagram of a second chip architecture.
Fig. 2 is a channel schematic of a TileLink bus.
Fig. 3 is a waveform diagram of the TileLink bus completing one transmission.
Fig. 4 is a waveform diagram of input and output of the channel arbitration module of the transmitting end according to an embodiment of the present invention.
Fig. 5 is a waveform diagram of input and output of the sending-end data serialization module in an embodiment of the present invention.
Fig. 6 is a waveform diagram of input and output of the sending-end data deserializing module according to an embodiment of the invention.
Fig. 7 is a waveform diagram of input and output of the arbitration module of the receiving end channel according to an embodiment of the present invention.
FIG. 8 is a waveform diagram of the input and output of the receiving end data serialization module in accordance with an embodiment of the present invention.
Fig. 9 is a waveform diagram of the input and output of the receiving-end data deserializing module according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
To facilitate understanding of the technical solution of the present application, the TileLink bus is first described as follows:
the TileLink bus contains A, B, C, D and E five channels as shown in fig. 3. A, D channel is necessary to carry out access operation to the device, and the operation type is distinguished by opcode signal; B. the C, E channel is optional to support cache coherency operations. The specific function of each channel is as follows, channel a: a request is transmitted to access a specified address range or to cache data. And (3) a channel B: a request is transmitted to access or write back data at an address cached by the master agent. And (3) a channel C: in response to channel B requests, it is also used to autonomously write back dirty cached data. And a channel D: a data reply response or reply message is transmitted to the original requester. And (3) a channel E: the final response from the original requester's cache block transmission is transmitted for serialization.
Each piece of data transmitted on any one of the above 5 channels is called a transmission. During transmission, an active transmission occurs when both VALID and READY signals are high and the clock has a rising edge. For example, transmission occurs at T3 in fig. 4.
The transmission direction of the A channel is from the master device to the slave device, and the A channel carries the request message and is sent to a specific address. The relevant information is shown in table 2.
TABLE 2 channel A Signal
Figure BDA0003456454850000061
Figure BDA0003456454850000071
Note: z: bit width of size field, minimum 4 bits; o: distinguishing the bit number required by a source (main) end; a: bit width of the address, minimum 32 bits; w: data bus width in bytes.
The transmission direction of the B-channel is from the slave to the master for sending a request message to the master agent holding a particular cache block. The relevant information is shown in table 3.
TABLE 3 channel B signals
Figure BDA0003456454850000072
Note: z: bit width of size field, minimum 4 bits; o: distinguishing the bit number required by a source (main) end; a: bit width of the address, minimum 32 bits; w: data bus width in bytes.
The transmission direction of the channel C is from the master device to the slave device, and is used for responding to the request message of the channel B and also for spontaneously writing back dirty cached data (dirty cached data). The relevant information is shown in table 4.
TABLE 4 channel C signals
Figure BDA0003456454850000073
Figure BDA0003456454850000081
Note: z: bit width of size field, minimum 4 bits; o: distinguishing the bit number required by a source (main) end; a: bit width of the address, minimum 32 bits; w: data bus width in bytes.
The direction of transfer for the D channel is from the slave to the master for responses sent to specific address requests by channel a and also for responses written back spontaneously by channel C. The relevant information is shown in table 5.
TABLE 5 channel D signals
Figure BDA0003456454850000082
Note: z: bit width of size field, minimum 4 bits; o: distinguishing the bit number required by a source (main) end; i: distinguishing the bit number required by the terminal (slave) end; w: data bus width in bytes.
The transmission direction of the E channel is from the master device to the slave device, and carries a response whether the channel D response message has been received. The relevant information is shown in table 6.
TABLE 6 channel E signals
Figure BDA0003456454850000083
Figure BDA0003456454850000091
Note: i: the number of bits required to distinguish the terminating (slave) end.
The first embodiment is as follows:
this embodiment provides a chip interconnect circuit based on TileLink, interconnect circuit includes: a sending end and a receiving end; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt a TileLink bus, the first chip and the second chip are connected, and the interconnection circuit realizes interconnection between the first chip and the second chip and data transmission;
the transmitting end comprises: the device comprises a first TileLink serialization deserializing module and a first Serdes control module; the first TiLELink serialization deserialization module is used for carrying out format unification and serialization processing on the received data from the TiLELink bus and then sending the data to the first Serdes control module, and is also used for restoring the received serialized data from the first Serdes control module into data of a channel corresponding to the TiLELink bus and transmitting the data to the TiLELink bus;
the receiving end includes: the second TileLink serialization deserializing module and the second Serdes control module; the second TiLELink serialization deserialization module is used for carrying out format unification and serialization processing on the received data from the TiLELink bus and then sending the data to the second Serdes control module, and is also used for restoring the received serialized data from the second Serdes control module into data of a channel corresponding to the TiLELink bus and transmitting the data to the TiLELink bus;
the first Serdes control module and the second Serdes control module are connected by a serial differential line.
Example two:
the embodiment provides a TileLink-based chip interconnection circuit, which serially sends data on a plurality of parallel channels of a TileLink bus through SerDes to complete cross-chip transmission of the data.
Fig. 1 and fig. 2 show an interconnection architecture according to this embodiment, where fig. 1 is a schematic diagram of a chip architecture at a transmitting end of an inter-chip interconnection circuit, and fig. 2 is a schematic diagram of a chip architecture at a receiving end of an inter-chip interconnection circuit; the interconnection framework comprises a sending end and a receiving end, wherein the sending end is respectively arranged on a chip 1 adopting a TiLELink bus, the receiving end is arranged on a chip 2 adopting the TiLELink bus, txp of the chip 1 is connected with rxp of the chip 2, txn of the chip 1 is connected with rxn of the chip 2, rxp of the chip 1 is connected with txp of the chip 2, rxn of the chip 1 is connected with txn of the chip 2, and therefore interconnection and data transmission between chips of the chip 1 and the chip 2 are achieved.
The sending end comprises a channel arbitration module, a data serialization module, a data deserializing module, a control module, a data FIFO module and a SerDes module; the receiving end comprises a channel arbitration module, a data serialization module, a data deserializing module, a control module, a data FIFO module and a SerDes module; and the control module, the data FIFO module and the SerDes module of the sending end are the same as the control module, the data FIFO module and the SerDes module of the receiving end.
Fig. 1 shows a connection situation of a sending-end chip architecture of an interconnect architecture according to the present invention, and specifically, in the chip 1: the input of the transmitting end is connected with three channels of a TileLink bus A, C, E, and the output of the transmitting end is connected with two channels of a TileLink bus B, D.
In the transmitting end, the A, C, E three channels are connected with the input of the channel arbitration module; the output of the channel arbitration module is connected with the input of the data serialization module; the output of the data serialization module is connected with the parallel input data port of the SerDes module; the parallel data output port of the SerDes module is connected with the input of the data FIFO module; the data output port of the data FIFO module is connected with the input of the data deserializing module, and the data quantity output port of the data FIFO module is connected with the control module; the control module is connected with a control port of the SerDes module; the output of the data deserializing module is connected with the two channels of the TileLink bus B, D.
As shown in fig. 2, in the chip 2, the output of the receiving end is connected to three channels of the TileLink bus A, C, E, and the input of the receiving end is connected to two channels of the TileLink bus B, D.
In the receiving end, the B, D two channels are connected with the input of the channel arbitration module; the output of the channel arbitration module is connected with the input of the data serialization module; the output of the data serialization module is connected with the parallel input data port of the SerDes module; the parallel data output port of the SerDes module is connected with the input of the data FIFO module; the data output port of the data FIFO module is connected with the input of the data deserializing module, and the data quantity output port of the data FIFO module is connected with the control module; the control module is connected with a control port of the SerDes module; and the output of the data deserializing module is connected with the three channels of the TileLink bus A, C, E.
In the sending end, the channel arbitration module is used for unifying the data formats of the three channels of the TileLink bus A, C, E, the unified formats are shown in table 1, then the data of the unified three channels are arbitrated, in order to avoid the occurrence of a bus deadlock phenomenon, the arbitration strategy adopts fixed priority arbitration, the priority E is greater than C and greater than A, and one channel of data is arbitrated and output to the data serialization module;
the data serialization module is used for serializing the arbitrated channel data according to the bit width of the input data of the SerDes module;
the data FIFO module is used for caching the data output by the SerDes module, the data is firstly input and firstly output, and the internal data quantity is output to the control module;
the control module is used for controlling the working state of the SerDes module and controlling the flow of the SerDes module according to the data quantity in the data FIFO module. When the data amount in the data FIFO module reaches the high threshold value, the function of the SerDes module is stopped, but the data in transmission may still exist, and the data FIFO module continues to receive; and when the data amount in the data FIFO module is reduced to a low threshold value, the data transceiving function of the SerDes module is restarted.
The data deserializing module is used for recovering the serialized data into data of a channel corresponding to the TiLELink bus;
and the SerDes module is used for serially transmitting the parallel data, receiving the serial data of the opposite end and then parallelly outputting the received serial data, and supporting flow control and data CRC check.
In the receiving end, the channel arbitration module is used for unifying the data formats of two channels of the TileLink bus B, D, the unified formats are shown in table 1, then the data of the two unified channels are arbitrated, in order to avoid bus deadlock, the arbitration strategy adopts fixed priority arbitration, the priority D is greater than B, and one channel of arbitrated channel data is output to the data serialization module;
according to the interconnect structure of this embodiment, in the receiving end, the data serialization module, the data deserialization module, the SerDes module, the data FIFO module, and the control module have the same functions as the data serialization module, the data deserialization module, the SerDes module, the data FIFO module, and the control module of the transmitting end.
Example three:
this embodiment provides a TileLink bus-based chip interconnection data transmission method, which is implemented based on the chip interconnection circuit in the second embodiment, and in the data stream transmission process of the method, when three channels of the TileLink bus A, C, E in the chip 1 initiate messages, the method includes the following steps:
the method comprises the following steps: the channel arbitration module in the chip 1 unifies data of three channels of the TileLink bus A, C, E, the new data format is shown in table 1, and the new data format includes a channel with chanId representing a source, opcode representing a channel message type, param representing a parameter code, size representing a logarithm of carrying data size, source representing a source device ID, address representing a target address of an operation, data representing data carried by a message, corrupt representing whether the data carried by the message has an error, units representing extra data different between channels, and last representing the last bit of unified data. Then, arbitrating the three unified channels, wherein in order to avoid the occurrence of a bus deadlock phenomenon, the arbitration strategy adopts fixed priority arbitration, the priority E is greater than C and greater than A, and one channel of channel data is selected for sending;
step two: the data serialization module serializes the selected channel data according to the parallel data input bit width of the SerDes module;
step three: the SerDes module serially sends the parallel data to the chip 2;
step four: after the SerDes module of the chip 2 receives the serial data, the serial data is output to a data FIFO module according to the parallel data output bit width of the SerDes module;
step five: the data FIFO module receives data in a first-in first-out mode, outputs the received data to the data deserializing module and outputs the internal data quantity to the control module;
step six: the data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the chip 2; in the process, if the data quantity in the data FIFO module of the receiving end exceeds a preset value, the control module controls the SerDes module; the TileLink bus message transmission from chip 1 to chip 2 is completed once.
In the chip interconnection data transmission method of this embodiment, when a message is transmitted to the chip 1 through two channels of the TileLink bus B, D of the chip 2, the method further includes the following steps:
the method comprises the following steps: the channel arbitration module in the chip 2 unifies the data of the two channels of the TileLink bus B, D, the new data format is shown in Table 1, then the unified data of the two channels are arbitrated, in order to avoid bus deadlock, the arbitration strategy adopts fixed priority arbitration, the priority D is greater than B, and one channel of channel data is selected for sending;
step two: the data serialization module serializes the selected channel data according to the parallel data input bit width of the SerDes module;
step three: the SerDes module serially sends the parallel data to the chip 1;
step four: after the SerDes module of the chip 1 receives the serial data, the serial data is output to a data FIFO module according to the parallel data output bit width of the SerDes module;
step five: the data FIFO module receives data in a first-in first-out mode, outputs the received data to the data deserializing module and outputs the internal data quantity to the control module;
step six: the data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the chip 1; in the process, if the data quantity in the data FIFO module of the sending end exceeds a preset value, the control module controls the SerDes module; the transmission of the TileLink bus message from chip 2 to chip 1 is completed once.
In the interconnection architecture of the embodiment, after multi-channel large-bit-width parallel TileLink bus data in a chip are serialized through arbitration, SerDes serial transmission is adopted to transmit the data to another chip, so that the use of chip pins can be reduced; and the clock is embedded in the data, and a channel associated clock does not need to be transmitted, so that the problem that a data receiving end cannot correctly receive the data due to different propagation delays of the data and the clock is avoided.
By increasing the way of arbitration among channels and unifying the data formats of all channels, the problem that multi-channel data cross-chip transmission cannot be carried out in the prior art is solved, all channel data and all operation types of the TiLELink bus can be completely transmitted by an interconnection circuit, and the circuit structure is flexibly configured according to the data width of the TiLELink bus. The serializing circuit is configured by parameterization, so that the interconnecting circuit can be adapted to SerDes with any interface width. The priority is set by fixing the priority sequence A < C < E and B < D among the channels in the arbitration circuit, so that the messages cannot enter a routing loop or be deadlocked by resources in the transmission process of the TileLink bus network, the occurrence of the phenomenon of bus deadlock is avoided, and the transmission process of the messages among the devices on all the channels is kept as a directed acyclic graph.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A chip interconnection circuit based on TileLink, characterized in that, the interconnection circuit includes: a sending terminal and a receiving terminal; the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt a TileLink bus, the first chip and the second chip are connected, and the interconnection circuit realizes interconnection between the first chip and the second chip and data transmission;
the transmitting end comprises: the device comprises a first TileLink serialization deserializing module and a first Serdes control module; the first TileLink serialization deserialization module is used for unifying formats of received data from a TileLink bus, performing serialization processing on the data, sending the data to the first Serdes control module, restoring the received serialized data from the first Serdes control module into data of a channel corresponding to the TileLink bus, and transmitting the data to the TileLink bus;
the receiving end includes: the second TileLink serialization deserializing module and the second Serdes control module; the second TiLELink serialization deserialization module is used for carrying out format unification and serialization processing on the received data from the TiLELink bus and then sending the data to the second Serdes control module, and is also used for restoring the received serialized data from the second Serdes control module into data of a channel corresponding to the TiLELink bus and transmitting the data to the TiLELink bus;
the first Serdes control module and the second Serdes control module are connected by a serial differential line.
2. The chip interconnect circuit of claim 1, wherein the first TileLink serialization deserialization module comprises: the device comprises a first channel arbitration module, a first data serialization module and a first data deserializing module; the first Serdes control module comprises: the system comprises a first data FIFO module, a first control module and a first SerDes module;
at the transmitting end, a plurality of channels in a TileLink bus A, C, E are connected with the input of the first channel arbitration module; the output of the first channel arbitration module is connected with the input of the first data serialization module; the output of the first data serialization module is connected with the parallel data input port of the first SerDes module; the parallel data output port of the first SerDes module is connected with the data input of the first data FIFO module; the data output of the first data FIFO module is connected with the input of the first data deserializing module; the data quantity output port of the first data FIFO module is connected with the first control module; the first control module is connected with a control port of the first SerDes module; the output of the first data deserializing module is connected with a plurality of channels in the TileLink bus B, D;
the first channel arbitration module is used for arbitrating a channel of channel data to be sent after unifying the data formats of a plurality of channels in the TileLink bus A, C, E; the first data serialization module is used for serializing the arbitrated channel data according to the sending capability of the first SerDes module; the first data FIFO module is used for caching the data output by the first SerDes module, the data are input first and output first, and the internal data quantity is output to the first control module; the first control module is used for controlling the flow of the first SerDes module according to the data quantity in the first FIFO module and controlling the working state of the first SerDes module; the first data deserializing module is used for recovering the serialized data into data of a channel corresponding to the TileLink bus; and the first SerDes module is used for serially transmitting the parallel data, receiving the serial data from the receiving end and then parallelly outputting the serial data.
3. The chip interconnect circuit of claim 2, wherein the second TileLink serialization deserialization module comprises: the second channel arbitration module, the second data serialization module and the second data deserializing module; the second Serdes control module comprises: the second data FIFO module, the second control module and the second SerDes module;
at the receiving end, a plurality of channels in the TileLink bus B, D are connected with the input of the second channel arbitration module; the output of the second channel arbitration module is connected with the input of the second data serialization module; an output of the second data serialization module is connected to a parallel data input port of the second SerDes module; the parallel data output port of the second SerDes module is connected with the data input of the second data FIFO module; the data output of the second data FIFO module is connected with the input of the second data deserializing module; the data quantity output port of the second data FIFO module is connected with the second control module; the second control module is connected with a control port of the second SerDes module; the output of the second data deserializing module is connected with a plurality of channels in the TileLink bus A, C, E;
the second channel arbitration module is used for arbitrating a channel of channel data to be sent after unifying the data formats of a plurality of channels in the TileLink bus B, D; the second data serialization module is used for serializing the arbitrated channel data according to the sending capability of the second SerDes module; the second data FIFO module is used for caching the data output by the second SerDes module, the data are input first and output first, and the internal data quantity is output to the second control module; the second control module is used for controlling the flow of the second SerDes module according to the data quantity in the second data FIFO module and controlling the working state of the second SerDes module; the second data deserializing module is used for recovering the serialized data into data of a channel corresponding to the TileLink bus; and the second SerDes module is used for serially transmitting the parallel data, receiving the serial data from the transmitting end and then parallelly outputting the serial data.
4. The chip interconnection circuit according to claim 3, wherein the first channel arbitration module and the second channel arbitration module arbitrate data of the unified channel, and an arbitration policy adopts fixed priority arbitration.
5. The chip interconnect circuit of claim 3, wherein the first and second SerDes modules support flow control and data CRC checks.
6. The chip interconnection circuit of claim 3, wherein the first chip and the second chip are connected by a metal connection, a PCB connection, or a signal line.
7. The chip interconnect circuit of claim 3, wherein data is transmitted between the TiLELink bus and the first channel arbitration module, between the first channel arbitration module and the first data serialization module, between the first data serialization module and the first SerDes module, between the first data FIFO module and the first data deserialization module, between the first data deserialization module and the TiLELink bus, and between the first control module and the first SerDes module using a VALID or READY handshake mechanism.
8. The chip interconnect circuit of claim 3, wherein a VALID, READY handshake mechanism is used to transmit data between the second SerDes module and the second data serialization module, between the second data FIFO module and the second data deserialization module, between the second data deserialization module and the TileLink bus, and between the second control module and the second SerDes module.
9. A TileLink bus-based chip interconnection data transmission method, characterized in that the data transmission method is implemented based on the chip interconnection circuit of claim 3, and when several channels in the TileLink bus A, C, E in the first chip initiate requests, the method comprises the following steps:
the method comprises the following steps: a first channel arbitration module in the first chip unifies the data formats of a plurality of channels in the TileLink bus A, C, E, arbitrates the plurality of unified channels, and selects one channel of data to send;
step two: the first data serialization module serializes the selected path of data according to the parallel data input bit width of the first SerDes module;
step three: the first SerDes module serially transmits parallel data to the second chip;
step four: after the second SerDes module of the second chip receives serial data, the second SerDes module outputs the data to the second data FIFO module in parallel;
step five: the second data FIFO module receives data in a first-in first-out mode, outputs the received data to the second data deserializing module and outputs the internal data quantity to the second control module;
step six: the second data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the second chip; in the process, if the data quantity in the second data FIFO module of the receiving end exceeds a preset value, the second control module controls the second SerDes module; and completing the transmission of the TileLink bus request message between the first chip and the second chip once.
10. The method for transmitting chip interconnection data according to claim 7, wherein during the data stream transmission process, when the response message is transmitted back through several channels in the TileLink bus B, D of the second chip, the method includes the following steps:
the method comprises the following steps: a second channel arbitration module in the second chip unifies the formats of the data of the channels in the TileLink bus B, D, and then arbitrates the channels with unified formats to select one channel of data to send;
step two: the second data serialization module serializes the selected path of data according to the parallel data input bit width of the second SerDes module;
step three: the second SerDes module serially transmits parallel data to the first chip;
step four: after the first SerDes module of the first chip receives serial data, the first SerDes module outputs the data to the first data FIFO module in parallel;
step five: the first data FIFO module receives data in a first-in first-out mode, outputs the received data to the first data deserializing module and outputs the internal data quantity to the first control module;
step six: the first data deserializing module receives and recombines the data, restores the data into a request message of a channel corresponding to the TiLELink bus and outputs the request message to the TiLELink bus in the first chip; in the process, if the data quantity in a first data FIFO module of the sending end exceeds a preset value, the first control module controls the first SerDes module; and completing the transmission of the TileLink bus response message between the first chip and the second chip once.
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