CN101415027B - Communication module based on HDLC protocol, and control method for data real time forwarding and storage - Google Patents
Communication module based on HDLC protocol, and control method for data real time forwarding and storage Download PDFInfo
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Abstract
The invention discloses a communication module based on an HDIC protocol and a method for controlling data real time transmitting and storage. The invention relates to a communication module realizing the data real time transmitting and storage function by the HDIC protocol and a logic control method thereof, so as to solve the problems that the nodes in the traditional data link do not have the capacity to process data and can not realize the nodes real time control or the data transmission and control between networks. The main controller of the invention controls the data transmission between an external synchronous interface and an internal bus interface according to an interruption signal; the external synchronous interface transmits the data between an external device and the main controller; the internal bus interface transmits the data between the main controller and the bus. In the invention, the functions of transmitting and storing data, non-conversion transmission and replacing transmission are embedded into the main controller to lead the communication module to have the function of data processing to meet various demands of data processing and realize the nodes real time control or the data transmission and control between the networks. The invention has the characteristics of faster processing speed and higher accuracy.
Description
Technical field
The present invention relates to a kind of FPGA/EPLD realized the communication module and the logic control method thereof of the real-time forwarding memory function of data belonging to communication technique field through the HDLC agreement as main control chip.
Background technology
Fast development along with the network storage and transfer of data, control technology; All there is every day lot of data to store on the internet and send; Bus and interface standard commonly used comprise PCI, AGP and PCI-E or the like; Its main advantage is exactly that message transmission rate is higher, and the highest PCI-E16X2.0 version can reach 10GB/s at present, can satisfy the low-speed device of appearance in the present and the future's certain hour and the demand of high-speed equipment.Great majority all are relaying and the forwardings of being accomplished data by the CPU Control Node based on the storage and the transmission equipment of bus at present, and node itself does not have the ability of deal with data, can not be implemented in node control in real time or inter-network data transmission and control.
HDLC (High-Level Data Link Control, High-Level Data Link Control) is a kind of at Synchronization Network transmitting data, bit-oriented data link layer protocol, and have following characteristics: agreement does not rely on any character set; But the data message transparent transmission is used to realize that " the 0 bit insertion " of transparent transmission is easy to the hardware realization; Support full-duplex communication, needn't just can send data continuously by wait acknowledge, the data link efficiency of transmission is higher; All Frames all adopt CRC check, and information frame is numbered, and can prevent that leak-stopping is received or repetition, and transmission reliability is high; The transmission controlled function is separated with processing capacity, has than big flexibility with than the perfect control function.Based on These characteristics,, HDLC is not applied in the storage and the forwarding field of control bus data though network design generally uses HDLC as data link control protocol.
Summary of the invention
The present invention does not have the ability of deal with data for the node itself in the solution conventional data link; Can not be implemented in the problem of node control in real time or inter-network data transmission and control, a kind of communication module and control method for data real time forwarding and storage based on the HDLC agreement is provided.Communication module of the present invention comprises with lower unit:
Master controller; Be used for and from the storage of any external sync interface and according to interrupt signal the data of storing sent to corresponding internal bus interface, also be used for the data of storing being sent to any external sync interface from the storage of internal bus interface and according to interrupt signal; Also be used for the data from any external sync interface are sent to another external sync interface arbitrarily, and simultaneously with the storage of sending or do not store;
A plurality of external sync interfaces, the data that are used for the autonomous controller in future send to corresponding external equipment, also are used for the data from external equipment are sent to master controller;
Internal bus interface, the data that are used for the autonomous controller in future send to bus, will be used for the data from bus are sent to master controller.
Control method for data real time forwarding and storage of the present invention may further comprise the steps:
Step 1, master controller is set Control Parameter according to the treatment type of the data that receive;
Step 2, master controller are based on said control parameter judgment data treatment type, and judged result is transmitting-receiving and storage data; Then execution in step three, and judged result is transmitted data for no conversion, and then execution in step seven; Judged result is replacement data and transmits that then execution in step ten;
Step 4, master controller will receive writing data into memory and according to sending interrupt signal said reception data sent to the external sync interface or the internal bus interface of appointment, return execution in step one then;
Whether the address that step 5, master controller judge to receive in the data is complementary with the address of memory, and judged result is for being, then execution in step six, and judged result is then returned execution in step one for denying;
Step 6, master controller receive described reception data, provide the reception interrupt signal after finishing receiving, and return step 1;
Step 7, master controller judge whether preserve to receive data, and judged result is for being, then execution in step eight, and judged result is for denying that then execution in step nine;
Step 8, master controller are preserved the reception data of transmitting when receiving data transmitting to the external sync interface of appointment or internal bus interface, preserve to provide no conversion forwarding interrupt signal and return execution in step one after accomplishing;
Step 9, master controller is transmitted the reception data to the external sync interface or the internal bus interface of appointment, and forwarding is returned execution in step one after accomplishing;
Step 10, master controller judge whether to replace the data of storage, and judged result is for being, then execution in step 11, and judged result is not for, and then execution in step nine;
Step 11; Master controller is according to the direction of data forwarding; External sync interface or internal bus interface to appointment are transmitted the reception data that the data that will store in the reception data replace with forwarding, provide replacement after forwarding is accomplished and transmit interrupt signal, and return execution in step one.
Beneficial effect: the present invention is based on FPGA and realize the HDLC agreement; Can make forwarding of data storage, no conversion transmit and replace forwarding capability through programming is embedded among the FPGA; Make individual node have data-handling capacity; And the function that communication module is possessed satisfies the various requirement of data processing, has realized in node control in real time or inter-network data transmission and control; Method of the present invention is divided into three processes by logic with data processing, and each process can both the independent process data, have the advantages that processing speed is very fast, accuracy is higher.
Description of drawings
Fig. 1 is the overall structure figure of communication module of the present invention; Fig. 2 is the flow chart of control method for data real time forwarding and storage of the present invention.
Embodiment
Embodiment one: referring to Fig. 1, this execution mode is by forming with lower unit:
Master controller 1; Be used for and from the storage of any external sync interface 2 and according to interrupt signal the data of storing sent to corresponding internal bus interface 3, also be used for the data of storing being sent to any external sync interface 2 from the storage of internal bus interface 3 and according to interrupt signal; Also be used for the data from any external sync interface 2 are sent to another external sync interface 2 arbitrarily, and simultaneously with the storage of sending or do not store;
A plurality of external sync interfaces 2, the data that are used for autonomous controller 1 in future send to corresponding external equipment 4, also are used for the data from external equipment 4 are sent to master controller 1;
The master controller 1 of this execution mode adopts FPGA/EPLD (belonging to the programmable logic device design); Write through VHDL or other FPGA design tool and to make it have three or three above ports: two or more synchronous 485 ports and a pci interface; Existing common data transmit-receive function (the transmitting-receiving memory space is variable, that can be provided with, also can Using P FGA external memory unit); Has real-time forwarding capability again; Can the data that a port receives not had conversion or have another port that passes through of conversion to transmit in real time; Can be in the process of transmitting according to user control command to selectively storage and replacement of data, concrete function is as follows:
1., as one independently communication module use, communications protocol satisfies the HDLC protocol specification.Module has two independently transceiver channels; The transmitting-receiving address of each passage is adjustable; The user can set a plurality of receiver addresses simultaneously, in receiving course if one of them address satisfy user's set point module and just begin to receive data, simultaneously with the storage that receives in the memory space of FPGA internal extended; Module produces and interrupts after each frame data finishes receiving; Pass to computer through pci interface, the user achieves a butt joint in interrupt routine and receives reading or other operations of data, and the concrete function of interrupt routine is write realization by the user; The transmission address is adjustable; The address of receiving equipment when the user can set each transmission data; Module can before the transmission data begin, send address information and receiving equipment matees; The receiving equipment of notice appointment prepares to receive data, and FPGA inside is similarly the transmission data and has expanded a memory space, and the data that the user will send before sending beginning are first written to memory space; Start after having write and send the continuous transmission that to accomplish data, all distribute until sending the memory space data.The transmitting-receiving process is all carried out CRC check, in the process that receives data, can provide sign to the CRC judged result of data, and the user judges the correctness that receives data through reading the CRC flag information, realizes the choice to data.The user need reset to flag information after reading the CRC flag information, and is convenient to receive the judgement of data next time.Two communication ports at this functional status lower module can be worked simultaneously, do not disturb each other.
2., has the no change forwarding capability; Use as forwarding card; In real time be transmitted to another external sync interface 2 from the data of any external sync interface 2 through the no conversion of B mouth (A mouth) with what A mouth (B mouth) received; Described A mouth and B mouth are two ports of master controller 1, are used for the storage and the forwarding of data.The user can set hold-over command in advance; Hold-over command is State_Save under the default conditions; Module can judge whether the data after the address byte are the hold-over command that the user sets in the process of transmitting, as satisfies the hold-over command that the user is provided with and then the data of the certain-length (being set at 2～256 bytes at present) after the hold-over command in the repeating process are preserved, and is saved among the RAM of FPGA internal extended; Storage finishes to produce interrupt signal; Be passed to computer through pci interface, the user can realize in interrupt routine that concrete processing procedure is realized by user program to preserving the processing of data.The data that store among the RAM can be according in each repeating process whether the storage real-time update being arranged; In the process that Updates Information, do not allow the user to read the data among the RAM; To guarantee that the data that provide are up-to-date valid data; Avoid the phenomenon that the data division updated portion is not upgraded occurring, lead to errors.Refresh Data is realized through adopting the secondary storage mode among the RAM; The data that module is preserved in repeating process at first are saved in the array; Judge do not have new data to preserve in module; When simultaneously the user does not need the reading and saving data, module automatically with the storage in the array to RAM, accomplish refreshing of a secondary data.Refresh process 30ns after one group of valid data storage is accomplished begins; If the user is reading the previous frame stored valid data when storage is accomplished; Then module can be waited for after the user accomplishes read operation and refreshing, and module can not respond the order of user's reading of data in the refresh process.In the process of transmitting; The port that receives data can provide the CRC check sign after receiving frame data, so that judge that receiving data has or not error code, makes things convenient for computer that the house of data is got; When data when transmit the another port; Module can not carried out CRC check again, does not just have conversion to the CRC check sign indicating number that receives and transmits, and realizes that the no conversion between two ports is transmitted.
3., realize the replacement and the forwarding capability of data, will transmit data simultaneously and store according to customer requirements.Replacement is transmitted has this function when having only the data from external sync interface 2 that the A mouth is received to send to another external sync interface 2 through the B mouth.Before replacement was carried out, the user needed write replacement data to module in advance, the FPGA internal extended RAM of 48 bytes be used to store the replacement data that the user sets; For guaranteeing the real-time of replacement data, the user can change replacement data at any time, and module can refresh the replacement data of user's change to RAM in real time; This realization process adopts the mode of secondary storage to realize equally, and the user is at first with in the expansion RAM in the replacement data writing module, when the user writes completion and do not carry out replacement operation simultaneously; Module is automatically with among Refresh Data to the predefined array; Do not respond the replacement order in the refresh process, to guarantee the true validity of replacement data, the time of refreshing is very short; And when being in module and receiving the CRC check sign indicating number, the possibility that therefore can not exist new replacement operation to carry out.The user can set position and the length that is replaced data; Be that 48 byte datas after the replacement order are divided into four groups at present, every group of 12 bytes, the user can set which group of each replacement or which group; Under default situations, be not replace, realize no conversion forwarding.In the process of transmitting; As satisfying the replacement order; Module can be stored the original data message that is replaced of 50 bytes after the replacement order automatically to the inner ram space of FPGA; Produce after storage is accomplished and interrupt, the user can operate the storage data in interrupt routine, and interrupt routine is write based on actual demand by the user.The user can also be provided with the replacement order in advance, and the replacement order can be 16 and 8 two kinds according to customer requirements, and default conditions are 8, and command code is 0x00, and the length and the content user of replacement order can be set arbitrarily.The A mouth is after the matching addresses success; At first the length of the replacement order of judges setting is a byte or two bytes; Length according to the user sets judges whether one or two data byte after the address byte is the replacement order that the user sets, and satisfies after the replacement order position and the length of the replacement data that judges is set; Be replaced data and replace with setting data after will replacing order according to customer requirements; And the new array that replacement is accomplished carried out CRC check, and generates new CRC check sign indicating number, guarantee the verification property of forwarding data.The data that the B mouth receives will not have the real-time forwarding of conversion to the A mouth, and its implementation is with 2. identical.
When having a plurality of port, satisfy between arbitrary port and transmit, only need a direction register be set for each port; Data represented the number of transmitting port in the direction register is an example with eight ports, and the 1-8 data in the direction register have just been represented the number of transmitting port respectively; When the data in the direction register are 1; Just represent by the port of the data that receive and transmit to 1 port, the process of transmitting and replacing can not occur in the direction register and the identical data of reception data terminal slogan with noted earlier identical certainly; Because same port can not be received and dispatched use simultaneously; When the number of port becomes for a long time, the same length that only needs to change the direction register makes it can represent that maximum portal number is promptly passable.In the process of using, need confirm routing direction and the number of transmitting port in advance, write the Inbound register then, thereby determine routing direction through the portal number in the judgement direction register in the integrated circuit board course of work.
Embodiment two: this execution mode further defines said master controller 1 and also is used for according to giving up the overtime data from internal bus interface 3 or any external sync interface 2 break period of setting on the basis of embodiment one.
Be provided with a timer in the master controller 1, the user can be provided with timing, and timing length is 10～100ms, and step-length is 10～200 μ s, and timing accuracy is superior to 10
-6S, overtime meeting produces interrupt signal.The user can be provided with timing in communication or repeating process, for the system that real-time is had relatively high expectations, can give up the data message of overtime transmitting-receiving through timer.The user can also realize resetting and be provided with timer in interrupt routine.
Embodiment three: referring to Fig. 2, the control method for data real time forwarding and storage of this execution mode is made up of following steps:
Step 1, master controller 1 is set Control Parameter according to the treatment type of the data that receive;
Step 2, master controller 1 are based on said control parameter judgment data treatment type, and judged result is transmitting-receiving and storage data; Then execution in step three, and judged result is transmitted data for no conversion, and then execution in step seven; Judged result is replacement data and transmits that then execution in step ten;
Step 4, master controller 1 will receive writing data into memory and according to sending interrupt signal said reception data sent to the external sync interface 2 or the internal bus interface 3 of appointment, return execution in step one then;
Step 5, master controller 1 judge that whether the address that receives in the data is complementary with the address of memory, and judged result is for being, then execution in step six, and judged result is then returned execution in step one for denying;
Step 6, master controller 1 receives described reception data, provides the reception interrupt signal after finishing receiving, and returns step 1;
Step 7, master controller 1 judge whether preserve to receive data, and judged result is for being, then execution in step eight, and judged result is for denying that then execution in step nine;
Step 8, master controller 1 are preserved the reception data of transmitting when receiving data transmitting to the external sync interface 2 of appointment or internal bus interface 3, preserve to provide no conversion forwarding interrupt signal and return execution in step one after accomplishing;
Step 9, master controller 1 is transmitted the reception data to the external sync interface 2 or the internal bus interface 3 of appointment, and forwarding is returned execution in step one after accomplishing;
Step 10, master controller 1 judges whether to replace the data of storage, and judged result is for being, and then execution in step 11, and judged result is not for, and then execution in step nine;
Step 11; Master controller 1 is according to the direction of data forwarding; External sync interface 2 or internal bus interface 3 to appointment are transmitted the reception data that the data that will store in the reception data replace with forwarding, provide replacement after forwarding is accomplished and transmit interrupt signal, and return execution in step one.
Claims (3)
1. based on the communication module of HDLC agreement, it is characterized in that it comprises with lower unit:
Master controller (1); Be used for and from the storage of any external sync interface (2) and according to interrupt signal the data of storing sent to corresponding internal bus interface (3), also be used for the data of storing being sent to any external sync interface (2) from the storage of internal bus interface (3) and according to interrupt signal; Also be used for the data from any external sync interface (2) are sent to another external sync interface (2) arbitrarily, and simultaneously with the storage of sending or do not store;
A plurality of external sync interfaces (2), the data that are used for autonomous controller in future (1) send to corresponding external equipment (4), also are used for the data from external equipment (4) are sent to master controller (1);
Internal bus interface (3), the data that are used for autonomous controller in future (1) send to bus (5), will be used for the data from bus (5) are sent to master controller (1);
Master controller (1) adopts programmable logic device, writes to make it have three or three above ports two or more synchronous 485 ports and a pci interface through VHDL or other FPGA design tool; Existing common data transmit-receive function; Has real-time forwarding capability again; The data that a port receives are not had conversion or have another port that passes through of conversion to transmit in real time, in the process of transmitting, according to user control command data are selectively stored and replacement, concrete function is as follows:
1., as one independently communication module use, communications protocol satisfies the HDLC protocol specification; Module has two independently transceiver channels; The transmitting-receiving address of each passage is adjustable; The user sets a plurality of receiver addresses simultaneously, in receiving course if one of them address satisfy user's set point module and just begin to receive data, simultaneously with the storage that receives in the memory space of FPGA internal extended; Module produces and interrupts after each frame data finishes receiving; Pass to computer through pci interface, the user achieves a butt joint in interrupt routine and receives the read operation of data, and the concrete function of interrupt routine is write realization by the user; The transmission address is adjustable; The address of receiving equipment when the user sets each transmission data, module can be sent address information with receiving equipment matees before beginning sending data, and the receiving equipment of notice appointment is prepared the reception data; FPGA inside is similarly the transmission data and has expanded a memory space; The data that the user will send before sending beginning are first written to memory space, start after having write to send the continuous transmission that can accomplish data, all distribute until sending the memory space data; The transmitting-receiving process is all carried out CRC check, in the process that receives data, can provide sign to the CRC judged result of data, and the user judges the correctness that receives data through reading the CRC flag information, realizes the choice to data; The user need reset to flag information after reading the CRC flag information, and is convenient to receive the judgement of data next time; Two communication ports at this functional status lower module are worked simultaneously, do not disturb each other;
2., has the no change forwarding capability; Use as forwarding card; In real time be transmitted to another external sync interface (2) from the data of any one external sync interface (2) through what the B mouth did not have a conversion with what the A mouth received; Described A mouth and B mouth are two ports of master controller (1), are used for the storage and the forwarding of data; The user sets hold-over command in advance; Hold-over command is State_Save under the default conditions; Module can judge whether the data after the address byte are the hold-over command that the user sets in the process of transmitting, as satisfies the hold-over command that the user is provided with and then the data of the certain-length after the hold-over command in the repeating process are preserved, and is saved among the RAM of FPGA internal extended; Storage finishes to produce interrupt signal; Be passed to computer through pci interface, the user realizes that in interrupt routine concrete processing procedure is realized by user program to preserving the processing of data; The data that store among the RAM can be based on whether the storage real-time update is arranged in each repeating process; In the process that Updates Information, do not allow the user to read the data among the RAM; To guarantee that the data that provide are up-to-date valid data; Avoid the phenomenon that the data division updated portion is not upgraded occurring, lead to errors; Refresh Data is realized through adopting the secondary storage mode among the RAM; The data that module is preserved in repeating process at first are saved in the array; Judge do not have new data to preserve in module; When simultaneously the user does not need the reading and saving data, module automatically with the storage in the array to RAM, accomplish refreshing of a secondary data; Refresh process 30ns after one group of valid data storage is accomplished begins; If the user is reading the previous frame stored valid data when storage is accomplished; Then module can be waited for after the user accomplishes read operation and refreshing, and module can not respond the order that the user reads data in the refresh process; In the process of transmitting; The port that receives data can provide the CRC check sign after receiving frame data, so that judge that receiving data has or not error code, makes things convenient for computer that the house of data is got; When data when transmit the another port; Module can not carried out CRC check again, just the CRC check sign indicating number that receives is not had conversion and transmits, and realizes that the no conversion between two ports is transmitted;
3., realize the replacement and the forwarding capability of data, will transmit data simultaneously and store according to customer requirements; Replacement is transmitted has this function when having only the data from external sync interface (2) that the A mouth is received to send to another external sync interface (2) by the B mouth; Before replacement was carried out, the user needed write replacement data to module in advance, the FPGA internal extended RAM of 48 bytes be used to store the replacement data that the user sets; For guaranteeing the real-time of replacement data, the user changes replacement data at any time, and module can refresh the replacement data of user's change to RAM in real time; This realization process adopts the mode of secondary storage to realize equally, and the user is at first with in the expansion RAM in the replacement data writing module, when the user writes completion and do not carry out replacement operation simultaneously; Module is automatically with among Refresh Data to the predefined array; Do not respond the replacement order in the refresh process, to guarantee the real-time effectiveness of replacement data, the time of refreshing is very short; And when being in module and receiving the CRC check sign indicating number, the therefore possibility that can not exist new replacement operation to carry out; User's setting is replaced the position and the length of data, is at present replacement order 48 byte datas afterwards are divided into four groups, and every group of 12 bytes, the user sets which group of each replacement or which group, under default situations, is not replace, and realizes no conversion forwarding; In the process of transmitting; As satisfying the replacement order; Module can be stored the original data message that is replaced of 50 bytes after the replacement order automatically to the inner ram space of FPGA; Produce after storage is accomplished and interrupt, the user operates the storage data in interrupt routine, and interrupt routine is write by the user according to the actual requirements; The user also is provided with the replacement order in advance, and the replacement order is 16 and 8 two kinds according to customer requirements, and default conditions are 8, and command code is 0x00, and the length and the content user of replacement order are set arbitrarily; The A mouth is after the matching addresses success; At first the length of the replacement order of judges setting is a byte or two bytes; Length according to the user sets judges whether one or two data byte after the address byte is the replacement order that the user sets, and satisfies after the replacement order position and the length of the replacement data that judges is set; Be replaced data and replace with setting data after will replacing order according to customer requirements; And the new array that replacement is accomplished carried out CRC check, and generates new CRC check sign indicating number, guarantee the verification of forwarding data; The data that the B mouth receives will not have the real-time forwarding of conversion to the A mouth, and its implementation is with 2. identical;
When having a plurality of port, between arbitrary port, transmit, for each port is provided with a direction register; Data represented the number of transmitting port in the direction register is provided with eight ports, and the 1-8 data in the direction register have just been represented the number of transmitting port respectively; When the data in the direction register are 1; Just represent by the port of the data that receive and transmit to 1 port, the process of transmitting and replacing can not occur in the direction register and the identical data of reception data terminal slogan with noted earlier identical certainly; Because same port can not be received and dispatched use simultaneously; When the number of port becomes for a long time, the same length that only needs to change the direction register makes it can represent maximum portal number; In the process of using, need confirm routing direction and the number of transmitting port in advance, write the Inbound register then, thereby determine routing direction through the portal number in the judgement direction register in the integrated circuit board course of work.
2. the communication module based on the HDLC agreement according to claim 1 is characterized in that said master controller (1) also is used for according to giving up the overtime data from internal bus interface (3) or external sync interface (2) break period of setting.
3. based on the control method for data real time forwarding and storage of the described communication module based on the HDLC agreement of claim 1, it is characterized in that the concrete course of work may further comprise the steps:
Step 1, master controller (1) is set Control Parameter according to the treatment type of the data that receive;
Step 2, master controller (1) are based on said control parameter judgment data treatment type, and judged result is transmitting-receiving and storage data; Then execution in step three, and judged result is transmitted data for no conversion, and then execution in step seven; Judged result is replacement data and transmits that then execution in step ten;
Step 3, master controller (1) judge that judged result is a transmit status to receiving the reiving/transmitting state of data, and then execution in step four, and judged result is an accepting state, and then execution in step five;
Step 4, master controller (1) will receive writing data into memory and according to sending interrupt signal said reception data sent to the external sync interface (2) or the internal bus interface (3) of appointment, return execution in step one then;
Whether the address that step 5, master controller (1) judge to receive in the data is complementary with the address of memory, and judged result is for being, then execution in step six, and judged result is then returned execution in step one for denying;
Step 6, master controller (1) receives described reception data, provides the reception interrupt signal after finishing receiving, and returns step 1;
Step 7, master controller (1) judge whether preserve to receive data, and judged result is for being, then execution in step eight, and judged result is for denying that then execution in step nine;
Step 8, master controller (1) are preserved the reception data of transmitting when receiving data transmitting to the external sync interface (2) of appointment or internal bus interface (3), preserve to provide no conversion forwarding interrupt signal and return execution in step one after accomplishing;
Step 9, master controller (1) is transmitted the reception data to the external sync interface (2) or the internal bus interface (3) of appointment, and forwarding is returned execution in step one after accomplishing;
Step 10, master controller (1) judges whether to replace the data of storage, and judged result is for being, and then execution in step 11, and judged result is not for, and then execution in step nine;
Step 11; Master controller (1) is according to the direction of data forwarding; External sync interface (2) or internal bus interface (3) to appointment are transmitted the reception data that the data that will store in the reception data replace with forwarding; Provide replacement forwarding interrupt signal after transmitting completion, and return execution in step one.
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| CN101635661B (en) * | 2009-08-14 | 2011-09-14 | 烽火通信科技股份有限公司 | Switching HDLC bus |
| CN102495814A (en) * | 2011-12-16 | 2012-06-13 | 创新科存储技术有限公司 | Communication method between controllers of storage device |
| CN103731509B (en) * | 2014-01-23 | 2017-03-08 | 中国联合网络通信集团有限公司 | A kind of data storage transmission control method, respective storage devices and server |
| CN105262659A (en) * | 2015-11-02 | 2016-01-20 | 日立永济电气设备（西安）有限公司 | HDLC protocol controller based on FPGA chip |
| CN112600864A (en) * | 2021-03-05 | 2021-04-02 | 成都奕信科技开发有限公司 | Verification code verification method, device, server and medium |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002009875A (en) * | 2000-06-22 | 2002-01-11 | Hitachi Ltd | Hdlc circuit |
| KR20050060766A (en) * | 2003-12-17 | 2005-06-22 | 엘지전자 주식회사 | Method of error detection and restoration in multi-point type hdlc bus |
| CN101146102A (en) * | 2007-10-16 | 2008-03-19 | 深圳国人通信有限公司 | HDLC data uplink and downlink method and communication device in RRU network |
| CN101163172A (en) * | 2007-11-12 | 2008-04-16 | 东方通信股份有限公司 | High-capacity media broadcasting system and method for mobile phone or fixed telephone switching system |
| CN101267448A (en) * | 2008-05-09 | 2008-09-17 | 东北大学 | An intelligent protocol conversion device and method based on embedded QNX operating system |
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