CN101776028B - Hold-down and release simulation data source system - Google Patents
Hold-down and release simulation data source system Download PDFInfo
- Publication number
- CN101776028B CN101776028B CN200910243287XA CN200910243287A CN101776028B CN 101776028 B CN101776028 B CN 101776028B CN 200910243287X A CN200910243287X A CN 200910243287XA CN 200910243287 A CN200910243287 A CN 200910243287A CN 101776028 B CN101776028 B CN 101776028B
- Authority
- CN
- China
- Prior art keywords
- data
- cpci
- source
- simulation
- serial ports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The invention discloses a simulation data source hold-down and release system, which comprises a CPCI data source device and a back-end computer. The hardware of the CPCI data source device comprises a power panel, a CPU board and a simulation source plate. The power panel is used for supplying power to the whole system; the CPU board is a main control panel of the data source device, and the simulation source plate implements transmission of three paths of serial port signals, output of a path of ignition signals and input of a path of data request signals. The software of the CPCI data source device adopts a VxWorks operating system. The application software comprises an initialization module, a network module and a serial port synchronous transmission module, wherein the initialization module is used for initializing the application software; the network module implements network reception and storage of simulation source data and reception and control execution of the ignition signal, and the serial port synchronous transmission module implements the response of the data request signals and controls the synchronous transmission of the simulation source data. The system solves the problem of synchronous real-time transmission of three paths of simulation data of a hold-down and release triple redundant system.
Description
Technical field
The present invention relates to a kind of hold-down and release simulation data source system, be applied to carrier rocket observing and controlling equivalence emulation field.
Background technique
Pin down delivery system before and after engine ignition, critical system jobs states such as motor on the arrow are carried out faut detection, discharge rocket in the normal back of definite detected system works.Reduce because the probability that the accident of the harm rocket that critical system initial failures such as motor cause, launching site safety takes place improves rocket launching, flight safety and flying reliability.
Pining down delivery system is divided into usually pining down and discharges TT﹠C system and pin down releasing device.Pin down and discharge TT﹠C system functions such as the parameter acquisition of detected object, transmission, fault judgement, transmission instructions.Pin down releasing device between rocket and pad, that realizes rocket and pad reliably is connected and removes connection, release rocket.
For improving reliability, pin down the release TT﹠C system and adopt the triple redundance design, all adopt the triple redundance design from sensor, data capture and transmission, fault judgement, control command output is got two voting circuits according to the output of triple redundance fault judgement through three and is sent.Hold-down and release simulation data source need cooperate triple redundancy embedded computer to finish high real-time, the synchronized transmission of three tunnel redundant datas.
Pin down the input output of external systems such as control that the delivery system simulation data source is used to simulate carrier rocket, remote measurement, checking pins down the fault detection capability of delivery system computer.
The general following three kinds of schemes of traditional simulation data source are carried out emulation testing:
(1) adopt the method for pure hardware to design, have very strong specific aim, but row is poor flexibly, be difficult for expansion and configuration, be difficult to guarantee that pining down the principle tests stage that discharges, the checking changes in demand may cause the hardware change for aspect faces such as fault injection, data logging;
(2) adopt software programming under the general-purpose platform to realize the equivalent system of copying, obviously real-time does not satisfy requirement, is difficult to control accurately the real-time transmission of synchronization accuracy and data under the Windows operation system;
(3) adopt the triple redundance hardware system for simulation data source, will comprise 3 road CPU in the equipment, opposition is finished a function separately, and also there is defective in this scheme, and it is all very high to be that complexity is gone up in the design of hardware design or software synchronization, and costs dearly.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of hold-down and release simulation data source system is provided, solved the synchronously real-time transmission problem that pins down three tunnel emulated datas that discharge the triple redundance system.
Technical solution of the present invention is: hold-down and release simulation data source system, it is characterized in that: comprise CPCI data-source device and backend computer, the CPCI data-source device receives analog data from backend computer, finish the storage of analog data, and according to the response of data request signal, send to front end triple redundance computer, the CPCI data-source device receives the igniting signal instruction from backend computer, and the output of control ignition signal; Backend computer is finished uploading of analog data, the transmission control of fire signal instruction, and reception shows the feedback information of CPCI data-source device, the hardware of CPCI data-source device comprises power panel, CPU board and simulation source plate, power panel is used for powering to whole system, CPU board is the master control borad of data-source device, the transmission of firm and hard existing three road rs 232 serial interface signals of dummy source, the output of one road fire signal, the input of a circuit-switched data demand signal; The software of CPCI data-source device adopts vxworks operating system, application software comprises initialization module, mixed-media network modules mixed-media and serial ports synchronized transmission module, initialization module is used for the initialization of application software, mixed-media network modules mixed-media is realized reception, the control execution of network reception, storage and the fire signal of dummy source data, serial ports synchronized transmission module realizes the response of data request signal, and control dummy source data synchronization sends, described analog data by engine ignition before and the true test data in igniting back form.
Described simulation source plate comprises the CPCI interface chip, the FPGA control circuit, No. three buffer circuits, three electrical level conversion circuits, three interface protective circuits, crystal oscillator, SDRAM, EEPROM, relay, photo coupler, wherein, the configuration information of EEPROM storage CPCI interface chip, after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip, the parallel port data that CPU board will send write in the internal data buffer memory of FPGA control circuit by the CPCI interface chip, SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory, the timer of CPU board in the FPGA control circuit sends enable signal, timer picks up counting according to the clock frequency that crystal oscillator produces, parallel-to-serial converter among the timer control FPGA carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM, when the timer timing then, three road TTL signals after timer control parallel-to-serial converter will be changed are sent to three buffer circuits isolates, carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last; Relay sends to the fire signal of FPGA control circuit output in the triple redundancy embedded computer of front end; The data request signal that triple redundancy embedded computer sends over is sent into the FPGA control circuit through after the photoelectric coupler isolation.
Described serial ports synchronized transmission module adopts the mode of interrupting to realize the data request signal response, and the data request signal response is realized by following three parts:
Initialization section: data request signal is articulated on the request of data interrupt function, creates serial ports synchronized transmission task then, request of data interrupts being set to the state of enabling at last;
Request of data interrupt function part: at first request of data interrupts being set to illegal state, and the request interrupt register that clears data then discharges the synchronizing signal amount at last;
Serial ports synchronized transmission task part: wait for the synchronizing signal amount, when the synchronizing signal amount, begin to carry out the dummy source data synchronization and send, after transmission finishes, request of data interrupts being set to the state of enabling, and returns wait state, waits for next synchronizing signal amount.
Described analog data by engine ignition before and the true test data in igniting back forms, serial ports synchronized transmission module realizes that the process of dummy source data transmission is as follows:
(1) waits for the synchronizing signal amount, when obtaining the synchronizing signal amount, judge whether system's current state is before lighting a fire, if before the igniting, then enter next step, if after the igniting, then directly enter step (6);
(2) from the analog data memory field, take out one group of preceding data of igniting according to current pointer position num, and form the serial communication frame; If from the analog data internal memory, fetch data for the first time, the then first address of pointed analog data internal memory, i.e. num=0;
(3) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundance computer of front end;
(4) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out;
(5) whether judge pointer position num less than n,, then return the synchronizing signal amount state of waiting for if less than n, if be not less than n, after then pointer position num is set to 0, return the synchronizing signal amount state of waiting for again, total group of number of data before the igniting that described n provides for system;
(6) whether at first judge current pointer position num less than n,, after then pointer position num is set to n, enter next step,, then directly enter next step if be not less than n if less than n;
(7) from the analog data memory field, take out one group of igniting back data according to current pointer position num, and form the serial communication frame;
(8) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundance computer of front end;
(9) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out, returns the synchronizing signal amount state of waiting for then.
The present invention's advantage compared with prior art is:
(1) simulation architecture of employing general computer and the combination of front end embedded device when having guaranteed platform reliability, real-time, also possesses very strong flexibility.With user-dependent command control, data transfer and upload by backend computer and finish, and adopt the front end embedded device of vxworks operating system and the real-time transmission of the reliable and analog data that software has guaranteed command execution.Highly versatile, real-time height help pining down the real-time simulation analysis of delivery system fault distinguishing.
(2) by having realized that based on the hardware timing mode of FPGA three road serial ports can be synchronously or asynchronous transmission, the zero-time that sends data between data that every road sends and the Ge Lu can set up on their own at interval, synchronously and the time precision of asynchronous transmission reach the microsecond level;
(3) analog data that adopts of hold-down and release simulation data source system is the firing test data of actual engine, can be according to pining down work characteristics such as discharging the TT﹠C system sequential, make and simulate data files such as various normal, warnings, fault; The user can select corresponding file to upload by backend computer according to content measurement, and flexibility is strong, has strengthened test coverage, easy-to-operat;
(4) software in the CPCI simulation data source system has adopted the memory partitioning management, solve the interim memory reliability problem of data that test data preservation and a large amount of analog datas transmission task conflict cause, prevent to cause loss of data because of reasons such as memory allocation failure and generation fragments;
(5) the serial ports transmitting module among the present invention has adopted the mechanism that serial ports synchronized transmission task and request of data Interrupt Process combine, and has not only guaranteed the redundant real-time response that sends of 3 road serial ports, the more important thing is the quality that improved software and the reliability of system.
Description of drawings
Fig. 1 is a simulation data source system schematic representation of the present invention;
Fig. 2 is a dummy source plate structure schematic representation of the present invention;
Fig. 3 is the theory of constitution figure of FPGA control circuit of the present invention;
Fig. 4 is the cut-away view of being made up of isolation module, electrical level conversion circuit and interface protective circuit;
Fig. 5 is the oscillogram of single channel rs 232 serial interface signal of the present invention;
Fig. 6 is network multiple-task communication structure figure of the present invention;
Fig. 7 realizes request of data responding process figure for serial ports transmitting module of the present invention;
Fig. 8 realizes analog data transmission flow figure for serial ports transmitting module of the present invention.
Embodiment
As shown in Figure 1, be simulation data source system schematic representation of the present invention, comprise CPCI data-source device and backend computer, the CPCI data-source device receives analog data from backend computer, finish the storage of analog data, and, send to front end triple redundance computer according to the response of data request signal, the CPCI data-source device receives the igniting signal instruction from backend computer, and the output of control ignition signal; Backend computer is finished uploading of analog data, the transmission control of fire signal instruction, and receive the feedback information that shows the CPCI data-source device.The CPCI data-source device adopts the form of standard C pci bus, with reliability and the versatility requirement that reaches system, the hardware of CPCI data-source device comprises power panel, CPU board and simulation source plate, power panel is used for powering to whole system, CPU board is the master control borad of data-source device, the transmission of firm and hard existing three road rs 232 serial interface signals of dummy source, the output of one road fire signal, the input of a circuit-switched data demand signal.
CPU board is to pin down the master control borad that discharges head end test and analog machine, has 1 road Ethernet interface, can receive the control command of backend computer, and import status data into supervisory control comuter in real time; Processor selection PowerPC series, dominant frequency is not less than 800MHz, CPU board can be selected GE-CV1 (6U) high-performance CPCI master control integrated circuit board for use, master chip is the MPC7447A G4 processor of Freescale company, it can provide the work dominant frequency of 1GHz, have 256MB DDR SDRAM and 128MB Flash, 1 road PMC interface, 2 tunnel gigabit ethernet interfaces, RS-232 interface and 10 road GPIO interfaces, can satisfy the performance requirement of native system fully, and very big function upgrading space can be provided.Power panel can adopt two redundancy backup schemes, can automatically switch; Input voltage: 200V-240V AC; Output power: be not less than 200W.
As shown in Figure 2; be dummy source plate structure schematic representation; comprise the CPCI interface chip; the FPGA control circuit; No. three buffer circuits; three electrical level conversion circuits; three interface protective circuits; crystal oscillator; SDRAM; EEPROM; relay; photo coupler; the configuration information of EEPROM storage CPCI interface chip; after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip; the parallel port data that CPU board will send write in the internal data buffer memory of FPGA control circuit by the CPCI interface chip; SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory; the timer of CPU board in the FPGA control circuit sends enable signal; timer picks up counting according to the clock frequency that crystal oscillator produces; parallel-to-serial converter among the timer control FPGA carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM; when the timer timing then; three road TTL signals after timer control parallel-to-serial converter will be changed are sent to three buffer circuits isolates; carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last.Relay sends to the fire signal of FPGA control circuit output in the triple redundancy embedded computer of front end; The data request signal that triple redundancy embedded computer sends over is sent into the FPGA control circuit through after the photoelectric coupler isolation.
As shown in Figure 3, the FPGA control circuit comprises three timers, three parallel-to-serial converters, three write buffer area and three and read buffer area, the parallel data that is write by the CPCI interface chip writes three and writes in the buffer area, SDRAM stores three parallel datas that write in the buffer area, three timers receive the enable signal that CPU board sends at the same time or separately, three clock frequency timing respectively that timer produces according to crystal oscillator after receiving enable signal, three parallel-to-serial converters are taken out to three with parallel data and read in the buffer area from SDRAM, three parallel-to-serial converters of three timer control carry out three parallel datas that read in the buffer area and go here and there to change forming three road TTL signals, when the timing of three timers then, three road TTL signal synchronization or asynchronous output after three timer control parallel-to-serial converters will be changed.
As shown in Figure 4, buffer circuit adopts photo coupler to carry out the photoelectricity isolation; Electrical level conversion circuit becomes the TTL signal conversion rs 232 serial interface signal of difference; Interface protective circuit adopts four reference diodes to form, the positive pole butt joint of per two reference diodes, negative pole one end ground connection, another termination one tunnel difference rs 232 serial interface signal.
Between CPCICPU plate and the CPCI interface chip with the parallel mode swap data, the CPCI interface chip constitutes bus interface circuit, transform signal sequence and address and data time-sharing multiplex signal that cpci bus provides, be convenient to rear end equipment and directly use, finish the data communication of FPGA and cpci bus.When serial data sent, the data that CPU board will send write the FPGA inner buffer by the CPCI interface chip, can be by enabling to control 3 road synchronized transmissions.Can set baud rate, parity check bit and the position of rest of transmission.The TTL signal of FPGA output is isolated and level conversion through photoelectricity, exports with serial ports (as RS-422) form.
When serial data receives, the rs 232 serial interface signal of input is converted to the TTL signal through electrical level transferring chip, isolates by photoelectricity, is responsible for receiving and handling by FPGA, use big capacity SDRAM that the data that receive are carried out buffer memory, CPU board can read the data that receive by the CPCI interface chip.
Realize that by FPGA but it is the hardware timer that makes up a plurality of synchronization control that the multi-channel serial port accurate timing sends key, if realize the synchronization accuracy of microsecond level, the frequency of FPGA crystal oscillator will be more than 1M, and the present invention has selected the 24M crystal oscillator for use, and theoretical synchronization accuracy can reach 42ns.The timing of hardware timer can carry out dynamic-configuration, realizes that 3 road serial ports synchronized transmissions need 3 hardware timers, enables the controller unification by 1 and controls, and has selected 3 25 bit timing devices here for use, and the transmitting time difference between its every road can reach 1.4s.
The communication standard that UART serial line interface EIA (EIA) formulates, serial line interface commonly used at present mainly contains RS-232, RS-422, RS-485 interface, the physical layer electrical characteristic difference of distinct interface, but the data frame format of their link layer is identical, is check bit, 1～2 position of rest composition by 1 start bit (logical zero is represented), 5～8 bit data positions (low level is preceding), 1.Parallel data is the byte mode storage the preceding of an employing high position, and-string changes and string-also the implementation of conversion is similar, and just operating process is opposite.And the process of string conversion is: rolling counters forward begins, and parallel-to-serial converter detects three parallel data level that read in the buffer area, all occurs in data bit time middle part with the bits per inch that guarantees this frame according to detecting, and reduces to detect the bit error rate; Data displacement: convert the parallel data little-endian to serial data by displacement mode, deposit in the temporary variable; Parity check: parity check is carried out in the setting of data based parity check after the displacement, when the timer timing to data are sent.
Can realize high-speed cache by the mode of program construction FIFO in fpga chip, need take resource on a large amount of sheets but make up FIFO, that generally can not do is very big, can't realize jumbo high-speed cache.And SDRAM can realize the storage capacity of tens M even M up to a hundred, but its access speed is relatively slow, and the mode that this paper combines with SDRAM by FIFO in the sheet has realized the high-speed cache of multi-channel serial port.
SDRAM has the advantages that the space memory space is big, read or write speed is fast, price is relatively cheap.But its control logic complexity needs periodic refresh operation, line management, different delayed time and command sequence etc.The memory address of SDRAM is divided into page or leaf (bank) address, row (row) address and row (column) address.For example the SDRAM of a 8MByte is divided into 4 bank, and promptly 1 bank is 2Mbyte, and each bank comprises 12 row, 8 row.A series of instructions of SDRAM are as shown in table 1, and each instruction finally all is to realize by control RAS, CAS, WE signal, common operating process such as table 1 to SDRAM.
Table 1 SDRAM operational order
| Order | Abbreviation | RAS | CAS | WE |
| Do-nothing operation | NOP | H | H | H |
| Page or leaf activates | ACT | L | H | H |
| Read operation | RD | H | L | H |
| Write operation | WR | H | L | L |
| Burst operation stops | BT | H | H | L |
| Precharge | PCH | L | H | L |
| Refresh | ARF | L | L | H |
| The configuration mode register | LMR | L | L | L |
The main operation that SDRAM is conducted interviews is exactly to read RD and write the WR operation.SDRAM must carry out page or leaf earlier and activate the ACT operation when carrying out read-write operation, opens to guarantee storage unit, so that therefrom read the address or write the address, closes storage unit and realizes by precharge PHC order.When carrying out write operation, inner column address and data will be deposited; When carrying out read operation, home address is deposited, and behind wait CAS retard time (being generally 1～3 clock cycle), the data of reading appear on the data/address bus, and concrete sequential sees the SDRAM databook for details, repeats no more herein.The present invention is for for simplicity, SDRAM is divided into the space of 3 fixed lengths, store the data that 3 road serial ports receive respectively, FPGA internal build 3 tunnel writes FIFO and 3 tunnel and reads FIFO, and parallel data at first is kept at and writes among the FIFO, and FPGA detects input FIFO in each clock cycle, finding wherein has data just data to be transferred among the SDRAM, whether be full, discontented then the SDRAM data are transferred to read among the FIFO if detecting and read FIFO, the confession primary control program reads.
The CPCI interface card is selected the PCI9030 of PLX company for use, and this chip adopts the 3.3V core voltage, compatible 5V signal level, and low in energy consumption, flexible configuration is simple, is easy to finish the data communication of FPGA and cpci bus; FPGA selects the XC3S400PQ208-4I chip in the Spartan3 of the Xilinx company series for use, and this chip comprises the GATES of 400K, and the RAM of 344K and 141 available I/O pins can satisfy the function requirement of system.
Full duplex serial ports electrical level transferring chip is selected the MAX485 chip for use, and its highest communication speed is 10Mbps, has the esd protection characteristic of 2KV.The interface protection chip is selected the PSM712 of ProTek Devices company for use, and this chip is a RS-422/485 interface TVS array commonly used, can effectively protect interface chip.Rs 232 serial interface signal adopts photoelectricity to isolate, and selects the HCPL0631 of FAIRCHILD company for use, and this chip is the high-speed photoelectric coupler spare of 10Mbps, can satisfy the system speed demand.
The operation system of test is used Windows operation system, the driver of integrated circuit board that adopted Driver studio software programming, the mode of receiving and dispatching mutually with data between each road of serial port board self is tested the transmission and the receiving function of serial ports, uses oscillograph to check that serial ports sends the level nature and the synchronization accuracy of data.After tested, every road serial ports all can normally be received and dispatched data, and the synchronization accuracy error of three road serial ports reaches below the 100ns, can satisfy the synchronization accuracy demand of system, and the waveform of single channel serial ports as shown in Figure 5.
The software of CPCI data-source device adopts vxworks operating system, application software comprises initialization module, mixed-media network modules mixed-media and serial ports synchronized transmission module, initialization module is used for the initialization of application software, mixed-media network modules mixed-media is realized reception, the control execution of network reception, storage and the fire signal of dummy source data, serial ports synchronized transmission module realizes the response of data request signal, and control dummy source data synchronization sends.
Initialization module is finished the initial work of serial ports transmitting module and mixed-media network modules mixed-media, mainly comprises configuration serial ports parameter (as baud rate, position of rest verification mode etc.), initialization network communication socket, system time is set, serial ports lock in time is set, opens up the analog data memory field.
Mixed-media network modules mixed-media: pin down release analogue simulation source software and adopted the TCP application service,, wait for the connection of backend computer as the notion existence of server.Because VxWorks adopts the obstructive type socket of acquiescence, adopt single task pattern and improper, therefore in mixed-media network modules mixed-media, adopt multitask mode to finish the network transmission of test data, storage and function control, its structure is as shown in Figure 6.
(1) netinit task tNetlnit: aperiodic task, finish the work that initialization connects.Simultaneously, this task is as the root task of network service, in case client end has connection request, just need to initiate various subtasks: network sends task, network receives task, information handling task, network monitoring task;
(2) network receives task tNetRecv: periodic task, be blocked on the recv () function of VxWorks system, its main effect is to receive data (analog data frame, fire signal), then all data is passed to information handling task and carries out concrete categorized treatment;
(3) information handling task tNetProc: periodic task, priority is lower, the data that received are resolved, parse the classification of data, if the analog data frame then carries out stores processor, if fire signal, then control simulation source plate output point fire signal is formed acknowledgement frame at last and is sent network transmission task to;
(4) network sends task tNetSend: periodic task is mainly used in the acknowledgement frame of computer transmission to the back-end, as receiving analog data, receiving fire signal etc.Because it is higher that priority is provided with, and after obtaining semaphore, takes out the acknowledgement frame content immediately and send to backend computer.
(5) network monitoring task tNetCheck: aperiodic task, priority are arranged on other network tasks.This task and information receive uses the binary type semaphore synchronous between task, information transmission task.In case network error obtains just initiating network after the binary signal amount and closes task tNetClose;
(6) network is closed task tNetClose: the monocycle task, and be responsible for the deletion network and send task, network reception task, information handling task, reinitialize network then, promptly initiate the netinit task once more.
Pin down discharge CPCI emulated data source device and receive " request of data " signal after, need to send analog data to 3 road serial ports immediately, require application software to have hard real-time, so CPCI emulated data source software has adopted the Vxworks real-time, that reliability is high as operation system of software.Repeatedly invalid in addition inquiry will inevitably reduce the execution efficient of software, therefore response " request of data " signal does not adopt the mode of poll, but adopt the mode of interrupting to finish, but interruption also has the drawback of oneself under the VxWorks, not allowing to call the function and the function form that can cause blocking must fix, therefore in order to ensure the real-time of running software, reliability, the task of the processing procedure of serial ports transmission being placed on a high priority is handled, and not that is to say and handles in the rank of interrupting.In this somewhat similar VxWorks of its basic principle to the mode of abnormal handling: interrupt service routine is just carried out the most basic Interrupt Process, for example disable interrupts, judge interrupt type, remove hardware related register or the like, and the processing of most programs, particularly can cause the program of obstruction, all be put in the serial ports transmission task and carry out.Serial ports synchronized transmission task is finished the extraction, packing of data and is sent to 3 serial ports and handles.After serial ports transmission task obtains the synchronizing signal amount, being divided into " before the igniting " and " igniting back " two branches carries out, two branch's flow processs are similar substantially, because " igniting " preceding analog data has only the n group (as 100 groups, 1 group of 80 floating data), therefore, " igniting " is preceding needs circulation to send these 100 groups; After " igniting ",, send the analog data of back successively since the 100th group.As shown in Figure 7 and Figure 8, be serial ports transmitting module realization flow figure of the present invention.The data request signal response is realized by following three parts:
Initialization section: data request signal is articulated in (function that realization articulates is provided by vxworks operating system) on the request of data interrupt function, creates serial ports synchronized transmission task then, request of data interrupts being set to the state of enabling at last;
Request of data interrupt function part: at first request of data interrupts being set to illegal state, and the request interrupt register that clears data then discharges synchronizing signal amount (allowing serial ports transmission task be able to downward operation) at last;
Serial ports synchronized transmission task part: wait for the synchronizing signal amount, when the synchronizing signal amount, begin to carry out the dummy source data synchronization and send, after transmission finishes, request of data interrupts being set to the state of enabling, and returns wait state, waits for next synchronizing signal amount.
Serial ports synchronized transmission module realizes that the process of dummy source data transmission is as follows:
(1) waits for the synchronizing signal amount, when obtaining the synchronizing signal amount, judge whether system's current state is before lighting a fire, if before the igniting, then enter next step, if after the igniting, then directly enter step (6);
(2) from the analog data memory field, take out one group of preceding data of igniting according to current pointer position num, and form the serial communication frame; If from the analog data internal memory, fetch data for the first time, the then first address of pointed analog data internal memory, i.e. num=0;
(3) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundance computer of front end;
(4) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out;
(5) whether judge pointer position num less than n,, then return the synchronizing signal amount state of waiting for if less than n, if be not less than n, after then pointer position num is set to 0, return the synchronizing signal amount state of waiting for again, total group of number of data before the igniting that described n provides for system;
(6) whether at first judge current pointer position num less than n,, after then pointer position num is set to n, enter next step,, then directly enter next step if be not less than n if less than n;
(7) from the analog data memory field, take out one group of igniting back data according to current pointer position num, and form the serial communication frame;
(8) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundance computer of front end;
(9) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out, returns the synchronizing signal amount state of waiting for then.
Practical application with certain model is an example below, and the present invention is further set forth:
1, data source choosing and handling
Choosing 80 groups of data of 5 motors of analog data requirement forms by 2 groups of true firing test data files of YF-100 motor and YF-77 transmitter.The file format of two engine test data is EXCEL, the data cycle is 10ms, according to pining down the delivery system operation cycle is 20ms, the demand of each period measuring and one group of data of processing, in EXCEL employing file, select for use even number line to remove the odd-numbered line method, promptly be processed into data of every 20ms, finally make to pin down to discharge observing and controlling and make up one group of firing test data that every 20ms obtains motor.
It is long and unknown to pin down the delivery system igniting Pretesting time, and prefiring data all are initial value (0) and no change basically.If corresponding one group of analog data of each 20ms operation cycle before the igniting, data volume is too big, and front end dummy source Device memory can't meet the demands.Therefore hold-down and release simulation data source adopts diverse ways to handle and the transmission data with the igniting back before adopting igniting: only choosing 100 groups of data creatings is prefiring analog data, and hold-down and release simulation data source will circulate and send these 100 groups of data before igniting; Be back 20 seconds of igniting owing to pin down the life cycle of delivery system, therefore need choose the data after 1000 (20*50) organize " igniting " again, totally 1100 groups of simulation firing test datas are formed final dummy source data file, at last the EXCEL document format data is directly saved as the txt text, offer backend computer and use.
2, the processing of analog data and uploading
Hold-down and release simulation data source system need discharge one group of analog data of observing and controlling combination transmission to pining down with the cycle of 20ms, in order to guarantee the real-time of test process, adopt following scheme: after dummy source system backend computer and CPCI simulation data source are set up network and be connected, backend computer is with the disposable front end CPCI simulation data source of passing to of whole analog datas, finish the process that analog data is uploaded, and work is afterwards given front end CPCI simulation data source fully and is finished.
Pining down release backend computer development platform is VC6.0, adopt the object oriented language of windows platform to develop its user interface, realize reading and sending of analog data file, and the transmission ignition control signal etc., adopt prior art commonly used to realize,, therefore need backend computer to finish conversion treatment because the dummy source data are the floating character string of common txt text formatting, after forming the binary source code data, utilize socket to send to CPCI emulated data source software again by network.
3, headend equipment is data processing and transmission
A) storage of data
Owing to promptly will store data (analog data) and program-code in the internal memory of CPCI emulated data source software, for reliability and the Security that improves software, the own memory partitioning management method of The software, code area and data area is separately strict, utilize malloc () and memPartCreate () function to go up the data storage area of setting up oneself at Installed System Memory subregion (Memory Partition) at first earlier, next calls memPartAlloc () and realize the memory management of oneself as required on this new subregion, distribute analog data size internal memory pond, after pining down that task termination of release, fall with memPartFree () to discharge internal memory at last.
According to system requirements, pin down discharge CPCI emulated data source software also need in Flash, store upload analog data, for interpretation afterwards provides foundation.Because writing and wipe, Flash all need complicated step just can finish, and the life-span is limited, therefore software selects the TFFS file system to safeguard storing the storage operation of data, adopting read is the file system interface of standard, in easy to operate, prolong Flash working life, improved the reliability of data power down storage.
B) triple redundance synchronized transmission
After carrier rocket changes electricity, pining down release observing and controlling combination beginning is the cycle to send " request of data " signal to external system with 20ms, begin to receive data and carry out the faut detection judgement, therefore hold-down and release simulation data source system need be by 3 road redundant 485 serial ports, and synchronized transmission goes out one group of identical analog data.Redundant synchronizing function is had relatively high expectations, and precision is not less than 10us, is therefore mainly guaranteed by hardware design, and provides the time synchronization interface to upper application software.
Preamble is mentioned the analog data that keeps in the CPCI simulation data source Device memory, and to have only preceding 100 groups be " igniting " preceding firing test data, therefore need circulation to send these data, and send (the simulation external system begins to enter igniting back state) after the instruction of " igniting " by backend computer as the user, CPCI emulated data source software should be immediately since the 101st group of analog data that sends successively backward after " igniting ".
The present invention not detailed description is a technology as well known to those skilled in the art.
Claims (4)
1. hold-down and release simulation data source system, it is characterized in that: comprise CPCI data-source device and backend computer, the CPCI data-source device receives analog data from backend computer, finish the storage of analog data, and according to the response of data request signal, send to the triple redundancy embedded computer of this system front end, the CPCI data-source device receives the igniting signal instruction from backend computer, and the output of control ignition signal; Backend computer is finished uploading of analog data, the transmission control of fire signal instruction, and reception shows the feedback information of CPCI data-source device, the hardware of CPCI data-source device comprises power panel, CPU board and simulation source plate, power panel is used for powering to whole system, CPU board is the master control borad of data-source device, the transmission of firm and hard existing three road rs 232 serial interface signals of dummy source, the output of one road fire signal, the input of a circuit-switched data demand signal; The software of CPCI data-source device adopts vxworks operating system, application software comprises initialization module, mixed-media network modules mixed-media and serial ports synchronized transmission module, initialization module is used for the initialization of application software, mixed-media network modules mixed-media is realized reception, the control execution of network reception, storage and the fire signal of dummy source data, serial ports synchronized transmission module realizes the response of data request signal, and control dummy source data synchronization sends, described analog data by engine ignition before and the true test data in igniting back form.
2. hold-down and release simulation data source system according to claim 1, it is characterized in that: described simulation source plate comprises the CPCI interface chip, the FPGA control circuit, No. three buffer circuits, three electrical level conversion circuits, three interface protective circuits, crystal oscillator, SDRAM, EEPROM, relay, photo coupler, wherein, the configuration information of EEPROM storage CPCI interface chip, after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip, the parallel port data that CPU board will send write in the internal data buffer memory of FPGA control circuit by the CPCI interface chip, SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory, the timer of CPU board in the FPGA control circuit sends enable signal, timer picks up counting according to the clock frequency that crystal oscillator produces, parallel-to-serial converter among the timer control FPGA carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM, when the timer timing then, three road TTL signals after timer control parallel-to-serial converter will be changed are sent to three buffer circuits isolates, carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last; Relay sends to the fire signal of FPGA control circuit output in the triple redundancy embedded computer of front end; The data request signal that the triple redundancy embedded computer of front end sends over is sent into the FPGA control circuit through after the photoelectric coupler isolation.
3. hold-down and release simulation data source system according to claim 1 is characterized in that: described serial ports synchronized transmission module adopts the mode of interrupting to realize the data request signal response, and the data request signal response is realized by following three parts:
Initialization section: data request signal is articulated on the request of data interrupt function, creates serial ports synchronized transmission task then, request of data interrupts being set to the state of enabling at last;
Request of data interrupt function part: at first request of data interrupts being set to illegal state, and the request interrupt register that clears data then discharges the synchronizing signal amount at last;
Serial ports synchronized transmission task part: wait for the synchronizing signal amount, when the synchronizing signal amount, begin to carry out the dummy source data synchronization and send, after transmission finishes, request of data interrupts being set to the state of enabling, and returns wait state, waits for next synchronizing signal amount.
4. according to claim 1 or 3 described hold-down and release simulation data source systems, it is characterized in that: described analog data by engine ignition before and the true test data in igniting back forms, serial ports synchronized transmission module realizes that the process of dummy source data transmission is as follows:
(1) waits for the synchronizing signal amount, when obtaining the synchronizing signal amount, judge whether system's current state is before lighting a fire, if before the igniting, then enter next step, if after the igniting, then directly enter step (6);
(2) from the analog data memory field, take out one group of preceding data of igniting according to current pointer position num, and form the serial communication frame; If from the analog data internal memory, fetch data for the first time, the then first address of pointed analog data internal memory, i.e. num=0;
(3) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundancy embedded computer of front end;
(4) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out;
(5) whether judge pointer position num less than n,, then return the synchronizing signal amount state of waiting for if less than n, if be not less than n, after then pointer position num is set to 0, return the synchronizing signal amount state of waiting for again, total group of number of data before the igniting that described n provides for system;
(6) whether at first judge current pointer position num less than n,, after then pointer position num is set to n, enter next step,, then directly enter next step if be not less than n if less than n;
(7) from the analog data memory field, take out one group of igniting back data according to current pointer position num, and form the serial communication frame;
(8) communication frame is filled into respectively among the FIFO of 3 serial ports of simulating source plate; 3 serial ports that start the simulation source plate then carry out synchronized transmission, three circuit-switched data are sent to the triple redundancy embedded computer of front end;
(9) num=num+1, promptly pointer position points to the memory address of next the group analog data that will take out, returns the synchronizing signal amount state of waiting for then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910243287XA CN101776028B (en) | 2009-12-30 | 2009-12-30 | Hold-down and release simulation data source system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910243287XA CN101776028B (en) | 2009-12-30 | 2009-12-30 | Hold-down and release simulation data source system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101776028A CN101776028A (en) | 2010-07-14 |
| CN101776028B true CN101776028B (en) | 2011-12-21 |
Family
ID=42512584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910243287XA Active CN101776028B (en) | 2009-12-30 | 2009-12-30 | Hold-down and release simulation data source system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101776028B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761199A (en) * | 2014-01-03 | 2014-04-30 | 哈尔滨工业大学 | CPCI bus digital-analog input module hardware architecture under VxWorks and CPCI bus digital-analog input timing-configurable driving method under VxWorks |
| CN103885912B (en) * | 2014-03-24 | 2016-12-07 | 上海航天电子通讯设备研究所 | A kind of moon exploration program miniaturization multiple types data source analog circuit |
| CN104895700B (en) * | 2015-04-15 | 2017-04-05 | 北京航天自动控制研究所 | A kind of low time delay ignition confirming system and confirmation method of arrow ground information fusion |
| CN105629952B (en) * | 2015-12-30 | 2018-04-03 | 中国航空综合技术研究所 | A kind of method of testing of engine control software |
| CN105425784B (en) * | 2015-12-30 | 2018-04-03 | 中国航空综合技术研究所 | A kind of inspection method of engine control software |
| CN106406076B (en) * | 2016-07-06 | 2019-06-28 | 上海宇航系统工程研究所 | A kind of carrier rocket redundancy sequential control system |
| CN108469207B (en) * | 2018-02-01 | 2020-02-07 | 蓝箭航天空间科技股份有限公司 | Launch method, launch automatic control method and launch control system of carrier rocket |
-
2009
- 2009-12-30 CN CN200910243287XA patent/CN101776028B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101776028A (en) | 2010-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101776028B (en) | Hold-down and release simulation data source system | |
| CN101931580B (en) | System on chip adopting ARINC 659 rear panel data bus interface chip | |
| CN101799678B (en) | Three-way asynchronous serial-port data real-time synchronous transmitting system | |
| CN102929836B (en) | Special ASIC (Application Specific Integrated Circuit) chip system for spaceflight | |
| CN103473196B (en) | Remote measuring and controlling data transmission device in a kind of 1553B bus and star between device bus | |
| CN101788945B (en) | Diagnostic test system and method for electronic system with multiple circuit boards or multiple modules | |
| CN103744753B (en) | A kind of data interactive method of dual systems and device | |
| CN102999425B (en) | Based on the housekeeping software emulation test system of virtual instrument technique | |
| CN104656632A (en) | Integrated interface test system and detection method for aircraft semi-physical simulation tests | |
| CN103488565B (en) | A kind of distributed real-time testing system test data collection method | |
| CN111800345B (en) | High-reliability constellation networking space router circuit | |
| CN105760241A (en) | Exporting method and system for memory data | |
| CN105515673B (en) | A kind of optical-fibre channel node card | |
| CN102023900B (en) | Two-channel fault logic arbitration method and system thereof | |
| CN113806290B (en) | High-integrity system-on-a-chip for integrated modular avionics systems | |
| CN102201908B (en) | EAST central timing system based on PXI (extension for instrumentation) | |
| CN109507991A (en) | A kind of two axis servo control platform debugging system and method | |
| CN101604304B (en) | Multi-CPU communication method and relay protection device | |
| CN202939599U (en) | ARINC429 bus test equipment | |
| CN101833535B (en) | Finite state machine with radiating resistant function for reconfigurable satellite-loaded computer | |
| CN105511815B (en) | A kind of PLC based on segment table can operating file storing and resolving method and storage system | |
| CN112486748B (en) | Test system and test method thereof | |
| CN204390224U (en) | A kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA | |
| CN100357933C (en) | A 386EX CPU based embedded computer system | |
| CN104572537A (en) | Fault-tolerant master-slave synchronization serial communication system based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |