CN108874720A - A kind of high precision timing serial data sending method and system - Google Patents
A kind of high precision timing serial data sending method and system Download PDFInfo
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- CN108874720A CN108874720A CN201810549302.2A CN201810549302A CN108874720A CN 108874720 A CN108874720 A CN 108874720A CN 201810549302 A CN201810549302 A CN 201810549302A CN 108874720 A CN108874720 A CN 108874720A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses a kind of high precision timing serial data sending method and systems, including fpga chip, further include the jtag interface being connected on fpga chip, RS-485/RS-422 transceiver and CLOCK clock source.To solve the problems, such as application software and multiple task operating system bad timing, serial data and timing parameters drive bus interface to be loaded into fpga chip by PCI-E, send serial data using the hardware timing function of fpga chip.Since the CLOCK clock source of hardware is the crystal oscillator used and itself Clock management technology, so timing accuracy is very high, suitable for requiring harsh occasion to regularly sending.Solving the transmission of existing serial ports is to be controlled to send by test software, in the case where fixed time interval requires relatively high, the problem of will lead to test crash.
Description
Technical field
Industrial test technical field, and in particular to a kind of high precision timing serial data sending method and system.
Background technique
RS-422 (EIA RS-422-AStandard) is the serial ports connection standard of the macintosh computer of Apple.
RS-422 uses differential signal, and RS-232 uses the non-equilibrium signal with reference to ground.Differential transfer is sent and received using both threads
Signal compares RS-232, it preferably antinoise and can have farther transmission range.In industrial environment better noise immunity and
Farther transmission range is a very big advantage.
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.It is as the field specific integrated circuit (ASIC)
One of semi-custom circuit and occur, not only solved the deficiency of custom circuit, but also overcome original programming device door electricity
The limited disadvantage of number.
JTAG(Joint Test Action Group；Joint test working group) it is a kind of international standard test protocol
(IEEE 1149.1 is compatible) is mainly used for chip interior test.Most high-grade devices all supports JTAG protocol now, such as
DSP, FPGA device etc..The jtag interface of standard is 4 lines：TMS, TCK, TDI, TDO, respectively model selection, clock, data are defeated
Enter and DOL Data Output Line.
Existing serial ports transmission is to be controlled to send by test software, this will receive multiple task operating system and software itself is fixed
When inaccurate influence, it is possible in the case where fixed time interval requires relatively high, will lead to test crash.
Summary of the invention
It is to be controlled to send by test software the technical problem to be solved by the present invention is to the transmission of existing serial ports, this will receive
The influence of multiple task operating system and software itself bad timing, it is possible in the case where fixed time interval requires relatively high, meeting
Lead to test crash, and it is an object of the present invention to provide a kind of high precision timing serial data sending method and system, solve existing serial ports
Transmission is to be controlled to send by test software, this will receive the influence of multiple task operating system and software itself bad timing, and having can
Can be in the case where fixed time interval require relatively high, the problem of will lead to test crash.
The present invention is achieved through the following technical solutions：
A kind of high precision timing serial data sending method and system, including fpga chip, further include being connected to FPGA core
Interface, RS-485/RS-422 transceiver and the CLOCK clock source of on piece.It is fixed to solve application software and multiple task operating system
When inaccurate problem, serial data and timing parameters are loaded into fpga chip by PCI-E driving bus interface, using FPGA
The hardware timing function of chip sends serial data.Since the CLOCK clock source of hardware is the crystal oscillator used and the clock of itself
Administrative skill, so timing accuracy is very high, suitable for requiring harsh occasion to regularly sending.PCI-E bus is one to finish
A kind of complete completely new bus specification for being different from pci bus in the past, compared with pci bus shares parallel architecture, PCI-E bus is one
The equipment connection mode of the point-to-point serial connection of kind, it is point-to-point to mean that each PCI-E device is owned by oneself independent number
According to connection, the transmission of concurrent data is independent of each other between each equipment, and that shared bus mode for past PCI, PCI
There can only be an equipment to be communicated in bus, once the equipment mounted in pci bus increases, the actual transmissions speed of each equipment
Rate will decline, and performance cannot be guaranteed.PCI-E handles communication in a point-to-point fashion, and each equipment is requiring transmission data
When respectively establish oneself transmission channel, be for this channel of other equipment it is closed, such operation ensure that logical
The monopoly in road avoids the interference of other equipment.
It further include the power supply module that DC/DC converter and LDO linear voltage regulator by being connected on FPGA form.LDO is
A kind of linear voltage regulator is subtracted from the input voltage of application using the transistor or field-effect tube run in its linear region
The voltage of excess is removed, the output voltage through overregulating is generated.
It further include the prom memory being connected on FPGA.PROM had referred to " programmable read only memory " both
Programmable Read-Only Memory.Such product only allows to be written once, so also referred to as " can once compile
Journey read-only memory ".
It further include the jtag interface being connected on FPGA.
A kind of high precision timing serial data sending method, including the following steps successively carried out：
A, application layer software will need the serial data packet sent and time parameter to be loaded into FPGA by PCI-E interface
Chip；
B, fpga chip regularly sends RS-485/RS-422 transceiver according to the time parameter received in step A
Interval is set；
C, CLOCK clock source provides time base for fpga chip；
D, FPGA sends serial data packet by RS-485/RS-422 transceiver according to the time parameter in step B.
A block RAM region is configured inside fpga chip, for placing serial data and timing parameters.
Application software passes through the ram region of PCI-E bus configuration fpga chip.
Compared with prior art, the present invention having the following advantages and benefits：
1, a kind of high precision timing serial data sending method of the present invention and system, pass through the standard of FPGA own hardware timing
Really control, it is ensured that when test source is sent to equipment under test by serial ports, time accuracy with higher；
2, a kind of high precision timing serial data sending method of the present invention and system, since the clock source of hardware is to use
The Clock management technology of crystal oscillator and itself, so timing accuracy is very high, suitable for requiring harsh occasion to regularly sending.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings：
Fig. 1 is schematic structural view of the invention；
Fig. 2 is fpga logic module diagram of the present invention；
Fig. 3 is present invention emulation schematic diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation for explaining only the invention, are not made
For limitation of the invention.
Embodiment 1
As shown in Figure 1, a kind of high precision timing serial data sending method of the present invention and system, including fpga chip, also
Including the interface, RS-485/RS-422 transceiver and CLOCK clock source being connected on fpga chip.For solve application software and
The problem of multiple task operating system bad timing, serial data and timing parameters drive bus interface to be loaded by PCI-E
Fpga chip sends serial data using the hardware timing function of fpga chip.Since the CLOCK clock source of hardware is to use
The Clock management technology of crystal oscillator and itself, so timing accuracy is very high, suitable for requiring harsh occasion to regularly sending.
PCI-E bus is a kind of a kind of completely new bus specification of pci bus of being totally different from over, shares parallel architecture with pci bus
It compares, PCI-E bus is a kind of equipment connection mode of point-to-point serial connection, point-to-point to mean each PCI-E equipment
Be owned by oneself independent data connection, the transmission of concurrent data is independent of each other between each equipment, and for past PCI that
Shared bus mode is planted, there can only be an equipment to be communicated in pci bus, once the equipment mounted in pci bus increases, often
The actual transfer rate of a equipment will decline, and performance cannot be guaranteed.PCI-E handles communication in a point-to-point fashion, each
Equipment respectively establishes oneself transmission channel when requiring transmission data, be for this channel of other equipment it is closed,
It is such to operate the monopoly that ensure that channel, avoid the interference of other equipment.
It further include the power supply module that DC/DC converter and LDO linear voltage regulator by being connected on FPGA form.LDO is
A kind of linear voltage regulator is subtracted from the input voltage of application using the transistor or field-effect tube run in its linear region
The voltage of excess is removed, the output voltage through overregulating is generated.
It further include the prom memory being connected on FPGA.PROM had referred to " programmable read only memory " both
Programmable Read-Only Memory.Such product only allows to be written once, so also referred to as " can once compile
Journey read-only memory ".
It further include the jtag interface being connected on FPGA.
Embodiment 2
A kind of high precision timing serial data sending method, including the following steps successively carried out：
A, application layer software will need the serial data packet sent and time parameter to be loaded into FPGA by PCI-E interface
Chip；
B, fpga chip regularly sends RS-485/RS-422 transceiver according to the time parameter received in step A
Interval is set；
C, CLOCK clock source provides time base for fpga chip；
D, FPGA sends serial data packet by RS-485/RS-422 transceiver according to the time parameter in step B.
A block RAM region is configured inside fpga chip, for placing serial data and timing parameters.
Application software passes through the ram region of PCI-E bus configuration fpga chip.
Embodiment 3
As shown in Figure 2 and Figure 3, the present embodiment is fpga logic module instance, is comprised the following modules：
The major function of uart_ram module, the module includes：Realize that serial ports sends data storage, host computer will be to be sent
All data be stored entirely in the module, the module is by the data of storage automatically according to the frame period of setting, frame length, hair
The parameters such as interval are sent to circuit sequentially transmission.The module input/output signal and explanation are as shown in table 1.
Table 1
The module is divided into two parts, and a part is that data to be sent are all written in transmission RAM host computer, another part
For after being connected to supervisory transmission order, the data of storage are sent by the requirement of setting.
Serial data sends RAM and is set as dual port RAM, and RAM data width is set as 8, and depth is up to 65536, end
Mouth a write-in, port b are read.Ram space depth ram_len is frame length frame_len and frame number set by higher level
Frame_num is multiplied.Sending address frame_addr of the hair frame in ram space is frame length frame_len set by higher level
It is multiplied with frame counting number frame_num_cnt.
When carrying out RAM write operation, when tx_ram_wren&&wr_en is 1, i.e., transmission RAM write is enabled effective and is write
Operation starts to carry out writing into RAM data, and RAM data write signal txdata_ram_wr_en is 1, and write address wr_addr is from 0
Start once to be incremented by, works as wr_addr>=ram_len, then it represents that all data all in write-in RAM, close write operation, will
Txdata_ram_wr_en is set to 0, remaining state txdata_ram_wr_en is 0, without write operation, when write operation, RAM
Location is that wr_addr is delayed 1 clock cycle.
It when starting to carry out read operation, sends operation state of a control machine and is in original state IDLE, when data transmission starts
There is rising edge in order tx_data_begin, starts data and sends, state machine jumps to TX_DATA, data valid signal
Data_valid becomes 1；In TX_DATA state, carry out data transmission, the address rd_addr where sending data in RAM according to
It is secondary to be incremented by, work as rd_addr>=frame_len+frame_addr-1'b1, expression have sent a frame data, into transmission data
Preparation state TX_PRE, data send frame count frame_num_cnt and add 1, when data send initiation command tx_data_
Begin rises edge under occurring, stop data and send；In TX_PRE state, as frame cycle count cnt==frame_cycle-1'
B1, expression can carry out next frame data transmission, jump to TX_DATA state, send since being continued a upper address, when
Frame_num_cnt==frame_num&&cnt==frame_cycle-1'b1, i.e. frame count are equal to the frame of setting
Number, indicates that all frames are all sent, by frame_num_cnt<=16'b0, sends since first frame again.Send number
It is that data valid signal data_valid is delayed 3 clock cycle according to effective txdata_valid.
The major function of uart module, the module includes：Exampleization Subordinate module realizes that serial ports transmits and receives communication protocol,
The various running parameters of serial ports are set by higher level.The module input/output signal and explanation are as shown in table 2.
Table 2
Uart module is mainly to carry out the setting of the example and basic working modes of Subordinate module.
Send data when, loop parameter is set as loop back mode, when loop be 1, then the serial ports number that will be received inside FPGA
According to directly transmitting away, when loop is 0 and fifo_en is 1, then data write-in to be sent is sent in FIFO, then will send
FIFO output, is sent to sending module uart_tx, carries out data transmission, directly will input when loop is 0 and fifo_en is 0
Data, be sent in uart_tx, carry out data transmission.As (tfifo_data_count<tgate)&&(|tgate)&&
Tx_intr_en&&fifo_en) effectively, send interrupt tx_intr be 1, (tx_intr_en&&~fifo_en&&ack) effectively,
Sending and interrupting tx_intr is 1, and it is 0 that remaining state, which sends and interrupts tx_intr,.Sending FIFO reading enable signal tfifo_rden is
~tfifo_empty&& (ack | tfifo_pre_rd) &&~rdy_n sends FIFO reset signal tfifo_rsttfifo_rst
For~nrst | | tfifo_full | | tfifo_clr, sending data fifo input tfifo_din is that higher level's data input data_
I, sending FIFO and writing enabled tfifo_wr_en is fifo_en？data_ie:1'b0 sends the non-full signal tfifo_no_ of FIFO
Full is~tfifo_full.
When receiving data, receiving FIFO not empty signal rfifo_no_empty is~rfifo_empty, and receiving FIFO and writing makes
Energy rfifo_rden is~rfifo_empty&&rfifo_rd_i, and receiving FIFO reset signal rfifo_rst is~nrst | |
Rfifo_full | | rfifo_clr, receiving data fifo input rfifo_din is fifo_en&&~loop？urx_data_o:
8'b0, receiving data fifo and writing enabled rfifo_wr_en is fifo_en&&~loop？urx_data_oe:1'b0, when FIFO makes
Can, i.e. fifo_en is 1, and receiving data data_o is to receive FIFO output, otherwise directly exports, connects for receiving module uart_rx
Receiving enabled data_oe is that reception FIFO output is enabled, is otherwise directly exported for receiving module uart_rx enabled.As (rx_intr_
En&&fifo_en) effective and (rfifo_data_count>=rgate) && (| rgate) | | (wait_time>=
Overtime) effectively, receiving and interrupting rx_intr is 1, when rx_intr_en&&~fifo_en&&urx_data_oe is effective, is connect
Receiving interruption rx_intr is 1, and it is 0 that remaining state, which receives and interrupts rx_intr,.Interrupt latency wait_time is received, when not having
Data input, and when rising edge occurs in serial ports clock uart_clk when beginning with data input, then becomes again automatically plus 1
0, whether there is or not Data Labels WAIT signals to be：Receiving FIFO and counting is not 0, and is counted constant.
The major function of uart_clk module, the module includes：Generate the serial ports clock uart_clk that serial port module needs
With 16 times of serial ports clock uart_clk_x16.The module input/output signal and explanation are as shown in table 3.
Table 3
Under the rising edge triggering of serial ports Base clock clk_uart_base, each baud rate counts acc_phase and adds
Baud rate parameter baudrate exports the highest order of several acc_phase, is gclk, and be delayed 1 clock cycle, and as 16
Times serial ports clock uart_clk_x16, clock frequency are：500MHz*baudrate/2^32.By gclk rising edge generate when
In clock signal uart_clk_x16_p input clock frequency division module clkdiv16,16 frequency dividings generate serial ports clock uart_
clk。
The major function of clkdiv16 module, the module includes：Input clock is subjected to 16 frequency dividings, and is exported.The module
Input/output signal and explanation are as shown in table 4.
Table 4
When input clock clk_x1 is 1, clock count cnt adds 1, when clk_x1 is 1 and clock count cnt is 7, then divides
Output clock jumps, final to generate 16 frequency dividing output clk_d16.
The major function of uart_tx module, the module includes：Input parallel data is serially sent, data width,
The parameters such as stop position, check bit are settable.The module input/output signal and explanation are as shown in table 5.
Table 5
When data input is effective, input data data is put into transmitter register bufdata by data_valid 1.
Data transmission controls transmission flow, original state txstate by 1 state machine<=IDLE, serial data exports at this time
uart_o<=1'b1, ready rdy_n<=1'b0, when data_valid be 1, jump to beginning state txstate<=
START；In START state, when serial ports clock is rising edge, i.e. uart_clk_pos is 1, by the number to be sent in bufdata
Parity check bit prtybit is obtained according to being put into transmitter register uart_tsr, and by bufdata data progress XOR operation,
Jump to transmission state txstate
<=SHIFT；Serial mode is sent out by turn under conditions of uart_clk_pos is 1 in SHIFT state,
Data width can be set, and when even-odd check is set as parity_en [1] effectively, is then entered verification state PARITY, otherwise entered
STOP_1BIT state；Verification state PARITY, uart_clk_pos be 1 under conditions of, when parity_en [0] be 1, then
For odd, it is even parity check, and jump to STOP_1BIT state that parity_en [0], which is 0,；In STOP_1BIT state,
Under conditions of uart_clk_pos is 1, work as stop_wd==2'b01, is 1.5bit stop position, jumps to STOP_HALFBIT
State is 1 by uart_o output 1 in uart_clk_neg, stops sending, and return to IDLE state, work as stop_wd==2'
B10 is 2bit stop position, jumps to STOP_2BIT state, is 1 by uart_o output 1 in uart_clk_pos, stops sending,
And IDLE state is returned, it is otherwise 1bit stop position, direct uart_o output 1 stops sending, returns to IDLE state.
Output response ack is rdy_n signal failing edge, i.e. transmission idle, can receive supervisory transmission data and life
It enables, carries out data transmission.
The major function of uart_rx module, the module includes：By the Serial data receiving of input, and be converted to simultaneously line number
According to passing to higher level's module.The module input/output signal and explanation are as shown in table 6.
Table 6
When failing edge occurs in serial data input uart_i, i.e. when uart_neg is 1, beginning log-on data is received, and is originally set
Meter carries out data sampling using 16 times of serial ports clock uart_clk_x16, when uart_clk_x16 is rising edge, counter
Cntmid starts to be incremented by, and when cntmid==4'd7 is, sample_mid 1 indicates that sampling is in serial data interlude,
When~sample_mid_syn&sample_mid is 1 to indicate that sampling is enabled, sample_en becomes 1.
Data receiver controls and receives process, original state rxstate by 1 state machine<=IDLE, works as uart_
Neg is 1, jumps to beginning state rxstate<=START；In START condition, when sample_en is 1, expression sampling is received
Start, jumps to reception state rxstate<=SHIFT；In SHIFT state, under conditions of sample_en is 1, by turn will
Serial data receiving is put into and receives shift register rxbuf, and data width data_wd can be set, when even-odd check is set as
Parity_en [1] effectively, then enters verification state PARITY, otherwise enters STOP_BIT state；State PARITY is being verified,
Under conditions of sample_en is 1, input uart_syn is assigned to check bit prtybit；In STOP_BIT state,
Under conditions of sample_en is 1, original state IDLE is returned.
(under the conditions of rxstate==STOP_BIT) &sample_en, will output useful signal data_valid be set to
1, the data for receiving shift register rxbuf are assigned to data_o, exports, check bit prtybit is assigned to prtybit_
o.As ^ { prtybit_o, data_o } &&parity_en [1:0]==2'b10 or~(^ { prtybit_o, data_
o})&& parity_en[1:0]==2'b11, indicates verification discovery mistake, and err signal is assigned to 1.
The major function of timer module, the module includes：According to the parameter that host computer is arranged, timing is carried out, timing is generated
Interrupt output.The module input/output signal and explanation are as shown in table 7:
Table 7
It is 1 when interrupting enabled int_en, then break period counting cnt adds 1 to be incremented by, and works as cnt==int_time-1'b1) |
|~int_en is effective, and cnt is set to 0.Work as cnt==int_time-1'b1, interrupt output intr<=1'b1, and it is continuously 1,
It is 1 until host computer sends interrupt clear order int_clr, then removes interruption, interrupt output intr<=1'b0.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (7)
1. a kind of high precision timing serial data sends system, including fpga chip, which is characterized in that further include being connected to FPGA
PCI-E interface, RS-485/RS-422 transceiver and CLOCK clock source on chip.
2. a kind of high precision timing serial data according to claim 1 sends system, which is characterized in that further include by even
Connect the power supply module of the DC/DC converter and LDO linear voltage regulator composition on FPGA.
3. a kind of high precision timing serial data according to claim 1 sends system, which is characterized in that further include connection
Prom memory on FPGA.
4. a kind of high precision timing serial data according to claim 1 sends system, which is characterized in that further include connection
Jtag interface on FPGA.
5. a kind of high precision timing serial data sending method according to claim 1, which is characterized in that including successively into
Capable following steps：
A, application layer software will need the serial data packet sent and time parameter to be loaded into FPGA core by PCI-E interface
Piece；
B, fpga chip regularly sends interval to RS-485/RS-422 transceiver according to the time parameter received in step A
It is set；
C, CLOCK clock source provides time base for fpga chip；
D, FPGA sends serial data packet by RS-485/RS-422 transceiver according to the time parameter in step B.
6. a kind of high precision timing serial data sending method according to claim 1, which is characterized in that in fpga chip
Inside one block RAM region of configuration, for placing serial data and timing parameters.
7. a kind of high precision timing serial data sending method according to claim 1, which is characterized in that application software is logical
Cross the ram region of PCI-E bus configuration fpga chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111638444A (en) * | 2020-05-07 | 2020-09-08 | 湖北航天技术研究院计量测试技术研究所 | High-capacity FPGA (field programmable Gate array) testing tool and testing method based on SPI (Serial peripheral interface) configuration mode |
| CN112925684A (en) * | 2021-03-22 | 2021-06-08 | 西安紫光国芯半导体有限公司 | Testing method of link establishment logic and related equipment |
| CN114760364A (en) * | 2022-04-02 | 2022-07-15 | 沈阳飞机设计研究所扬州协同创新研究院有限公司 | Time-triggered serial device communication management method |
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