CN102104427B - FPGA-based nuclear magnetic resonance data communication implementation device and method - Google Patents

Abstract

The invention relates to a field programmable gate array (FPGA)-based nuclear magnetic resonance data communication implementation device and an FPGA-based nuclear magnetic resonance data communication implementation method. An optical fiber Ethernet scanning control board is interconnected with an optical fiber communication card through a multimode optical fiber; the optical fiber Ethernet scanning control board comprises a back panel interface, an I-type communication protocol converter and a first optical fiber transceiving module, wherein the I-type communication protocol converter is in communication connection with a spectrometer system through the back panel interface and performs bidirectional transmission with the optical fiber communication card through the first optical fiber transceiving module; and the optical fiber communication card comprises a peripheral component interconnect express (PCIe) interface, a second optical fiber transceiving module and an II-type communication protocol converter, wherein the II-type communication protocol converter is in communication connection with a control console through the PCIe interface and performs bidirectional transmission with the optical fiber Ethernet scanning control board through the second optical fiber transceiving module. The invention supports transmission of multi-receiving channel data and solves the problem of high-speed communication of mass data; a LINK serial data protocol and an Ethernet frame format type data protocol are analyzed and generated; and the device is simple in structure, high in integration level and stable in operation.

Description

Nuclear magnetic resonance data communication implementation device based on FPGA and method

Technical field

The present invention relates to nulcear magnetic resonance (NMR) control technology, specifically a kind of nuclear magnetic resonance data communication implementation device and method based on FPGA.

Background technology

Operation control for the ease of operator to nuclear magnetic resonance imaging system, and be convenient to realize scanning device is controlled in real time and is managed concentratedly, nuclear magnetic resonance imaging system all adopts control desk to be placed in operation room at present, and is placed in the implementation pattern between instrument for the spectrometer of sequence scanning control.Because the implementation structure of different nuclear magnetic resonance imaging system is different, data communication protocol between the inner modules of the data/address bus pattern that control desk adopts and spectrometer is also different, thereby makes the communication mode between nuclear magnetic resonance spectrometer and nuclear magnetic resonance console also different.

In existing technology, there are two kinds of diverse ways to realize the nuclear magnetic resonance data communication between control desk and spectrometer, the first adopts the data mode based on isa bus local area network technology of copper medium, the data throughout of which is restricted, and can not be applied to the transmission of many receive paths mass data; It two is to adopt the opto-electronic conversion data communication mode based on pci bus of fiber medium, and which complex structure is with high costs, is difficult to support multi-channel data transmission.

Summary of the invention

Above-mentionedly be difficult to support the weak points such as the transmission of multichannel magnanimity quantity for what exist in prior art, the technical problem to be solved in the present invention is to provide a kind of for realizing the high-speed data communication between nuclear magnetic resonance spectrometer and control desk, support the transmission of many receive paths data, solve the nuclear magnetic resonance data communication implementation device based on FPGA and the method for mass data high-speed communication problem.

For solving the problems of the technologies described above, the technical solution used in the present invention is:

The nuclear magnetic resonance data communication implementation device that the present invention is based on FPGA comprises: be placed in fiber optic Ethernet scan control plate and the optical fiber communication card that is placed in control desk in spectrometer system, independently between board, realize interconnected by multimode fiber for two;

Fiber optic Ethernet scan control plate comprises backplane interface, I type communication protocols converter and the 1st optical fiber transceiving module, I type communication protocols converter is communicated and is connected with spectrometer system by backplane interface, carries out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card;

Optical fiber communication card comprises PCIe interface, the 2nd optical fiber transceiving module and II type communication protocols converter, II type communication protocols converter is communicated and is connected with control desk by PCIe interface, carries out transmitted in both directions by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate.

Described I type communication protocols converter is realized by FPGA, there is 1LINK module, 1LINK2TSE module, 1TSE2LINK module, 1TSE IP kernel module and 1CFG_TSE module, wherein 1LINK module is carried out communicating by letter of serial LINK protocol data by backplane interface and spectrometer system, and the LINK protocol data that 1LINK2TSE module receives 1LINK module is connected with 1TSE IP kernel module after converting TSE protocol data to; 1TSE IP kernel module is connected with 1LINK module after converting TSE protocol data to LINK protocol data by 1TSE2LINK module; 1TSE IP kernel module is carried out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card.

Described 1LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial LINK data of backplane interface after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to backplane interface by LINK passage simultaneously.

Under the condition that described 1LINK2TSE module receives in 1LINK module data or error identification in FIFO, the state of analysis, reset mode signal changes, the data fifo that 1LINK module is received, and the error identification signal combination that backplane interface transmits becomes LAN data frame format, and send to TSE IP kernel module.

1TSE2LINK module is carried out determined property to the received data of 1TSE IP kernel module, if LINK data write in the transmission FIFO of 1LINK, if analyze mark or reset identification-state signal, directly send backplane interface to by status signal lines.

Described II type communication protocols converter is realized by FPGA, there is 2LINK module, 2LINK2TSE module, 2TSE2LINK module, 2TSE IP kernel module, 2CFG TSE module and back-end data integrator, wherein back-end data integrator is communicated and is connected with control desk by PCIe interface, and the LINK protocol data that 2LINK2TSE module receives 2LINK module is connected with 2TSE IP kernel module after converting TSE protocol data to; 2TSE IP kernel module is connected with 2LINK module after converting TSE protocol data to LINK protocol data by 2TSE2LINK module; 2TSE IP kernel module is by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate transmitted in both directions.

Described 2LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial data of back-end data integrator after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to back-end data integrator by LINK passage simultaneously.

Described 2LINK2TSE module receives and has in FIFO under the condition that the state of data or error identification signal changes in 2LINK module, the data fifo that 2LINK module is received, and the analysis that back-end data integrator transmits becomes LAN data frame format with reset mode signal combination, and send to 2TSE IP kernel module.

Described 2TSE2LINK module is carried out determined property to the received data of 2TSE IP kernel module, if LINK data write in the transmission FIFO of 2LINK, if error identification status signal directly sends back-end data integrator to by status signal lines.

Described backstage integrator is carried out on the one hand by the error identification from 2TSE2LINK module with from the LINK data of 2LINK module and LINK passage sky/full scale is known and whether PCIe packet is ready to identify the operation that sends to PCIe interface module; On the other hand according to received data attribute, by LINK data and reset signal and analytical signal interpretation out, and send to respectively 2LINK module and 2LINK2TSE module.

Described I type communication protocols converter also has 1CFG_TSE module and II type communication protocols converter also has 2CFG_TSE module, 1CFG_TSE module is configured for MAC Address and lan data frame maximum length to 1TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 1TSE IP kernel monitors fiber connection status of optical and changes, need again 1TSE IP kernel module to be configured; 2CFG_TSE module is configured for MAC Address and lan data frame maximum length to 2TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 2TSE IP kernel monitors fiber connection status of optical and changes, need again 2TSE IP kernel module to be configured.

The nuclear magnetic resonance data communication implementation method that the present invention is based on FPGA comprises the following steps:

Receive respectively the data of spectrometer system and control desk transmission by fiber optic Ethernet scan control plate and optical fiber communication card;

Process in the data of fiber optic Ethernet scan control plate and optical fiber communication card while pair spectrometer system and control desk transmission respectively, obtain respectively fiber-optic signal separately;

The fiber-optic signal that fiber optic Ethernet scan control plate obtains self exports optical fiber communication card to through fiber medium; The fiber-optic signal that the card of optical fiber communication simultaneously obtains self through fiber medium exports fiber optic Ethernet scan control plate to;

The fiber-optic signal that optical fiber communication card imports fiber optic Ethernet scan control plate into is sent to control desk after processing; The fiber-optic signal that fiber optic Ethernet scan control plate imports optical fiber communication card into is simultaneously sent to spectrometer system after processing.

The described data that send in fiber optic Ethernet scan control plate pair spectrometer system are processed and are comprised the following steps:

The data that spectrometer system sends are delivered to by backplane interface and in the I type communication protocols converter of fiber optic Ethernet scan control plate, are carried out being sent to the 1st optical fiber transceiving module after the synthetic and conversion process of data, form serial optical optical fiber signaling, transfer to optical fiber communication card through fiber medium;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

I type communication protocols converter receives LINK data and the error condition mark that backplane interface is imported into;

LINK data transfer to 1LINK2TSE module by 1LINK module, and error condition mark directly transfers to 1LINK2TSE module;

1LINK2TSE module is integrated into local area network (LAN) formatted data by the LINK data of above-mentioned reception and error condition mark and after 1TSE IP kernel module is carried out parallel-serial conversion, is sent to the 1st optical fiber transceiving module.

The processing procedure of described 1LINK2TSE module is as follows:

Start, enter idle condition;

Judged whether LINK data inputs, or whether status signal changes or changing of executing state machine first;

If meet one of above-mentioned three conditions, enter data packet head and send state;

Judge whether executing state machine first, in this way, enter index mark transmission state;

In the time of index mark=0x1f, enter error identification and send state, return to index mark transmission state;

In the time of index mark=0x3f, enter and analyze mark transmission state, return to index mark transmission state;

In the time of index mark=0x7f, enter the mark transmission state that resets, return to index mark transmission state;

In the time of index mark=0x1c, enter the empty mark of FIFO transmission state, return to index mark transmission state;

In the time of index mark=0x1b, enter FIFO full scale and know transmission state, return and wait for a clock cycle state, then enter idle condition;

If not executing state machine first, LINK data are judged whether;

If there are LINK data, enter LINK index and send state, then enter data length and send state;

In the time of index mark=0x01, enter LINK0 channel data and send state;

In the time of index mark=0x03, enter LINK1 channel data and send state;

In the time of index mark=0x07, enter LINK2 channel data and send state;

If when the state of above-mentioned index mark is all false, enters LINK3 channel data and send state.

Does judgement send the quantity=0x01 of data in the time entering LINK0 channel data transmission state?

If equation is false, returns to LINK0 channel data and send state;

If equation is set up, judge whether LINK1, LINK2, LINK3 passage have data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK1 channel data transmission state?

If equation is false, returns to LINK1 channel data and send state;

If equation is set up, judge whether LINK2, LINK3 passage have data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK2 channel data transmission state?

If equation is false, returns to LINK2 channel data and send state;

If equation is set up, judge whether LINK3 passage has data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK3 channel data transmission state?

If equation is false, returns to LINK3 channel data and send state;

If equation is set up, go to index mark transmission state.

The fiber-optic signal that described optical fiber communication card imports fiber optic Ethernet scan control plate into comprises the following steps after processing:

The fiber data that fiber optic Ethernet scan control plate sends through fiber medium is sent to PCIe interface after carrying out the synthetic and conversion process of data during optical fiber transceiving module is delivered to the II type communication protocols converter of optical fiber communication card, form PCIe bus data, be uploaded to control desk;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter receives LAN data and the error condition mark imported into from the 2nd optical fiber module;

LAN data carries out data by the transmission of 2TSE IP kernel module and unpacks, carry out the conversion of LAN data agreement to LINK protocol data by 2TSE2LINK module, and the go-on-go status indicator that makes mistake, the LINK protocol data of changing out is sent to 2LINK module and becomes serial LINK data to deliver to back-end data integrator through 2LINK module converts, the go-on-go status indicator that makes mistake is directly sent to back-end data integrator, back-end data integrator by after error condition mark and serial LINK Data Integration through PCIe interface sending console.

The processing procedure of described 2TSE2LINK module is as follows:

Start, enter peek state;

Enter TSE data wait state;

Is data receiver useful signal=1 waited in judgement?

If above formula is set up, have:

In the time that TSE reception data are respectively 0x01,0x03,0x07 and 0x0f, all enter the LINK transmission data length state that obtains;

In the time that TSE reception data are 0x1f, enter the error identification state that sends;

In the time that TSE reception data are 0x3f, enter to send and analyze identification-state;

In the time that TSE reception data are 0x7f, enter the reset signal state that sends;

In the time that TSE reception data are 0x1c, enter and send empty identification-state;

In the time that TSE reception data are 0x1b, enter and send full identification-state;

When entering when obtaining LINK and sending data length state, if data receiver useful signal is high level, have:

In the time that data index value is respectively 0x01,0x03,0x07 and 0x0f, enter respectively LINK0 data and send that state, LINK1 data send state, LINK2 data send state and LINK3 data send state, in passage separately, judge respectively data counts value be whether 0 and data receiver useful signal be high level; If meet above-mentioned condition, be all back to the next step that wait data receiver useful signal is 1 and process; If do not meet above-mentioned condition, return to the data of passage separately and send state;

In the time that data index value is 0x1f, enter the error identification state that sends;

In the time that data index value is 0x3f, enters to send and analyze identification-state;

In the time that data index value is 0x7f, enter the reset signal state that sends;

In the time that data index value is 0x1c, enters and send empty identification-state;

In the time that data index value is 0x1b, enters and send full identification-state;

Judge above-mentioned transmission error identification state, send and analyze identification-state, send reset signal state, send empty identification-state and send whether the completely data receiver useful signal of identification-state is high level, if level, all be back to TSE data wait state, otherwise in the corresponding state being back to separately.

The data that described optical fiber communication card sends control desk are processed, and obtain fiber-optic signal and comprise the following steps:

The PCIe bus data that control desk imports into transfers to and in II type communication protocols converter, carries out, after the synthetic and conversion process of data, being sent to fiber optic Ethernet scan control plate by optical fiber transceiving module through fiber medium through PCIe interface;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter takes out serial LINK data, reset mode mark and analysis state mark from back-end data integrator, become LAN protocol data by all transferring to 2LINK2TSE module converts with reset mode mark and analysis state mark after the parallel LINK data of 2LINK module converts one-tenth, by being transferred to fiber optic Ethernet scan control plate by the 2nd optical fiber module through fiber medium after the packing of 2TSE IP kernel module.

The fiber-optic signal that described fiber optic Ethernet scan control plate imports optical fiber communication card into is processed and is comprised the following steps:

Optical fiber communication card transfers to serial optical optical fiber signaling through fiber medium the 1st optical fiber transceiving module and delivers to and in I type communication protocols converter, carry out the synthetic and conversion process of data, and the data after the synthetic and conversion process of data are delivered to spectrometer system by backplane interface;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

The local area network (LAN) serial data obtaining from the 1st optical fiber transceiving module gone here and there by 1TSE IP kernel module and change send into 1TSE 2LINK module and carry out data protocol conversion, divide and detect LINK data and reset mode mark and analysis state mark, 1LINK module becomes serial LINK data to deliver to backplane interface LINK data decomposition, reset mode mark and analysis state mark are directly delivered to after backplane interface, by backplane interface unification, LINK data, position status indicator and analysis state mark are transferred to spectrometer system.

The data that fiber optic Ethernet scan control plate pair spectrometer system sends are processed and are comprised the following steps:

The data that spectrometer system sends are delivered to by backplane interface and in the I type communication protocols converter of fiber optic Ethernet scan control plate, are carried out being sent to the 1st optical fiber transceiving module after the synthetic and conversion process of data, form serial optical optical fiber signaling, transfer to optical fiber communication card through fiber medium;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

I type communication protocols converter receives LINK data and the error condition mark that backplane interface is imported into;

LINK data transfer to 1LINK2TSE module by 1LINK module, and error condition mark directly transfers to 1LINK2TSE module;

1LINK2TSE module is integrated into local area network (LAN) formatted data by the LINK data of above-mentioned reception and error condition mark and after 1TSE IP kernel module is carried out parallel-serial conversion, is sent to the 1st optical fiber transceiving module.

The present invention has following beneficial effect and advantage:

1. the present invention proposes a kind of new types of data communication pattern that realize based on FPGA, that employing kilomega optic fiber is transmission medium, for realizing the high-speed data communication between nuclear magnetic resonance spectrometer and control desk, support the transmission of many receive paths data, solve mass data high-speed communication problem.

2. realize parsing and the generation of LINK serial data agreement and Ethernet frame format data protocol; Support data reconstruction and state of a control to identify with packet transmission, simple in structure, integrated level is high, stable.

Brief description of the drawings

Fig. 1 is apparatus of the present invention structured flowchart;

Fig. 2 is LINK2TSE module status machine workflow diagram in the present invention;

Fig. 3 is TSE2LINK module status machine workflow in the present invention.

Embodiment

The nuclear magnetic resonance data communication implementation device that the present invention is based on FPGA by two kinds independently board form, be respectively the fiber optic Ethernet scan control plate being placed in spectrometer system and be placed in the Ethernet-PCIe optical fiber communication card of control desk base plate PCIe slot; Independently between board, realize interconnected by multimode fiber for two.Fig. 1 has provided the structured flowchart of apparatus of the present invention.

Fiber optic Ethernet scan control plate comprises backplane interface, I type communication protocols converter and the 1st optical fiber transceiving module, I type communication protocols converter is communicated and is connected with spectrometer system by backplane interface, carries out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card;

Optical fiber communication card comprises PCIe interface, the 2nd optical fiber transceiving module and II type communication protocols converter, II type communication protocols converter is communicated and is connected with control desk by PCIe interface, carries out transmitted in both directions by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate.

Fiber optic Ethernet scan control plate is made up of backplane interface, I type communication protocols converter and optical fiber transceiving module (SFP).Backplane interface is used for realizing four groups of LINK channel signals, error identification (ERROR) signal and reset (RESET) is connected with analysis (ANALYSE) signaling interface, I type communication protocols converter is for realizing the conversion between LINK communication protocol and Ethernet communication protocol, and optical fiber transceiving module (SFP) is for realizing the conversion of optical fiber gigabit Ethernet HSSI High-Speed Serial Interface signal and the signal of telecommunication.

Ethernet-PCIe optical fiber communication card is made up of optical fiber interface, II type communication protocols converter and PCIe interface.Optical fiber transceiving module (SFP) is for realizing the conversion of optical fiber gigabit Ethernet HSSI High-Speed Serial Interface signal and the signal of telecommunication, II type communication protocols converter is integrated the conversion between LINK communication protocol and Ethernet communication protocol for realizing back-end data, PCIe interface adopts the PCIeCompiler IP kernel of altera corp to realize, and connects for completing PCIe HSSI High-Speed Serial Interface signaling interface.

Fiber optic Ethernet scan control plate, interconnected by realizing distributed parallel processor by spectrometer backplane interface, comprise radio frequency reception channel data in interior serial LINK communication protocol data, be packaged into Ethernet frame format packet together with error identification (ERROR) signal, by the optical fiber transceiving module (SFP) on plate, taking multimode fiber as medium, be transferred in Ethernet-PCIe optical fiber communication card, again the Ethernet frame format packet receiving through multimode fiber is unpacked simultaneously, sort out LINK data and reset (RESET) and analyze (ANALSYS), according to LINK serial data agreement, the LINK data that sort out are changed, and after buffer memory by LINK data placement in LINK bus,

Ethernet-PCIe optical fiber communication card, by the scan control order and the data that receive from the PCIe universal serial bus of operation computer, be converted to LINK protocol format by PCIe protocol format, and by conversion after data according to Ethernet frame format, optical fiber transceiving module (SFP) on plate, taking multimode fiber as medium, be transferred in fiber optic Ethernet scan control plate, to unpack through the received Ethernet frame format packet that comprises multichannel radio frequency reception data of multimode fiber again simultaneously, obtain LINK protocol data, and be uploaded to control desk according to PCIe protocol format, rebuild original imaging data is provided for Magnetic resonance imaging.

Described I type communication protocols converter is realized by FPGA, there is 1LINK module, 1LINK2TSE module, 1TSE2LINK module, 1TSE IP kernel module and 1CFG_TSE module, wherein 1LINK module is carried out communicating by letter of serial LINK protocol data by backplane interface and spectrometer system, and the LINK protocol data that 1LINK2TSE module receives 1LINK module is connected with 1TSE IP kernel module after converting TSE protocol data to; 1TSE IP kernel module is connected with 1LINK module after converting TSE protocol data to LINK protocol data by 1TSE2LINK module; 1TSE IP kernel module is carried out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card.

1LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial LINK data of backplane interface after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to backplane interface by LINK passage simultaneously.

Under the condition that 1LINK2TSE module receives in 1LINK module data or error identification in FIFO, the state of analysis, reset mode signal changes, the data fifo that 1LINK module is received, and the error identification signal combination that backplane interface transmits becomes LAN data frame format, and send to TSE IP kernel module.

1TSE2LINK module is carried out determined property to the received data of 1TSE IP kernel module, if LINK data write in the transmission FIFO of 1LINK, if analyze mark or reset identification-state signal, directly send backplane interface to by status signal lines.

Described II type communication protocols converter is realized by FPGA, there is 2LINK module, 2LINK2TSE module, 2TSE2LINK module, 2TSE IP kernel module, 2CFG_TSE module and back-end data integrator, wherein back-end data integrator is communicated and is connected with control desk by PCIe interface, and the LINK protocol data that 2LINK2TSE module receives 2LINK module is connected with 2TSE IP kernel module after converting TSE protocol data to; 2TSE IP kernel module is connected with 2LINK module after converting TSE protocol data to LINK protocol data by 2TSE2LINK module; 2TSE IP kernel module is by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate transmitted in both directions.

2LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial data of back-end data integrator after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to back-end data integrator by LINK passage simultaneously.

2LINK2TSE module receives and has in FIFO under the condition that the state of data or error identification signal changes in 2LINK module, the data fifo that 2LINK module is received, and the analysis that back-end data integrator transmits becomes LAN data frame format with reset mode signal combination, and send to 2TSE IP kernel module.

2TSE2LINK module is carried out determined property to the received data of 2TSE IP kernel module, if LINK data write in the transmission FIFO of 2LINK, if error identification status signal directly sends back-end data integrator to by status signal lines.

Described backstage integrator is carried out on the one hand by the error identification from 2TSE2LINK module with from the LINK data of 2LINK module and LINK passage sky/full scale is known and whether PCIe packet is ready to identify the operation that sends to PCIe interface module; On the other hand according to received data attribute, by LINK data and reset signal and analytical signal interpretation out, and send to respectively 2LINK module and 2LINK2TSE module.

Described I type communication protocols converter also has 1CFG_TSE module, and II type communication protocols converter also has 2CFG_TSE module, 1CFG_TSE module is configured for MAC Address and lan data frame maximum length to 1TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 1TSE IP kernel monitors fiber connection status of optical and changes, need again 1TSE IP kernel module to be configured; 2CFG_TSE module is configured for MAC Address and lan data frame maximum length to 2TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 2TSE IP kernel monitors fiber connection status of optical and changes, need again 2TSE IP kernel module to be configured.

Communication protocols converter of the present invention shows as two entities realizing based on FPGA (field programmable gate array) technology, is respectively the I type communication protocols converter that is applied to fiber optic Ethernet scan control plate and the II type communication protocols converter that is applied to Ethernet-PCIe optical fiber communication card.I type communication protocols converter and II type communication protocols converter include LINK module, LINK2TSE module, TSE2LINK module, TSE IP kernel module and CFG_TSE module, and II type communication protocols converter comprises back-end data integrator (BACKEND) module simultaneously.

LINK module in I type communication protocols converter and II type communication protocols converter, by four groups independently LINK passage and receive FIFO and send FIFO form.In LINK module, first changed into the parallel data of 8 from the serial LINK signal of spectrometer backboard, be then written to and receive in FIFO, the data that send in FIFO are sent to spectrometer backboard by LINK passage simultaneously.

LINK2TSE module in I type communication protocols converter and II type communication protocols converter, under the condition that have data or error identification (Error) in LINK module reception (RX) FIFO, analyze (Analyses), the state of the status signals such as (Reset) that resets changes, the data fifo that LINK module is received, and the error identification (Error) that transmits of backboard, analyze the status signal such as (Analyses) and reset (Reset) and be combined into Ethernet data frame format, and send to TSE IP kernel module.

TSE2LINK module in I type communication protocols converter and II type communication protocols converter, the data that TSE module is received are carried out to determined property, if LINK data write in transmission (TX) FIFO of LINK, if such as error identification (Error), analysis (Analyses) or the status signals such as (Reset) that resets, directly send spectrometer backplane interface to by status signal lines.

TSE2LINK module in I type communication protocols converter and II type communication protocols converter, adopts the TSE IP kernel of altera corp to realize.This IP kernel can be supported the MAC of tri-speed of 10M/100M/1000M, and the PCS of a 1000Base-X and an optional PMA.The present embodiment is selected the mode of operation of 1000M MAC+1000Base-X/SGMII PCS, use Transceiver Block (GXB) resource simultaneously, the inside FIFO degree of depth of TSE is used 2048, width is 8, and the configuration of inner critical registers adopts following strategy: Ipg_length=64; Frm_length=1518; TX_FIFO_AE=8; TX_FIFO_AF=8; TX_FIFO_SECTION_EMPTY=1800; TX_FIFO_SECTION_FULL=16; Command_config=0x0408003b.

CFG_TSE module in I type communication protocols converter and II type communication protocols converter, be configured for the project such as MAC Address and Ethernet Frame maximum length to TSE IP kernel, control configuration flow by a state machine, state machine starts to carry out from idle condition.After configuration completes, if monitoring fiber connection status of optical, TSE IP kernel changes, need again TSE IP kernel module to be configured.

Back-end data integrator (BACKEND) module in II type communication protocols converter, on the one hand, carry out by the error identification from TSE2LINK module (ERROR) with from the LINK data of LINK module, and LINK passage sky/full scale is known and whether PCIe packet is ready to identify the operation that sends to PCIe interface module, on the other hand, also will be according to received data attribute, by LINK data and reset (Reset) signal and analysis (Analyses) signal resolution out, and send to respectively LINK module and LINK2TSE module.

LINK2TSE module in communication protocols converter and TSE2LINK module all need Ethernet frame format packet to operate, wherein LINK2TSE module completes the reception of serial LINK data and the generation of Ethernet frame format packet, and TSE2LINK module completes parsing and the transmission of Ethernet frame format packet data.

Ethernet frame format packet is made up of the one or more subdata bags of source address+destination address+length ten, source address and destination address are got identical value 0xAAAAAAAAAAAA, each subdata handbag is containing the data of a LINK or the state of a status signal that will transmit, its data format is: Data_index+Length (optional)+Content, wherein, Data_index indicate transmission data type, its subdata bag dtd--data type definition is as shown in table 1; Length indicate transmission data length, LINK categorical data has data length definition, and error identification (Error), analysis (Analyse) and (Reset) status indicator signal that resets do not have data length definition; Content is the data content that will transmit, if Data_index is LINK categorical data, the content of Content is exactly LINK data, if status indicator signal, the content of Content is exactly the state value of corresponding state signal, wherein, and when status signal is high level, the content of Content is 0x01, is 0x00 when low level.The order that subdata bag forms whole data type is: LINK0 data+LINK1 data+LINK2 data+LINK3 data+error identification (Error) signal+analysis mark (Analyses) signal+reset (Reset) signal+FIFO sky (rx_fifo_empty) id signal+FIFO full (ff_rx_a_full) id signal.If the data that some packets will not transmit, do not comprise corresponding subdata bag in this packet.

Table 1 subdata bag dtd--data type definition table

Data type	Data_index numerical value
		LINK0 data	?0x01
LINK1 data	?0x03
		LINK2 data	?0x07
LINK3 data	?0x0f
		Error identification (Error) signal	?0x1f
Analyze (Analyzes) signal	?0x3f
		(Reset) signal resets	?0x7f
FIFO sky (rx_fifo_empty) signal	?0x1c
		Full (ff_rx_a_full) signal of FIFO	?0x1b
Invalid data or signal	Other value

The nuclear magnetic resonance data communication implementation method that the present invention is based on FPGA comprises the following steps:

Receive respectively the data of spectrometer system and control desk transmission by fiber optic Ethernet scan control plate and optical fiber communication card;

Process in the data of fiber optic Ethernet scan control plate and optical fiber communication card while pair spectrometer system and control desk transmission respectively, obtain respectively fiber-optic signal separately;

The fiber-optic signal that fiber optic Ethernet scan control plate obtains self exports optical fiber communication card to through fiber medium; The fiber-optic signal that the card of optical fiber communication simultaneously obtains self through fiber medium exports fiber optic Ethernet scan control plate to;

The fiber-optic signal that optical fiber communication card imports fiber optic Ethernet scan control plate into is sent to control desk after processing; The fiber-optic signal that fiber optic Ethernet scan control plate imports optical fiber communication card into is simultaneously sent to spectrometer system after processing.

1) data that fiber optic Ethernet scan control plate pair spectrometer system sends are processed and are comprised the following steps:

The data that spectrometer system sends are delivered to by backplane interface and in the I type communication protocols converter of fiber optic Ethernet scan control plate, are carried out being sent to the 1st optical fiber transceiving module after the synthetic and conversion process of data, form serial optical optical fiber signaling, transfer to optical fiber communication card through fiber medium;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

I type communication protocols converter receives LINK data and the error condition mark that backplane interface is imported into; LINK data transfer to 1LINK2TSE module by 1LINK module, and error condition mark directly transfers to 1LINK2TSE module;

1LINK2TSE module is integrated into the LINK data of above-mentioned reception and error condition mark to export 1TSE IP kernel module after local area network (LAN) formatted data to and carry out data and be sent to the 1st optical fiber transceiving module.

The processing procedure of described 1LINK2TSE module as shown in Figure 2,

Start, enter idle condition;

Judged whether LINK data inputs, or whether status signal changes or executing state machine first;

If meet one of above-mentioned three conditions, enter data packet head and send state;

Judge whether executing state machine first, in this way, enter index mark transmission state;

In the time of index mark=0x1f, enter error identification and send state, return to index mark transmission state;

In the time of index mark=0x3f, enter and analyze mark transmission state, return to index mark transmission state;

In the time of index mark=0x7f, enter the mark transmission state that resets, return to index mark transmission state;

In the time of index mark=0x1c, enter the empty mark of FIFO transmission state, return to index mark transmission state;

In the time of index mark=0x1b, enter FIFO full scale and know transmission state, return and wait for a clock cycle state, then enter idle condition;

If not executing state machine first, LINK data are judged whether;

If there are LINK data, enter LINK index and send state, then enter data length and send state;

In the time of index mark=0x01, enter LINK0 channel data and send state;

In the time of index mark=0x03, enter LINK1 channel data and send state;

In the time of index mark=0x07, enter LINK2 channel data and send state;

If when the state of above-mentioned index mark is all false, enters LINK3 channel data and send state;

Does judgement send the quantity=0x01 of data in the time entering LINK0 channel data transmission state?

If equation is false, returns to LINK0 channel data and send state;

If equation is set up, judge whether LINK1, LINK2, LINK3 passage have data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK1 channel data transmission state?

If equation is false, returns to LINK1 channel data and send state;

If equation is set up, judge whether LINK2, LINK3 passage have data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK2 channel data transmission state?

If equation is false, returns to LINK2 channel data and send state;

If equation is set up, judge whether LINK3 passage has data;

If there are data, return to LINK index and send state;

If there is no data, go to index mark transmission state.

Does judgement send the quantity=0x01 of data in the time entering LINK3 channel data transmission state?

If equation is false, returns to LINK3 channel data and send state;

If equation is set up, go to index mark transmission state.

LINK2TSE module is the shared module of I type communication protocols converter and II type communication protocols converter, is responsible for carrying out the conversion operations of LINK serial protocol data to Ethernet frame format data.

In the present embodiment, LINK2TSE module interface protocol definition 12 kinds of different input signals, be respectively: the reset signal (rst_n) of Low level effective; Work clock signal (clk); In LINK module, receive the LINK data that FIFO exports (link_data[i] [link_fifo_width-1..0] wherein, i=0,1,2,3); In LINK module receive (RX) FIFO the data with existing degree of depth (rdusedw[i] [link_fifo_dwidth-1..0] wherein, i=0,1,2,3); In LINK module for 4 dummy status identification lists (rdempty[3..0]) that receive FIFO; TSE module sends (TX) FIFO will expire status indicator (ff_tx_a_full); TSE module receives (TX) FIFO, and whether preparedness identifies (ff_tx_rdy); For error identification (Error), the analysis mark (Analyses) of identification-state and mark (Reset) signal that resets; Whether phase-locked loop the phase-locked id signal (locked) of success.

In the present embodiment, LINK2TSE module interface protocol definition 6 kinds of different output signals, be respectively: the data (ff_tx_data[TSE_fifo_width-1..0]) that write TSE module and send (TX) FIFO; That exports to TSE module writes ED id signal (ff_tx_eop); The data of writing of exporting to TSE module start id signal (ff_tx_sop); Export to TSE module and be used for representing the transmission whether vicious id signals of data (ff_tx_err); Export to TSE module for writing data enable signal (ff_tx_wren); Export to LINK reception (RX) FIFO read identification list (link_fifo_rd[3..0]).

The operating state of LINK2TSE module is implemented to control by state machine, and this state machine has 15 states and forms, and is respectively idle condition (idle), data packet head sends state (send_package_head), LINK index sends state (send_link_index), data length sends state (send_data_length), LINK0 channel data sends state (send_data_link0), LINK1 channel data sends state (send_data_link1), LINK2 channel data sends state (send_data_link2), LINK3 channel data sends state (send_data_link3), wait for a clock cycle state (wait_1t), index mark transmission state (send_misc_index), error identification sends state (send_err), analyze mark transmission state (send_analyses), FIFO empty mark transmission state (send_rx_fifo_empty), FIFO full scale is known transmission state (send_ff_rx_a_full), mark transmission state (send_reset) resets.

After module resets, state machine is first in idle condition (idle), then judge whether executing state machine first, if carry out first the data packet head transmission state (send_package_head) that directly enters, execution contains source address, the transmit operation of the data packet head of destination address and length information, then enter index mark transmission state (send_misc_index) so the mark of transmission, enter respectively afterwards error identification and send state (send_err), analyze mark transmission state (send_analyses), FIFO empty mark transmission state (send_rx_fifo_empty), FIFO full scale is known transmission state (send_ff_rx_a_full) and the mark transmission state (send_reset) that resets, to send the status signal of initial state, after completing aforesaid operations, state machine enters idle condition (idle), to wait for that LINK receives (RX) FIFO and has data, or error identification (Error), analyze (Analyse), reset (Reset), the empty mark of FIFO, the id signal generation level such as FIFO full scale knowledge change, once receiving (RX) FIFO, LINK have data or id signal level to change, state machine enters the transmit operation of data packet head transmission state (send_package_head) executing data bag.In the time having the condition of multiple satisfied transmissions, should enter transmission state according to the priority of LINK0 > LINK1 > LINK2 > LINK3 > error identification (Error) > analysis (Analyzes) > reset (Reset) > FIFO sky (rx_fifo_empty) > FIFO full (ff_rx_a_full).Be sent rear state machine and again enter the pending transmit operations such as idle condition (idle).

2) fiber-optic signal that optical fiber communication card imports fiber optic Ethernet scan control plate into comprises the following steps after processing:

The fiber data that fiber optic Ethernet scan control plate sends through fiber medium is sent to PCIe interface after carrying out the synthetic and conversion process of data during optical fiber transceiving module is delivered to the II type communication protocols converter of optical fiber communication card, form PCIe bus data, be uploaded to control desk;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter receives LAN data and the error condition mark imported into from the 2nd optical fiber module;

LAN data carries out data by the transmission of 2TSE IP kernel module and unpacks, carry out the conversion of LAN data agreement to LINK protocol data by 2TSE2LINK module, and the go-on-go status indicator that makes mistake, the LINK protocol data of changing out is sent to 2LINK module and becomes serial LINK data to deliver to back-end data integrator through 2LINK module converts, the go-on-go status indicator that makes mistake is directly sent to back-end data integrator, back-end data integrator by after error condition mark and serial LINK Data Integration through PCIe interface sending console;

The processing procedure of 2TSE2LINK module is as shown in Figure 3:

Start, enter peek state;

Enter TSE data wait state;

Is data receiver useful signal=1 waited in judgement?

If above formula is set up, have:

In the time that TSE reception data are respectively 0x01,0x03,0x07 and 0x0f, all enter the LINK transmission data length state that obtains;

In the time that TSE reception data are 0x1f, enter the error identification state that sends;

In the time that TSE reception data are 0x3f, enter to send and analyze identification-state;

In the time that TSE reception data are 0x7f, enter the reset signal state that sends;

In the time that TSE reception data are 0x1c, enter and send empty identification-state;

In the time that TSE reception data are 0x1b, enter and send full identification-state;

If when TSE reception data do not meet above-mentioned any condition, return to TSE data wait state;

When entering when obtaining LINK and sending data length state, if data receiver useful signal is high level, have:

In the time that data index value is respectively 0x01,0x03,0x07 and 0x0f, enter respectively LINK0 data and send that state, LINK1 data send state, LINK2 data send state and LINK3 data send state, in passage separately, judge respectively data counts value be whether 0 and data receiver useful signal be high level; If meet above-mentioned condition, be all back to the next step that wait data receiver useful signal is 1 and process; If do not meet above-mentioned condition, return to the data of passage separately and send state;

In the time that data index value is 0x1f, enter the error identification state that sends;

In the time that data index value is 0x3f, enters to send and analyze identification-state;

In the time that data index value is 0x7f, enter the reset signal state that sends;

In the time that data index value is 0x1c, enters and send empty identification-state;

In the time that data index value is 0x1b, enters and send full identification-state;

Judge above-mentioned transmission error identification state, send and analyze identification-state, send reset signal state, send empty identification-state and send whether the completely data receiver useful signal of identification-state is high level, if level, all be back to TSE data wait state, otherwise in the corresponding state being back to separately.

TSE2LINK module is the shared module of I type communication protocols converter and II type communication protocols converter, is responsible for carrying out the conversion operations of Ethernet frame format data to LINK serial protocol data.In the present embodiment, TSE2LIN module interface protocol definition 6 kinds of different input signals, be respectively: the reset signal (rst_n) of Low level effective, work clock signal (clk), the data receiver commencing signal (ff_rx_sop) of TSE module output, the high level active data of TSE module output receives useful signal (ff_rx_dval), LINK module sends the full scale of (TX) FIFO and knows (Full Flag) list signal (link_txfifo_full[3..0]), the reception FPDP ff_rx_d[TSE_fifo_width-1..0 of TSE module].

In the present embodiment, TSE2LINK module interface protocol definition 6 kinds of different output signals, be respectively: high level is effectively exported to the write signal (link_txfifo_wr[3..0]) of 4 transmissions of LINK module (TX) FIFO, high level effectively represents to be ready to the id signal (ff_rx_rdy) of data receiver, error identification signal (Error), analyze id signal (Analyses), reset signal (Reset), be used for writing the data (fifo_rx_data_delay[TSE_fifo_width-1..0]) of LINK module (TX) FIFO.

The operating state of TSE2LINK module is implemented to control by state machine, this state machine has 12 states and forms, be respectively: get first data mode (fetch_data), TSE data wait state (wait_ff_rx_d), obtain the length (get_data_length) that LINK sends data, LINK0 data send state (send_link0_data), LINK1 data send state (send_link1_data), LINK2 data send state (send_link2_data), LINK3 data send state (send_link3_data), send error identification state (send_Error), send and analyze identification-state (send_analyses), send reset signal state (send_reset), send empty identification-state (send_empty), send full identification-state (send_ff_rx_a_full).

TSE2LINK module status machine is carried out flow process as shown in Figure 3.After TSE2LINK module resets, first state machine enters gets first data mode (fetch_data), and output represents that TSE2LINK module has been ready to the high level id signal (ff_rx_rdy) of data receiver, state machine enters TSE data wait state (wait_ff_rx_d) afterwards, waits for that data receiver useful signal (ff_rx_dval) becomes high level; After data receiver useful signal (ff_rx_dval) becomes effectively, state machine can be resolved the data of received packet according to defined data packet format, then state machine jumps to corresponding LINK data transmission state and carries out the transmit operation of LINK data, or jump to corresponding id signal state, carry out the transmit operation of status signal.When executing after LINK data or the transmit operation of signal condition mark, state machine then carries out next Data Analysis and transmit operation, until complete parsing and the transmit operation of a packet, when whole packet is resolved and after transmit operation completes, state machine just enters wait state, to wait for the arrival of next new packet.

3) data that optical fiber communication card sends control desk are processed, and obtain fiber-optic signal and comprise the following steps:

The PCIe bus data that control desk imports into transfers to and in II type communication protocols converter, carries out, after the synthetic and conversion process of data, being sent to fiber optic Ethernet scan control plate by optical fiber transceiving module through fiber medium through PCIe interface;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter takes out serial LINK data, reset mode mark and analysis state mark from back-end data integrator, become LAN protocol data by all transferring to 2LINK2TSE module converts with reset mode mark and analysis state mark after the parallel LINK data of 2LINK module converts one-tenth, by being transferred to fiber optic Ethernet scan control plate by the 2nd optical fiber module through fiber medium after the packing of 2TSE IP kernel module.

The processing procedure of 2LINK2TSE module is identical with 1LINK2TSE module, repeats no more here.

4) fiber-optic signal that fiber optic Ethernet scan control plate imports optical fiber communication card into is processed and is comprised the following steps:

Optical fiber communication card transfers to serial optical optical fiber signaling through fiber medium the 1st optical fiber transceiving module and delivers to and in I type communication protocols converter, carry out the synthetic and conversion process of data, and the data after the synthetic and conversion process of data are delivered to spectrometer system by backplane interface;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

The local area network (LAN) serial data obtaining from the 1st optical fiber transceiving module gone here and there by 1TSE IP kernel module and change send into 1TSE 2LINK module and carry out data protocol conversion, divide and detect LINK data and reset mode mark and analysis state mark, 1LINK module becomes serial LINK data to deliver to backplane interface LINK data decomposition, reset mode mark and analysis state mark are directly delivered to after backplane interface, by backplane interface unification, LINK data, reset mode mark and analysis state mark are transferred to spectrometer system.

The processing procedure of 1TSE2LINK module is identical with 2TSE2LINK module, repeats no more here.

Claims (21)

1. the nuclear magnetic resonance data communication implementation device based on FPGA, it is characterized in that comprising: be placed in fiber optic Ethernet scan control plate and the optical fiber communication card that is placed in control desk in spectrometer system, independently between board, realize interconnected by multimode fiber for two;

Fiber optic Ethernet scan control plate comprises backplane interface, I type communication protocols converter and the 1st optical fiber transceiving module, I type communication protocols converter is communicated and is connected with spectrometer system by backplane interface, carries out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card;

Optical fiber communication card comprises PCIe interface, the 2nd optical fiber transceiving module and II type communication protocols converter, II type communication protocols converter is communicated and is connected with control desk by PCIe interface, carries out transmitted in both directions by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate;

Described I type communication protocols converter is realized by FPGA, there is 1LINK module, 1LINK2TSE module, 1TSE2LINK module, 1TSE IP kernel module and 1CFG_TSE module, wherein 1LINK module is carried out communicating by letter of serial LINK protocol data by backplane interface and spectrometer system, and the LINK protocol data that 1LINK2TSE module receives 1LINK module is connected with 1TSE IP kernel module after converting TSE protocol data to; 1TSE IP kernel module is connected with 1LINK module after converting TSE protocol data to LINK protocol data by 1TSE2LINK module; 1TSE IP kernel module is carried out transmitted in both directions by the 1st optical fiber transceiving module and optical fiber communication card;

1CFG_TSE module is connected with 1TSE IP kernel module, be configured for MAC Address and lan data frame maximum length to 1TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 1TSE IP kernel monitors fiber connection status of optical and changes, need again 1TSE IP kernel module to be configured.

2. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 1, it is characterized in that: described 1LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial LINK data of backplane interface after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to backplane interface by LINK passage simultaneously.

3. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 1, it is characterized in that: under the condition that described 1LINK2TSE module receives in 1LINK module data or error identification in FIFO, the state of analysis, reset mode signal changes, the error identification signal combination that the data fifo that 1LINK module is received and backplane interface transmit becomes LAN data frame format, and sends to 1TSE IP kernel module.

4. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 1, it is characterized in that: 1TSE2LINK module is carried out determined property to the received data of 1TSE IP kernel module, if LINK data write in the transmission FIFO of 1LINK, if analyze or reset mode signal, directly send backplane interface to by status signal lines.

5. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 1, it is characterized in that: described II type communication protocols converter is realized by FPGA, there is 2LINK module, 2LINK2TSE module, 2TSE2LINK module, 2TSE IP kernel module, 2CFG_TSE module and back-end data integrator, wherein back-end data integrator is communicated and is connected with control desk by PCIe interface, and the LINK protocol data that 2LINK2TSE module receives 2LINK module is connected with 2TSE IP kernel module after converting TSE protocol data to; 2TSE IP kernel module is connected with 2LINK module after converting TSE protocol data to LINK protocol data by 2TSE2LINK module; 2TSE IP kernel module is by the 2nd optical fiber transceiving module and fiber optic Ethernet scan control plate transmitted in both directions;

2CFG_TSE module is connected with 2TSE IP kernel module, be configured for MAC Address and lan data frame maximum length to 2TSE IP kernel module, control configuration flow by a state machine, after configuration completes, if 2TSE IP kernel monitors fiber connection status of optical and changes, need again 2TSE IP kernel module to be configured.

6. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 5, it is characterized in that: described 2LINK module has four groups of independently LINK passage and reception FIFO and transmission FIFO, changed into from the serial data of back-end data integrator after the parallel data of 8 and be written to and receive in FIFO, the data that are sent in FIFO are sent to back-end data integrator by LINK passage simultaneously.

7. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 5, it is characterized in that: described 2LINK2TSE module receives and has in FIFO under the condition that the state of data or error identification signal changes in 2LINK module, the analysis that the data fifo that 2LINK module is received and back-end data integrator transmit becomes LAN data frame format with reset mode signal combination, and sends to 2TSE IP kernel module.

8. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 5, it is characterized in that: described 2TSE2LINK module is carried out determined property to the received data of 2TSE IP kernel module, if LINK data write in the transmission FIFO of 2LINK, if error identification status signal directly sends back-end data integrator to by status signal lines.

9. by the nuclear magnetic resonance data communication implementation device based on FPGA claimed in claim 5, it is characterized in that: described back-end data integrator is carried out on the one hand by the error identification from 2TSE2LINK module with from the LINK data of 2LINK module and LINK passage sky/full scale is known and whether PCIe packet is ready to identify the operation that sends to PCIe interface module; On the other hand according to received data attribute, by LINK data and reset signal and analytical signal interpretation out, and send to respectively 2LINK module and 2LINK2TSE module.

10. the nuclear magnetic resonance data communication implementation method based on FPGA, is characterized in that comprising the following steps:

Receive respectively the data of spectrometer system and control desk transmission by fiber optic Ethernet scan control plate and optical fiber communication card;

Fiber optic Ethernet scan control plate and the optical fiber communication card data that pair spectrometer system and control desk send simultaneously are respectively processed, and obtain fiber-optic signal separately;

The fiber-optic signal that fiber optic Ethernet scan control plate obtains self exports optical fiber communication card to through fiber medium; The fiber-optic signal that the card of optical fiber communication simultaneously obtains self through fiber medium exports fiber optic Ethernet scan control plate to;

The fiber-optic signal that optical fiber communication card imports fiber optic Ethernet scan control plate into is sent to control desk after processing; The fiber-optic signal that fiber optic Ethernet scan control plate imports optical fiber communication card into is simultaneously sent to spectrometer system after processing;

The described data that send in fiber optic Ethernet scan control plate pair spectrometer system are processed and are comprised the following steps:

The data that spectrometer system sends are delivered to by backplane interface and in the I type communication protocols converter of fiber optic Ethernet scan control plate, are carried out being sent to the 1st optical fiber transceiving module after the synthetic and conversion process of data, form serial optical optical fiber signaling, transfer to optical fiber communication card through fiber medium;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

I type communication protocols converter receives LINK data and the error condition mark that backplane interface is imported into;

LINK data transfer to 1LINK2TSE module by 1LINK module, and error condition mark directly transfers to 1LINK2TSE module;

1LINK2TSE module is integrated into local area network (LAN) formatted data by the LINK data of above-mentioned reception and error condition mark and after 1TSE IP kernel module is carried out parallel-serial conversion, is sent to the 1st optical fiber transceiving module.

11. by the nuclear magnetic resonance data communication implementation method based on FPGA claimed in claim 10, it is characterized in that the processing procedure of described 1LINK2TSE module is as follows:

Start, enter idle condition;

Judged whether LINK data inputs, or whether status signal changes or first executing state machine change;

If meet one of above-mentioned three conditions, enter data packet head and send state;

Judge whether executing state machine first, in this way, enter index mark transmission state;

In the time that index is designated 0x1f, enter error identification and send state, return to index mark transmission state;

In the time that index is designated 0x3f, enter and analyze mark transmission state, return to index mark transmission state;

In the time that index is designated 0x7f, enter the mark transmission state that resets, return to index mark transmission state;

In the time that index is designated 0x1c, enter the empty mark of FIFO transmission state, return to index mark transmission state;

In the time that index is designated 0x1b, enter FIFO full scale and know transmission state, return and wait for a clock cycle state, then enter idle condition.

12. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 11, it is characterized in that: if not executing state machine first, judged whether LINK data;

If there are LINK data, enter LINK index and send state, then enter data length and send state;

In the time that index is designated 0x01, enters LINK0 channel data and send state;

In the time that index is designated 0x03, enters LINK1 channel data and send state;

In the time that index is designated 0x07, enters LINK2 channel data and send state;

If when the state of above-mentioned index mark is all false, enters LINK3 channel data and send state.

13. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 12, it is characterized in that:

In the time entering LINK0 channel data transmission state, judge whether the quantity that sends data equals 0x01;

If be not equal to, returned to LINK0 channel data and send state;

If equaled, judge whether LINK1, LINK2, LINK3 passage have data; If there are data, return to LINK index and send state; If there is no data, go to index mark transmission state.

14. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 12, it is characterized in that:

In the time entering LINK1 channel data transmission state, judge whether the quantity that sends data equals 0x01;

If be not equal to, returned to LINK1 channel data and send state;

If equaled, judge whether LINK2, LINK3 passage have data; If there are data, return to LINK index and send state; If there is no data, go to index mark transmission state.

15. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 12, it is characterized in that:

In the time entering LINK2 channel data transmission state, judge whether the quantity that sends data equals 0x01;

If be not equal to, returned to LINK2 channel data and send state;

If equaled, judge whether LINK3 passage has data; If there are data, return to LINK index and send state; If there is no data, go to index mark transmission state.

16. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 12, it is characterized in that:

In the time entering LINK3 channel data transmission state, judge whether the quantity that sends data equals 0x01;

If equation is false, returns to LINK3 channel data and send state;

If equation is set up, go to index mark transmission state.

17. by the nuclear magnetic resonance data communication implementation method based on FPGA claimed in claim 10, it is characterized in that: the fiber-optic signal that described optical fiber communication card imports fiber optic Ethernet scan control plate into comprises the following steps after processing:

The fiber data that fiber optic Ethernet scan control plate sends through fiber medium is sent to PCIe interface after carrying out the synthetic and conversion process of data during optical fiber transceiving module is delivered to the II type communication protocols converter of optical fiber communication card, form PCIe bus data, be uploaded to control desk;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter receives LAN data and the error condition mark imported into from the 2nd optical fiber module;

LAN data carries out data by the transmission of 2TSE IP kernel module and unpacks, carry out the conversion of LAN data agreement to LINK protocol data by 2TSE2LINK module, and the go-on-go status indicator that makes mistake, the LINK protocol data of changing out is sent to 2LINK module and becomes serial LINK data to deliver to back-end data integrator through 2LINK module converts, the go-on-go status indicator that makes mistake is directly sent to back-end data integrator, back-end data integrator by after error condition mark and serial LINK Data Integration through PCIe interface sending console.

18. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 17, it is characterized in that: the processing procedure of described 2TSE2LINK module is as follows:

Start, enter peek state;

Enter TSE data wait state;

Judge and wait for whether data receiver useful signal equals 1;

If equaled, have:

In the time that TSE reception data are respectively 0x01,0x03,0x07 and 0x0f, all enter the LINK transmission data length state that obtains;

In the time that TSE reception data are 0x1f, enter the error identification state that sends;

In the time that TSE reception data are 0x3f, enter to send and analyze identification-state;

In the time that TSE reception data are 0x7f, enter the reset signal state that sends;

In the time that TSE reception data are 0x1c, enter and send empty identification-state;

In the time that TSE reception data are 0x1b, enter and send full identification-state;

If when TSE reception data do not meet above-mentioned any condition, return to TSE data wait state.

19. by the nuclear magnetic resonance data communication implementation method based on FPGA described in claim 18, it is characterized in that: when entering when obtaining LINK and sending data length state, if data receiver useful signal is high level, have:

In the time that data index value is respectively 0x01,0x03,0x07 and 0x0f, enter respectively LINK0 data and send that state, LINK1 data send state, LINK2 data send state and LINK3 data send state, in passage separately, judge respectively data counts value be whether 0 and data receiver useful signal be high level; If meet above-mentioned condition, be all back to the next step that wait data receiver useful signal is 1 and process; If do not meet above-mentioned condition, return to the data of passage separately and send state;

In the time that data index value is 0x1f, enter the error identification state that sends;

In the time that data index value is 0x3f, enters to send and analyze identification-state;

In the time that data index value is 0x7f, enter the reset signal state that sends;

In the time that data index value is 0x1c, enters and send empty identification-state;

In the time that data index value is 0x1b, enters and send full identification-state;

Judge above-mentioned transmission error identification state, send and analyze identification-state, send reset signal state, send empty identification-state and send whether the completely data receiver useful signal of identification-state is high level, if high level, all be back to TSE data wait state, otherwise in the corresponding state being back to separately.

20. by the nuclear magnetic resonance data communication implementation method based on FPGA claimed in claim 10, it is characterized in that: the data that described optical fiber communication card sends control desk are processed, and obtain fiber-optic signal and comprise the following steps:

The PCIe bus data that control desk imports into transfers to and in II type communication protocols converter, carries out, after the synthetic and conversion process of data, being sent to fiber optic Ethernet scan control plate by optical fiber transceiving module through fiber medium through PCIe interface;

Describedly in II type communication protocols converter, carry out that data are synthetic and translation process is as follows:

II type communication protocols converter takes out serial LINK data, reset mode mark and analysis state mark from back-end data integrator, become LAN protocol data by all transferring to 2LINK2TSE module converts with reset mode mark and analysis state mark after the parallel LINK data of 2LINK module converts one-tenth, by being transferred to fiber optic Ethernet scan control plate by the 2nd optical fiber module through fiber medium after the packing of 2TSE IP kernel module.

21. by the nuclear magnetic resonance data communication implementation method based on FPGA claimed in claim 10, it is characterized in that: the fiber-optic signal that described fiber optic Ethernet scan control plate imports optical fiber communication card into is processed and comprised the following steps:

Optical fiber communication card transfers to serial optical optical fiber signaling through fiber medium the 1st optical fiber transceiving module and delivers to and in I type communication protocols converter, carry out the synthetic and conversion process of data, and the data after the synthetic and conversion process of data are delivered to spectrometer system by backplane interface;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

The local area network (LAN) serial data obtaining from the 1st optical fiber transceiving module gone here and there by 1TSE IP kernel module and change send into 1TSE2LINK module and carry out data protocol conversion, divide and detect LINK data and reset mode mark and analysis state mark, 1LINK module becomes serial LINK data to deliver to backplane interface LINK data decomposition, reset mode mark and analysis state mark are directly delivered to after backplane interface, by backplane interface unification, LINK data, reset mode mark and analysis state mark are transferred to spectrometer system;

The data that fiber optic Ethernet scan control plate pair spectrometer system sends are processed and are comprised:

The data that spectrometer system sends are delivered to by backplane interface and in the I type communication protocols converter of fiber optic Ethernet scan control plate, are carried out being sent to the 1st optical fiber transceiving module after the synthetic and conversion process of data, form serial optical optical fiber signaling, transfer to optical fiber communication card through fiber medium;

Describedly carry out at I type communication protocols converter that data are synthetic and translation process is as follows:

I type communication protocols converter receives LINK data and the error condition mark that backplane interface is imported into;

LINK data transfer to 1LINK2TSE module by 1LINK module, and error condition mark directly transfers to 1LINK2TSE module;

1LINK2TSE module is integrated into local area network (LAN) formatted data by the LINK data of above-mentioned reception and error condition mark and after 1TSE IP kernel module is carried out parallel-serial conversion, is sent to the 1st optical fiber transceiving module.