CN106303759B - A kind of high speed serialization transceiver interface and its working method based on FPGA - Google Patents
A kind of high speed serialization transceiver interface and its working method based on FPGA Download PDFInfo
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Abstract
The present invention relates to a kind of high speed serialization transceiver interface and its working method based on FPGA.The interface is used for the conversion of parallel data and serial data, comprising: the end Custom MAC, the end Custom IP；The end the Custom MAC, for carrying out parallel data transmitting-receiving with the end the Custom IP；The end the Custom IP, for carrying out serial data transmitting-receiving with the opposite end end Custom IP；The end the Custom IP and the end opposite end Custom IP are connected with each other by coaxial cable.The high speed serialization transceiver interface is based on FPGA technology, and the circuit of realization is pure hardware circuit；It is small to occupy hardware space；Data transparent transmission may be implemented；By the multiplexing in the channel PHY, has certain extended capability；Environmental suitability is strong, and stability is high.
Description
Technical field
The present invention relates to interfacing field more particularly to a kind of high speed serialization transceiver interfaces and its work based on FPGA
Method.
Background technique
Traditional data transceiver interface can be divided into parallel interface and two kinds of serial line interface, and parallel interface transmission speed is fast, single
Position time information amount is big, but the demand to hardware resource is big；Serial line interface is low to hardware resource requirements but rate is relatively slow.With
The development of science and technology, requirement of the people to information processing and transmission is higher and higher, how to meet the requirement of resource and rate simultaneously
Increasingly paid attention to by industry, various improved serial line interfaces come into being.
Serial line interface general at present mainly has the data-interfaces such as USB, SATA, PCI-E, RapidIO, SDI, wherein；
USB 3.0 is to increase 4 on the basis of 4 cable architecture of data line (power supply, ground wire, 2 datas) of USB2.0
Route, for receiving and transmitting signal, bus bandwidth is up to 5.0Gbps full duplex, due to increasing 4 routes, USB's 3.0
Cable can more " thickness ", while being limited to mainboard interface, storage medium；
3.0 bus bandwidth of SATA is promoted to 6Gbps, but needs the support of hardware chip；
3.0 bus bandwidth of PCI-E has reached 10Gbps, but PCI-E interface agreement is huge, hardware interface area occupied
Greatly, some application scenarios are not suitable for, and are mainly used for hard disk and video card interface；
RapidIO 2.x standard supports the transmission rate of 5GHz and 6.25GHz, but is the interconnection based on packet-switching
Architecture, configuration is complicated, is mainly used in embedded system intraconnection, supports chip to chip, plate to the communication between plate,
Mainly as backboard (Backplane) connection of embedded device, it is suitable for bursty communication, is not suitable for long message, session
The communication of formula；
SDI interface is transmitted using coaxial cable, and hardware configuration is succinct, and SDI interface can pass through the serial digital of 270Mbps point
Amount signal can transmit the signal of 360Mbps, but SDI interface is to aim to establish digital audio/video net for 16:9 format-pattern
Network and design, using synchronizing network technology, use Handshake Protocol like that rather than computer network.
As it can be seen that above-mentioned existing serial line interface there is the equilibrium problem between the elements such as space, cost, ability, scalability with
And the restricted problem of application field.Therefore, it is necessary to one kind to compare other existing serial line interfaces, and cost is suitable, performance is high, hardware accounts for
With space is small, to packet conveying length, there is no limit, while all better data transmit-receive of stability, scalability, maintainability etc.
Interface.
Summary of the invention
In view of above-mentioned analysis, the present invention is intended to provide a kind of high speed serialization transceiver interface and its work side based on FPGA
Method, to solve balance of the existing HSSI High-Speed Serial Interface data transceiver interface between the elements such as space, cost, ability, scalability
Problem.
The purpose of the present invention is mainly achieved through the following technical solutions:
A kind of high speed serialization transceiver interface based on FPGA, the interface are used for the conversion of parallel data and serial data,
It include: the end Custom MAC, the end Custom IP；It is characterized in that,
The end the Custom MAC, for carrying out parallel data transmitting-receiving with the end the Custom IP；
The end the Custom IP, for carrying out serial data transmitting-receiving with the opposite end end Custom IP；
The end the Custom IP and the end opposite end Custom IP are connected with each other by coaxial cable.
Wherein, the every coaxial cable is as a channel；The end each Custom IP transmitting-receiving both direction respectively possesses most
More 32 channels.
Wherein, the end Custom MAC includes: to transmit/receive buffer area FIFO, IP kernel initialization and configuration circuit, bell idles self-test
Circuit, step-out restore that circuit, transmitting-receiving parallel drive circuit, channel is protected to entangle a yard circuit, overtime protection circuit.
Wherein, IP kernel initialization and configuration circuit are used for: being powered on and carried out reset and initialization operation to IP kernel, to register
Carry out parameter configuration；Initialization front and back carries out block protection to channel.
Wherein, transmitting-receiving parallel drive circuit includes hair parallel drive circuit and receipts parallel drive circuit；Generate parallel drive electricity
Data in hair caching FIFO are increased feature field according to channel parallel data bit width by road, then by using PHY core to provide
Transmitted in parallel clock is transported in PHY core parallel entry；Parallel drive circuit is received to mention the parallel outlet data of PHY core with PHY core
The parallel reception clock supplied is to entangle a yard module with reference to feeding channel, and caching FIFO is received in write-in after processing, for outside extraction.
Wherein, the end Custom IP includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer.
Wherein, PCS Physical Coding Sublayer is responsible for 8b/10b coding and CRC check, and be integrated with responsible channel binding and
The modified elastic buffer of clock.
Wherein, PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data
Stream.
A kind of data transmission method for uplink of the high speed serialization transceiver interface based on FPGA, which comprises the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；
Step 2: the end Custom MAC receives data from outside, transmitted in parallel gives the end Custom IP；
Step 3: the end Custom IP receives parallel data, and serial data stream is converted to, is sent by FPGA transceiver
To opposite end FPGA transceiver.
The Custom IP kernel initialization further comprises:
1.1, IP kernel initialization and configuration circuit power on, and Custom IP kernel is resetted and initialized；In reset and just
Channel guard is carried out during beginningization；
1.2, after the initialization of the end Custom IP, the real-time self-test of bell idles and correction are carried out.
It the real-time self-test of the bell idles and corrects and includes:
When there are data, data are received；When no data, self-test is carried out, idle self demarking code is received, monitors channel free time shape
Whether state is abnormal；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if
Whether further monitoring data transmission is abnormal；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue if data transmission is normal
Data are sent until completing this data receiver；
Self-test is carried out again after completing this data receiver, is repeated the above steps.
The step of data transmission method for uplink of the high speed serialization transceiver interface based on FPGA two, further comprises:
The end Custom MAC passes through FPGA inner peripheral logic from host receiving data；
It transmits/receives buffer area fifo module and writes enabled, the write-in of the data received from host is transmitted/received into buffer area FIFO mould
Block；
Hair parallel drive circuit increases the data transmitted/received in buffer area fifo module according to channel parallel data bit width special
Field is levied, the parallel entry at the end Custom IP is then sent to by the transmitted in parallel clock that the end Custom IP provides.
The step of data transmission method for uplink of the high speed serialization transceiver interface based on FPGA three, further comprises:
PCS Physical Coding Sublayer carries out 8B/10B transformation to the parallel data received；
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data stream and passes through
Coaxial cable is sent.
A kind of data receiver method of the high speed serialization transceiver interface based on FPGA, which comprises the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；
Step 2: the end Custom IP receives serial data stream from the opposite end end Custom IP by FPGA transceiver；It will connect
The converting serial data streams received are parallel data, and are sent to the end Custom MAC；
Step 3: the end Custom MAC receives data from the end Custom IP parallel, it is sent to outside.
The Custom IP kernel initialization further comprises:
1.1, IP kernel initialization and configuration circuit power on, and Custom IP kernel is resetted and initialized；In reset and just
Channel guard is carried out during beginningization；
1.2, after the initialization of the end Custom IP, the real-time self-test of bell idles and correction are carried out.
It the real-time self-test of the bell idles and corrects and includes:
When there are data, data are received；When no data, self-test is carried out, idle self demarking code is received, monitors channel free time shape
Whether state is abnormal；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if
Whether further monitoring data transmission is abnormal；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue if data transmission is normal
Data are sent until completing this data receiver；
Self-test is carried out again after completing this data receiver, is repeated the above steps.
The step of data receiver method of the high speed serialization transceiver interface based on FPGA two, further comprises:
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
It is exported parallel by PHY core and sends data；
The step of data receiver method of the high speed serialization transceiver interface based on FPGA three, further comprises:
The transmitted in parallel clock that parallel drive output circuit is provided with the end Custom IP is received to go out parallel for reference from PHY core
Mouth receives parallel data；It is sent into channel and entangles a yard circuit；
Channel is entangled yard circuit and is handled the parallel data；Interchannel is solved due to arrival time sequence and when sending
It is inconsistent and there is the problem of randomness；
It transmits/receives buffer area fifo module and writes enabled, the write-in of treated data is transmitted/received into buffer area fifo module；
The end Custom MAC sends data to host by FPGA inner peripheral logic.
The present invention has the beneficial effect that:
The interface is based on FPGA technology, and the circuit of realization is that (FPGA can do auxiliary activities logic simultaneously to pure hardware circuit
Processing)；It is small to occupy hardware space；Data transparent transmission may be implemented；By the multiplexing in the channel PHY, there is certain propagation energy
Power；Environmental suitability is strong, and stability is high.
Other features and advantages of the present invention will illustrate in the following description, also, partial become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by written explanation
Specifically noted structure is achieved and obtained in book, claims and attached drawing.
Detailed description of the invention
Attached drawing is only used for showing the purpose of specific embodiment, and is not to be construed as limiting the invention, in entire attached drawing
In, identical reference symbol indicates identical component.
Fig. 1 is the high speed serialization transceiver interface hardware macrostructure figure disclosed by the embodiments of the present invention based on FPGA；
Fig. 2 is the high speed serialization transceiver interface system composed structure schematic diagram disclosed by the embodiments of the present invention based on FPGA；
Fig. 3 is the high speed serialization transceiver interface modular structure schematic diagram disclosed by the embodiments of the present invention based on FPGA.
Fig. 4 be the high speed serialization transceiver interface initialization procedure disclosed by the embodiments of the present invention based on FPGA in self-test with
Selfreparing flow chart；
Fig. 5 is error correction stream in channel in the high speed serialization transceiver interface receive process disclosed by the embodiments of the present invention based on FPGA
Cheng Tu.
Specific embodiment
Specifically describing the preferred embodiment of the present invention with reference to the accompanying drawing, wherein attached drawing constitutes the application a part, and
Together with embodiments of the present invention for illustrating the principle of the present invention.
Abbreviation and Key Term definition
Customize PHY (Custom PHY, a kind of IP kernel, the customizable ethernet PHY transceiver used)；
PCS (PHYsical Coding Sublayer, Physical Coding Sublayer)；
PMA (PHYsical Medium Attachment, physical media adaptation layer).
A specific embodiment according to the present invention discloses a kind of high speed serialization transceiver interface based on FPGA, described
Interface realizes the conversion of parallel data and serial data, comprising: the end Custom MAC, the end Custom IP；Wherein,
The end the Custom MAC, for carrying out parallel data transmitting-receiving with the end the Custom IP；
The end the Custom IP, for carrying out serial data transmitting-receiving with the opposite end end Custom IP；
The end the Custom IP and the end opposite end Custom IP are connected with each other by coaxial cable；Every coaxial cable conduct
One serial-port；The end each Custom IP transmitting-receiving both direction respectively possesses most 32 channels, each channel supports 8,16,
The bit width modes such as 32bit, single channels maximum capacity 3.125Gbit.
In the present embodiment, the interface has 6 times of extended capabilities, and by configuring the value of lanes (number of vias), (1 to 6 is whole
Number), while configuring single pass bit width mode, then parallel port bit wide is " port number is multiplied by single channel bit width values ", is gone here and there simultaneously
Row port number is lanes (port number).
The end the Custom IP is customization PHY, is internally provided with the work that a source clock compensation drives all cascade channels
Make mode.Each service aisle is actually independent, bundles and significantly improves the total capacity of macroscopic path.After cascade
Phy interface ability to work 10,000,000,000 from 0 to 2 between ladder it is adjustable, and reflect to the only area Tiao Shuo of coaxial cable on hardware circuit
Not, serial line interface need to be only reserved according to the planning of extension, subsequent upgrade does not need redesign hardware can be to letter
Road ability is promoted, and consumption and development cycle are reduced costs.The ability that can according to need in actual use to module into
The corresponding configuration of row, hardware environment only increase and decrease number of coaxial cables, remaining operation is programmed by FPGA to be realized, operation letter
Victory, the development cycle is short, significant effect.
As shown in figure 3, the end the Custom MAC include: transmit/receive buffer area FIFO, IP kernel initialization and configuration circuit,
Bell idles self-checking circuit, step-out restore that circuit, transmitting-receiving parallel drive circuit, channel is protected to entangle a yard circuit, overtime protection circuit；Its
In,
Transmitting-receiving caching FIFO mainly has two big functions: first is that clock domain separation, because of the clock frequency of application and height
There may be differences for quick access mouth setting input frequency, and increasing transmitting-receiving caching FIFO can not be influenced by cross clock domain.Second is that buffering
Data facilitate and carry out the operation of the frames such as feature head insertion, can increase data transmission guarantee ability.
IP kernel initialization and configuration circuit: reset and initialization operation are carried out to IP kernel first is that powering on, to necessary register
Carry out parameter configuration；Second is that the block that initialization front and back carries out a period of time to channel is protected, generally 2 seconds.
Bell idles self-checking circuit: after system initialization, bell idles self-checking circuit start it is non-to channel use the time
Section cycles through hexadecimal " BC " bell idles, while veritifying idle code word in receiving end channel non-use periods, is returning to code word just
Normal and abnormal two states.
Step-out restores protection circuit: when bell idles detection is returned as abnormality, starting step-out restores protection circuit, right
Entire high-speed interface driving and customization PHY core are quickly reset, and automatic guarantee channel restores normal.(experiment shows that channel is different
Normal state possibly always is present at startup stage, does not occur step-out after starting is normal, step-out, which restores protection circuit, to be had
The normal starting of guarantee channel is imitated, while can be supported to provide insurance during working normally.)
Receive and dispatch parallel drive circuit: hair is cached the number in FIFO according to channel parallel data bit width by hair parallel drive circuit
According to feature field is increased, then it is transported in PHY core parallel entry by the transmitted in parallel clock for using PHY core to provide；It receives parallel
The parallel reception clock that the parallel outlet data of PHY core is provided with PHY core is to entangle a yard module with reference to feeding channel by driving circuit, is located
Caching FIFO is received in write-in after reason, is extracted for outside.
A yard circuit is entangled in channel: mainly solve interchannel due to arrival time sequence and send when it is inconsistent and have randomness
The problem of.
Overtime protection circuit: mainly assuming that channel keeps state in transmission for a long time, is more than setting time, it is believed that high speed
There is a kind of special state in channel, i.e. channel externally shows as occupied always and refuses to receive new frame, which originates from
In start-up course.Since the state can weaken the monitoring dynamics of bell idles detection circuit, it is subject to so needing to be arranged time-out time
Protection occurs time-out and handles by abnormal conditions, starts Restoration Mechanism.Time-out time needs designer according to the practical feelings of application environment
Condition setting, if you need to then need to cancel again after the completion of Initial Channel Assignment blocks the 2 second time of protection using channel with pattern of traffic
Overtime protection circuit.
The end the Custom IP includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer；Wherein,
PCS Physical Coding Sublayer is responsible for 8b/10b coding, avoids occurring the case where even 0 company 1 in data flow, convenient for clock
Restore.PCS Physical Coding Sublayer carries out 8B/10B transformation to the parallel data received；Every 8bit increases the error-detecging code of 2bit；
One of the characteristic of 8B/10B transformation is ensuring that DC balance, that is, the quantity of " 0 " and " 1 " is basic in binary data stream after encoding
It is consistent, because of (i.e. so-called long even 0 He when the logic 1 and logical zero of high speed serialization stream have multiple positions not generate variation
It is long even 1), the conversion of signal will because of voltage position rank relationship and cause signal error, DC balance can overcome this to ask
Topic.When transformation, continuous " 0 " perhaps be must be inserted into after " 1 " quantity is no more than 5 i.e. every 5 continuous " 0 " or " 1 "
One " 1 " or " 0 ", to guarantee that signal DC is balanced.It can guarantee that serial data can correctly be restored in receiving end in this way,
Receiving end can also be helped to carry out recovery operation using special code (K code) simultaneously, and can be transmitted in early detection data bit
Mistake inhibits mistake to continue to occur.
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data stream and passes through
Coaxial cable is sent；The function of judgement and carrier sense to link state is provided.
In the present embodiment, PCS and PMA are realized by hardware logic, and the entire IP kernel part for customizing PHY has used about 1%
FPGA resource.
A specific embodiment according to the present invention, discloses the high speed serialization transceiver interface described in one kind based on FPGA
Data send working method, comprising the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；
Specifically, as shown in figure 4,
The initialization of Custom IP kernel further comprises:
1.1, IP kernel initialization and configuration circuit power on, and Custom IP kernel is resetted and initialized；In reset and just
Channel guard is carried out during beginningization；
Firstly, it is necessary to which the entrance and exit at the end Custom IP increases protection, the unwanted data of real system are filtered
Fall, excludes communicating pair and receive the mistake response that extraneous data in turn results in；
Secondly as customization PHY has the preparation process of a very short time after the completion of resetting, but for high-speed interface
This time cannot be ignored, and need to have it simple protective；
Wherein, during reset and initialization carry out channel guard further comprise:
The block that IP kernel initialization and configuration circuit do a period of time to channel parallel outlet after system starting resets is protected
Shield generally 2 seconds, improves PHY initialization stability and initial synchronisation ability；
1.2, after the initialization of the end Custom IP, when for booting the communicating pair end Custom IP start asynchronous problem into
The real-time self-test of row bell idles and correction；
When there are data, data are sent；When no data, self-test is carried out, idle self demarking code is sent, monitors channel free time shape
Whether state is abnormal；Specifically, bell idles self-checking circuit cycles through hexadecimal " BC " to the non-usage time interval of channel in originator
Bell idles, while according to the normal and abnormal two states of the code word that the bell idles self-checking circuit of receiving end channel returns；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if
Whether further monitoring data transmission is abnormal；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue if data transmission is normal
Data send until completing this data and send；
It completes to carry out self-test again after this data is sent, repeat the above steps.
Reparation problem can be used there are many means, such as the detection of real-time bell idles and real time data status monitoring etc.,
Interface real-time status, the necessary means for the first time anti symptom treatment that notes abnormalities effectively are grasped, this means are used in various logical
The survival ability of equipment can be greatly improved among letter system.
When channel keeps state in transmission for a long time, more than setting time, then it is assumed that special state, i.e. channel pair occur
It shows as outside occupied always and refuses to receive new frame, which originates from start-up course.Since the state can weaken bell idles
The monitoring dynamics of detection circuit is protected so needing to be arranged time-out time, and time-out occurs and then handles by abnormal conditions, starting
Repair mechanism.Time-out time needs designer to be set according to application environment actual conditions, if you need to use channel with pattern of traffic
It then needs to cancel overtime protection circuit again after the completion of Initial Channel Assignment blocks the 2 second time of protection.
Step 2: the end Custom MAC receives data from outside, transmitted in parallel gives the end Custom IP；Specifically,
The end Custom MAC passes through FPGA inner peripheral logic (such as PCI/PCIE interface) from host receiving data；
It transmits/receives buffer area fifo module and writes enabled, the write-in of the data received from host is transmitted/received into buffer area FIFO mould
Block；Buffer area fifo module buffered data is transmitted/received, facilitates the first-class frame operation of insertion feature to carry out, increases data transmission guarantee energy
Power；Transmission feature head is defined, filters out the hash in channel in conjunction with envelope, improves interface service efficiency and reduce failure
Existing probability.It is inserted into when transmission, determines when reception to use；It is the screening in receiving end to data that feature head, which adds envelope to filter out hash,
Link, it is therefore an objective to prevent non-user protocol data from reaching and receive terminal, influence terminal processes process.
Hair parallel drive circuit increases the data transmitted/received in buffer area fifo module according to channel parallel data bit width special
Field is levied, is then sent to entering parallel for the end Custom IP (i.e. PHY core) by the transmitted in parallel clock that the end Custom IP provides
Mouthful；
Step 3: the end Custom IP receives parallel data, and serial data stream is converted to, is sent by FPGA transceiver
To opposite end FPGA transceiver.
Specifically, PCS Physical Coding Sublayer is responsible for 8b/10b coding and CRC check, and is integrated with responsible channel binding
With the modified elastic buffer of clock.Can be to avoid there is the case where even 0 company 1, convenient for the extensive of clock in 8b/10b coding in data flow
It is multiple.PCS Physical Coding Sublayer carries out 8B/10B transformation to the parallel data received；Every 8bit increases the error-detecging code of 2bit；8B/
One of the characteristic of 10B transformation is ensuring that DC balance, that is, the quantity of " 0 " and " 1 " is protected substantially in binary data stream after encoding
It holds unanimously, because (i.e. so-called length connects 0 and length when the logic 1 and logical zero of high speed serialization stream have multiple positions not generate variation
Even 1), signal conversion will because of voltage position rank relationship and cause signal error, DC balance can overcome this problem.
When conversion, continuous " 0 " perhaps must be inserted into one after " 1 " quantity is no more than 5 i.e. every 5 continuous " 0 " or " 1 "
Position " 1 " or " 0 ", to guarantee that signal DC is balanced.It can guarantee that serial data can correctly be restored in receiving end in this way, together
Shi Liyong special code (K code) can also help receiving end to carry out recovery operation, and can transmit in early detection data bit wrong
Accidentally, mistake is inhibited to continue to occur.
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data stream, passes through
Coaxial cable is sent；The function of judgement and carrier sense to link state is provided.
Another specific embodiment according to the present invention discloses a kind of number of high speed serialization transceiver interface based on FPGA
According to reception working method, comprising the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；Specifically,
As shown in figure 4, the initialization of Custom IP kernel further comprises:
1.1, IP kernel initialization and configuration circuit power on, and Custom IP kernel is resetted and initialized；In reset and just
Channel guard is carried out during beginningization；
Firstly, it is necessary to which the entrance and exit at the end Custom IP increases protection, the unwanted data of real system are filtered
Fall, excludes communicating pair and receive the mistake response that extraneous data in turn results in；
Secondly as customization PHY has the preparation process of a very short time after the completion of resetting, but for high-speed interface
This time cannot be ignored, and need to have it simple protective；
Wherein, channel guard is carried out during reset and initialization further comprises:
The block that IP kernel initialization and configuration circuit do a period of time to channel parallel outlet after system starting resets is protected
Shield generally 2 seconds, improves PHY initialization stability and initial synchronisation ability；
1.2, after the initialization of the end Custom IP, when for booting the communicating pair end Custom IP start asynchronous problem into
The real-time self-test of row bell idles and correction；
When there are data, data are received；When no data, self-test is carried out, idle self demarking code is received, monitors channel free time shape
Whether state is abnormal；Specifically, it receives opposite end bell idles self-checking circuit and hexadecimal is cycled through to the non-usage time interval of channel
" BC " bell idles, while bell idles self-checking circuit returns to the normal and abnormal two states of code word to opposite end；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if
Whether further monitoring data transmission is abnormal；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue if data transmission is normal
Data are sent until completing this data receiver；
Self-test is carried out again after completing this data receiver, is repeated the above steps.
Reparation problem can be used there are many means, such as the detection of real-time bell idles and real time data status monitoring etc.,
Interface real-time status is effectively grasped, notes abnormalities and handles at the first time, the survival ability of equipment can be improved.
When channel keeps state in reception for a long time, more than setting time, then it is assumed that a kind of special state occur, that is, believe
Road externally shows as occupied always and refuses to receive new frame.Since the state can weaken the monitoring force of bell idles detection circuit
Degree occurs time-out and handles by abnormal conditions, start repair mechanism so setting time-out time is protected.Time-out time according to
Application environment actual conditions setting, if you need to then be needed using channel with pattern of traffic when Initial Channel Assignment blocks protection 2 seconds
Between after the completion of cancel overtime protection circuit again.
It is flowed to Step 2: the end Custom IP receives serial data from the opposite end end Custom IP by FPGA external transceiver
FPGA internal transceiver；It is parallel data by the converting serial data streams received, and is sent to the end Custom MAC；Specifically
Ground,
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
It is exported parallel by PHY core and sends data；
Wherein, the serial data received is converted to parallel data by the end Custom IP, and is sent to Custom MAC
End further comprises:
Since channel arranges irregular, to handle using High-Speed Hardware advantage under multibyte bit width mode between byte data
Realize that fully intermeshing is handled to it, the recombination of data is mainly carried out according to each number of subchannels in channel according to the time order and function of appearance；Together
When relatively independent situation between the byte that multibyte bit wide macroscopically shows referred to due to the subchannel, i.e., it is a kind of virtual
Call.Due to PHY core receiving end decoding after using byte as unit parallel output information, single channel fictionalized it is several son lead to
Road comes.The byte envelope of each subchannel is relatively independent, is integrated into multibyte bit wide and needs to construct corresponding new data later
Effective envelope.
Such as: data send the preceding field X " 11223344 " for a bit wide 32, reach opposite end decoding by high-speed interface
After obtain X " BCBC3344 ", X " 1122BCBC " (note: BC is idle self demarking code, is likely to occur 16 kinds of combinations herein)；By extensive
Compound circuit recovers supply rear class for originating data is errorless, at the same the envelope that needs of rear class also must operation obtain.
In addition to registration operations, restores the combined operation of originator and be based on combinational circuit real-time operation, as shown in figure 5,
Step 1: the data that high-speed interface inputs being deposited into 1 clock cycle by channel respectively, are used for data recombination；Together
When, channel envelope is deposited into 1 clock cycle in a register；
Step 2: being to be recombinated with reference to registered data sorts with corresponding channel envelope arrival time, data are posted after recombination
It deposits, obtains corresponding envelope after waiting envelope operation；
Step 3: checking the envelope value in primary each channel original envelope value and register, in each clock cycle T with total
Line data mode checks (the corresponding bit in each channel)；Such as when 4 channel, former envelope value is only distinguished to be had completely without effect with non-entirely
Two kinds of situations are imitated, register envelope value there are 16 kinds.2 kinds of former envelope values and 16 kinds of register envelope values are done into combination judgement: original packet
When network value is completely without effect and entirely effective register envelope value, output envelope value is any channel register envelope value；Former envelope value is non-
When completely without effect, output envelope value is the register envelope value of highest effective bit corresponding channel.Learn the envelope at current time
As the envelope output after recombination after virtual value；(that is: the reality output envelope deposit packet that is that effective channel the latest
Network.)
Corresponding envelope is added in data after recombination, sends rear class processing to.
Step 3: the end Custom MAC receives data from the end Custom IP parallel, it is sent to outside；Specifically,
The transmitted in parallel clock that parallel drive output circuit is provided with the end Custom IP is received to go out parallel for reference from PHY core
Mouth receives parallel data；It is sent into channel and entangles a yard circuit；
Channel is entangled yard circuit and is handled the parallel data；Interchannel is solved due to arrival time sequence and when sending
It is inconsistent and there is the problem of randomness；
It transmits/receives buffer area fifo module and writes enabled, the write-in of treated data is transmitted/received into buffer area fifo module；
The end Custom MAC sends data to host by FPGA inner peripheral logic (such as PCI/PCIE interface).
The present invention has the beneficial effect that:
The high speed serialization transceiver interface is based on FPGA technology, and the circuit of realization is that (FPGA can be done pure hardware circuit simultaneously
Auxiliary activities logical process)；It is small to occupy hardware space；Data transparent transmission may be implemented；By the multiplexing in the channel PHY, there is one
Fixed extended capability；Environmental suitability is strong, and stability is high.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
Claims (15)
1. a kind of high speed serialization transceiver interface based on FPGA, the interface is used for the conversion of parallel data and serial data, packet
It includes: the end Custom MAC, the end Custom IP；It is characterized in that,
The end the Custom MAC, for carrying out parallel data transmitting-receiving with the end the Custom IP；
The end the Custom MAC include: transmit/receive buffer area FIFO, IP kernel initialization and configuration circuit, bell idles self-checking circuit,
Step-out restores that circuit, transmitting-receiving parallel drive circuit, channel is protected to entangle a yard circuit, overtime protection circuit；
The end the Custom IP, for carrying out serial data transmitting-receiving with the opposite end end Custom IP；
The end the Custom IP and the end opposite end Custom IP are connected with each other by coaxial cable.
2. the high speed serialization transceiver interface according to claim 1 based on FPGA, which is characterized in that
The every coaxial cable is as a channel；The end each Custom IP transmitting-receiving both direction respectively possesses most 32 and leads to
Road.
3. the high speed serialization transceiver interface according to claim 1 based on FPGA, which is characterized in that
The IP kernel initialization and configuration circuit are used for: being powered on and are carried out reset and initialization operation to IP kernel, carry out to register
Parameter configuration；Initialization front and back carries out block protection to channel.
4. the high speed serialization transceiver interface according to claim 1 based on FPGA, which is characterized in that
The transmitting-receiving parallel drive circuit includes hair parallel drive circuit and receipts parallel drive circuit；Send out parallel drive circuit according to
Data in hair caching FIFO are increased feature field by channel parallel data bit width, then by the parallel hair for using PHY core to provide
Clock is sent to be transported in PHY core parallel entry；Receive parallel drive circuit the parallel outlet data of PHY core is provided with PHY core and
It is to entangle a yard module with reference to feeding channel that row, which receives clock, and caching FIFO is received in write-in after processing, for outside extraction.
5. the high speed serialization transceiver interface according to claim 1 based on FPGA, which is characterized in that
The end the Custom IP includes: PCS Physical Coding Sublayer, PMA physical media adaptation layer.
6. the high speed serialization transceiver interface according to claim 5 based on FPGA, which is characterized in that
The PCS Physical Coding Sublayer is responsible for 8b/10b coding and CRC check, and integrated responsible channel binding and clock are repaired
Positive elastic buffer.
7. the high speed serialization transceiver interface according to claim 5 based on FPGA, which is characterized in that
The PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data stream.
8. a kind of data transmission method for uplink that the high speed serialization transceiver interface using described in claim 4 based on FPGA is realized,
It is characterized in that, comprising the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；
Step 2: the end Custom MAC receives data from outside, transmitted in parallel gives the end Custom IP；
The step 2 further comprises:
The end Custom MAC passes through FPGA inner peripheral logic from host receiving data；
Transmit/receive buffer area fifo module write it is enabled, by the data received from host write-in transmit/receive buffer area fifo module；
Hair parallel drive circuit increases tagged word to the data transmitted/received in buffer area fifo module according to channel parallel data bit width
Then section is sent to the parallel entry at the end Custom IP by the transmitted in parallel clock that the end Custom IP provides；
Step 3: the end Custom IP receives parallel data, and serial data stream is converted to, is sent to pair by FPGA transceiver
Hold FPGA transceiver.
9. data transmission method for uplink according to claim 8, which is characterized in that the initialization of the end the Custom IP is further
Include:
1.1, IP kernel initialization and configuration circuit power on, and the end Custom IP is resetted and initialized；It is resetting and is initializing
Period carries out channel guard；
1.2, after the initialization of the end Custom IP, the real-time self-test of bell idles and correction are carried out.
10. data transmission method for uplink according to claim 9, which is characterized in that the real-time self-test of the bell idles and correct packet
It includes:
When there are data, data are received；When no data, self-test is carried out, receives idle self demarking code, monitoring channel idle state is
No exception；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if into one
Whether abnormal walk monitoring data transmission；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue data if data transmission is normal
It sends until completing this data receiver；
Self-test is carried out again after completing this data receiver, is repeated the above steps.
11. data transmission method for uplink according to claim 8, which is characterized in that the step 3 further comprises:
PCS Physical Coding Sublayer carries out 8B/10B transformation to the parallel data received；
PMA physical media adaptation layer carries out parallel-serial conversion to the parallel data after variation, is converted to serial data stream；By coaxial
Cable is sent.
12. a kind of data receiver method that the high speed serialization transceiver interface using described in claim 4 based on FPGA is realized,
It is characterized in that, comprising the following steps:
Step 1: the end Custom MAC, the initialization of the end Custom IP；
Step 2: the end Custom IP receives serial data stream from the opposite end end Custom IP by FPGA transceiver；It will receive
Converting serial data streams be parallel data, and be sent to the end Custom MAC；
Step 3: the end Custom MAC receives data from the end Custom IP parallel, it is sent to outside；
The step 3 further comprises:
The transmitted in parallel clock that receipts parallel drive output circuit is provided with the end Custom IP exports for reference from PHY core parallel to be connect
Receive parallel data；It is sent into channel and entangles a yard circuit；
Channel is entangled yard circuit and is handled the parallel data；Interchannel is solved due to different when arrival time sequence is with transmission
It causes and there is the problem of randomness；
It transmits/receives buffer area fifo module and writes enabled, the write-in of treated data is transmitted/received into buffer area fifo module；
The end Custom MAC sends data to host by FPGA inner peripheral logic.
13. data receiver method according to claim 12, which is characterized in that the end the Custom IP is initialized into one
Step includes:
1.1, IP kernel initialization and configuration circuit power on, and the end Custom IP is resetted and initialized；It is resetting and is initializing
Period carries out channel guard；
1.2, after the initialization of the end Custom IP, the real-time self-test of bell idles and correction are carried out.
14. data receiver method according to claim 13, which is characterized in that the real-time self-test of the bell idles and correct packet
It includes:
When there are data, data are received；When no data, self-test is carried out, receives idle self demarking code, monitoring channel idle state is
No exception；
Enter re-synchronization mechanism if channel idle state is abnormal to be repaired；If channel idle state normally if into one
Whether abnormal walk monitoring data transmission；
Enter data synchronization processing mechanism if data transmission exception to be repaired；Continue data if data transmission is normal
It sends until completing this data receiver；
Self-test is carried out again after completing this data receiver, is repeated the above steps.
15. data receiver method according to claim 12, which is characterized in that the step 2 further comprises:
Serial data stream is received by coaxial cable；
PMA physical media adaptation layer carries out serioparallel exchange；
PCS Physical Coding Sublayer carries out 10B/8B decoding to parallel data；
It is exported parallel by PHY core and sends data.
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| CN109948788B (en) * | 2019-03-07 | 2021-01-15 | 清华大学 | Neural network accelerator based on FPGA |
| CN111708724B (en) * | 2020-05-29 | 2022-02-22 | 苏州浪潮智能科技有限公司 | Method and equipment for allocating resources of PCIe board card |
| CN111949590B (en) * | 2020-08-11 | 2022-05-06 | 国微集团(深圳)有限公司 | High-speed communication method capable of crossing FPGA platform |
| CN111984574A (en) * | 2020-08-17 | 2020-11-24 | 北京中新创科技有限公司 | Backboard bus exchange system based on universal serial transmit-receive interface |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174283A (en) * | 2007-12-03 | 2008-05-07 | 电子科技大学 | Software and hardware cooperating simulation platform based on network |
| CN101330328A (en) * | 2008-07-24 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for implementing multi-speed optical interface |
| US7913104B1 (en) * | 2007-10-12 | 2011-03-22 | Xilinx, Inc. | Method and apparatus for receive channel data alignment with minimized latency variation |
| CN102104427A (en) * | 2009-12-18 | 2011-06-22 | 东软飞利浦医疗设备系统有限责任公司 | FPGA-based nuclear magnetic resonance data communication implementation device and method |
| CN103326236A (en) * | 2013-06-19 | 2013-09-25 | 华中科技大学 | Semiconductor laser unit modulating and driving system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120188885A1 (en) * | 2011-01-20 | 2012-07-26 | Mehmet Tazebay | Method and system for self-adapting dynamic power reduction mechanism for physical layer devices in packet data networks |
-
2016
- 2016-08-30 CN CN201610787092.1A patent/CN106303759B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7913104B1 (en) * | 2007-10-12 | 2011-03-22 | Xilinx, Inc. | Method and apparatus for receive channel data alignment with minimized latency variation |
| CN101174283A (en) * | 2007-12-03 | 2008-05-07 | 电子科技大学 | Software and hardware cooperating simulation platform based on network |
| CN101330328A (en) * | 2008-07-24 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for implementing multi-speed optical interface |
| CN102104427A (en) * | 2009-12-18 | 2011-06-22 | 东软飞利浦医疗设备系统有限责任公司 | FPGA-based nuclear magnetic resonance data communication implementation device and method |
| CN103326236A (en) * | 2013-06-19 | 2013-09-25 | 华中科技大学 | Semiconductor laser unit modulating and driving system |
Non-Patent Citations (1)
| Title |
|---|
| "100G以太网PCS子层研究及其在FPGA的实现";张立鹏;《中国优秀硕士学位论文全文数据库信息科技辑》;20110415;摘要，第3、6章 |
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