CN103685238A

CN103685238A - Media access controller XMACII

Info

Publication number: CN103685238A
Application number: CN201310599169.9A
Authority: CN
Inventors: 韩毅
Original assignee: Chengdu Zhaoyi Technology Development Co Ltd
Current assignee: Chengdu Zhaoyi Technology Development Co Ltd
Priority date: 2013-11-25
Filing date: 2013-11-25
Publication date: 2014-03-26

Abstract

The invention discloses a media access controller XMACIIACII which comprises FIFO (first in, first out) control logic, an MAC, a PCS, a register, an Ethernet transceiver, an FPGA (field programmable gate array) and a clock control interface. The FIFO control logic comprises transmitting FIFO and receiving FIFO; the MAC comprises a transmitting state machine and a receiving state machine; the PCS comprises a coder/decoder with an FC-0 interface and a GMII with a GMII interface; the register comprises a management register and a control interface; the clock control interface is connected with the register which is connected with the FIFO control logic and the FPGA, the FIFO control logic is connected with the MAC which is connected with the PCS, and the 8B10BPCS coder/decoder, with the FC-0 interface, in the PCS is connected with the Ethernet transceiver. The media access controller XMACIIACII has the advantages that a logic time sequence of a data converter and all device read-write data is realized, working efficiency is highly improve, maintenance is reduced, and high-speed transfer of data is realized.

Description

A kind of media access controller XMACII

Technical field

The present invention relates to a kind of media access controller XMACII, particularly a kind of thousand realize the data link layer of router and the data transmission medium access controller XMACII between Gigabit Ethernet.

Background technology

Along with the multiservice requirement of the universal and network application of broadband network, increasing of the large capaciated flow network business based on video multimedia etc. particularly, traditional router more and more becomes the bottleneck of express network.Owing to being to be connected by shared bus between each port of router, the port speed of router is lower, thereby has limited the ability that forwards IP grouping.Traditional router is all difficult to meet the requirement of modern IP communication network at aspects such as operation Routing Protocol, maintaining routing lists.

For the data link layer and the data between Gigabit Ethernet that realize router, transmit, the transmission of data, need data converter, in order not there are not a large amount of packet drops, also need to meet the logical sequence that each device reads and writes data a plurality of equipment of outer company of having to, not only can increase and realize data transmission Lian road, and be easy to not realize the data link layer of router and the data between Gigabit Ethernet transmit because of misconnection, thereby increase maintenance workload, reduce Job readiness efficiency.

Summary of the invention

The present invention is directed to the deficiencies in the prior art part, a kind of media access controller XMACII is provided, ethernet transceiver and FPGA are integrated in media access controller, realize the logical sequence that data converter and each device read and write data, improve efficient work rate, reduce and safeguard, the high speed that realizes data transmits.

For achieving the above object, the technical solution used in the present invention is:

A media access controller XMACIIACII, is characterized in that: comprise fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises with the decoding/decoder of FC-0 interface, with the GMII of gmii interface; Register comprises supervisor register and control interface;

Clock control interface is connected with register, and register is connected with FPGA with fifo control logic, and fifo control logic is connected with MAC, and MAC is connected with PCS, and the 8B10BPCS decoding/decoder with FC-0 interface in PCS is connected with ethernet transceiver.

As preferably, described media access controller XMACII encapsulates by the PQFP of 240 pins.

As preferably, described fifo control logic comprises that the 8KB of 32 bit data width receives FIFO and 4KB sends FIFO.

As preferably, described decoding/decoder with FC-0 interface is 8B or 10B decoding/decoder.

As preferably, described FPGA comprises and sends data module and receive data module, and two modules are independent mutually.

Compared with prior art, the invention has the advantages that:

1, in media access controller XMACIIACI, be integrated with ethernet transceiver, the conversion while realizing digital received and sent;

2., in media access controller XMACIIACI, be integrated with FPGA, realize the logic control that in router side high-level device, Gigabit Ethernet media access controller XMACII, between large Capacity FIFO, data transmit, prevented the packet loss of data.

Accompanying drawing explanation

Fig. 1 is structural representation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described.

A media access controller XMACIIACII, comprises fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises with the decoding/decoder of FC-0 interface, with the GMII of gmii interface; Register comprises supervisor register and control interface;

The serial data of the data flow of broadcasting in the Gigabit Ethernet of fiber medium after fiber channel interface must first be converted into by Gigabit Ethernet transceiver (claiming again Serdes, parallel converters) the FC-0 interface that 10 parallel coded datas just can be sent to XMACII; The 10bit coded data that the FC-0 interface of XMACII is sent also will first be converted to the data flow of 10 times of baud rates through Serdes, then broadcasts to Ethernet through fiber channel interface.So ethernet transceiver is integrated in media access controller XMACIIACII; And the message transmission rate of Gigabit Ethernet is very high, peak data rate can reach 1.25Gb/s.And the speed of data link layer deals grouping is relatively slow, thereby can when burst mass data (data bursting), data be difficult to timely processing, occur a large amount of packet losses.Although integrated in media access controller, receive and send FIFO to carry out data buffering, the inside FIFO of media access controller XMACII is easily still less.For avoiding factor data link layer to have little time the situation of a large amount of packet losses of deal with data, integrated FPGA on media access controller XMACII, as data buffering.

Send data module and process the data that router side high-level device sends, latched one-period and send into external FIFO, and control it and from FIFO, read and send into XMACII with correct sequential.If the reason that data are latched to a clock cycle is to consider the data that sent by the trackside FIFO that writes direct, when being had quite strict requirement so that realized, the judgement of control signal is difficult to reach.Therefore data are latched once to facilitate judgement and the driving of control logic.In addition also need to be by the cumulative length that obtains each Frame of counter, to can determine the border of each Frame when data reading when data write FIFO.In FIFO, the length of each Frame is deposited in a FIFO who realizes with software FPGA inside in order.Detailed process: when whole writing after external FIFO of Frame, the byte number that accumulated counts obtains this Frame has also write the FIFO of FPGA inside simultaneously; And soon from FIFO, decide a law case while when Frame, first the byte number of this frame is read from the inside FIFO of FPGA, and when reading frame data, this byte number is corresponding successively decreases, and till zero, a Frame is read by whole, so repeatedly carries out.

Receive data module and process the data that XMACII receives, send in FIFO after being latched equally a clock cycle, by router side high-level device, data are read from FIFO.When data write FIFO, still need to record the length of each Frame, in the time of router side reading out data, once read whole Frame.Specific implementation and sending module are similar.Data width while writing FIFO due to XMACII is 32, and the high-rise data width arranging while reading FIFO of router side is 16, thereby should have corresponding processing when the byte count of Frame.

Below by reference to the accompanying drawings a kind of media access controller XMACII of the present invention is explained, but protection scope of the present invention is not limited to this, all changes of having done based on above embodiment or distortion all belong to the scope of protection of present invention.

Claims

1. a media access controller XMACIIACII, is characterized in that: comprise fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises with the decoding/decoder of FC-0 interface, with the GMII of gmii interface; Register comprises supervisor register and control interface;

2. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described media access controller XMACII encapsulates by the PQFP of 240 pins.

3. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described fifo control logic comprises that the 8KB of 32 bit data width receives FIFO and 4KB sends FIFO.

4. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described decoding/decoder with FC-0 interface is 8B or 10B decoding/decoder.

5. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described FPGA comprises transmission data module and reception data module, and two modules are independent mutually.