CN203574689U

CN203574689U - Medium access controller XMACII

Info

Publication number: CN203574689U
Application number: CN201320748038.8U
Authority: CN
Inventors: 韩毅
Original assignee: Chengdu Zhaoyi Technology Development Co Ltd
Current assignee: Chengdu Zhaoyi Technology Development Co Ltd
Priority date: 2013-11-25
Filing date: 2013-11-25
Publication date: 2014-04-30
Anticipated expiration: 2023-11-25

Abstract

The utility model discloses a medium access controller XMACIIACII. The medium access controller comprises an FIFO control logic, an MAC, a PCS, a register, an Ethernet transceiver, an FPGA and a clock control interface, the FIFP control logic comprises a sending FIFO and a reception FIFO, the MAC comprises a sending state machine and a reception state machine, the PCS comprises a decoding/decoder with an FC-0 interface and a GMII with a GMII interface, the register comprises a management register and a control interface, the clock control interface is connected with the register, the register is connected with the FIFO control logic and the FPGA, the FIFO control logic is connected with the MAC, the MAC is connected with the PCS, and the 8B10BPCS decoding/decoder with the FC-0 interface in the PCS is connected with the Ethernet transceiver. According to the medium access controller, logic time sequence of a data converter and read-write data of each device is achieved, the work efficiency is improved, the maintenance is reduced, and high-speed transmission of data is achieved.

Description

A kind of media access controller XMACII

Technical field

The utility model relates to a kind of media access controller XMACII, particularly a kind of thousand data transmission medium access controller XMACII that realize between data link layer and the Gigabit Ethernet of router.

Background technology

Along with the multiservice requirement of the universal and network application of broadband network, particularly increasing of the large capaciated flow network business based on video multimedia etc., traditional router more and more becomes the bottleneck of express network.Owing to being to be connected by shared bus between each port of router, the port speed of router is lower, thereby has limited the ability that forwards IP grouping.Traditional router is all difficult to meet the requirement of modern IP communication network at aspects such as operation Routing Protocol, maintaining routing lists.

For the data transmission realizing between data link layer and the Gigabit Ethernet of router, the transmission of data, need data converter, in order not there are not a large amount of packet drops, also need to meet the logical sequence that each device reads and writes data the multiple equipment of outer company of having to, not only can increase and realize data transmission Lian road, and be easy to because misconnection does not realize the data transmission between data link layer and the Gigabit Ethernet of router, thereby increase maintenance workload, reduce Job readiness efficiency.

Summary of the invention

The utility model is for the deficiencies in the prior art part, a kind of media access controller XMACII is provided, ethernet transceiver and FPGA are integrated in media access controller, realize the logical sequence that data converter and each device read and write data, improve efficient work rate, reduce and safeguard, realize the high speed transmission of data.

For achieving the above object, the technical solution adopted in the utility model is:

A kind of media access controller XMACIIACII, is characterized in that: comprise fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises decoding/decoder, the GMII with gmii interface with FC-0 interface; Register comprises supervisor register and control interface;

Clock control interface is connected with register, and register is connected with FPGA with fifo control logic, and fifo control logic is connected with MAC, and MAC is connected with PCS, and the 8B10BPCS decoding/decoder with FC-0 interface in PCS is connected with ethernet transceiver.

As preferably, described media access controller XMACII is by the PQFP encapsulation of 240 pins.

As preferably, described fifo control logic comprises that the 8KB of 32 bit data width receives FIFO and 4KB sends FIFO.

As preferably, described decoding/decoder with FC-0 interface is 8B or 10B decoding/decoder.

As preferably, described FPGA comprises and sends data module and receive data module, and two modules are independent mutually.

Compared with prior art, the utility model has the advantage of:

1, in media access controller XMACIIACI, be integrated with ethernet transceiver, the conversion while realizing digital received and sent;

2, in media access controller XMACIIACI, be integrated with FPGA, realize the logic control that in router side high-level device, Gigabit Ethernet media access controller XMACII, between large Capacity FIFO, data transmit, prevented the packet loss of data.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail.

A kind of media access controller XMACIIACII, comprises fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises decoding/decoder, the GMII with gmii interface with FC-0 interface; Register comprises supervisor register and control interface;

The serial data of the data flow of broadcasting in the Gigabit Ethernet of fiber medium after fiber channel interface must be first converted into 10 parallel coded datas and just can be sent to the FC-0 interface of XMACII by Gigabit Ethernet transceiver (claiming again Serdes, parallel converters); The 10bit coded data that the FC-0 interface of XMACII is sent also will first be converted to the data flow of 10 times of baud rates through Serdes, then broadcasts to Ethernet through fiber channel interface.So ethernet transceiver is integrated in media access controller XMACIIACII; And the message transmission rate of Gigabit Ethernet is very high, peak data rate can reach 1.25Gb/s.And the speed of data link layer deals grouping is relatively slow, thereby can when burst mass data (data bursting), data be difficult to timely processing, occur a large amount of packet losses.Although integrated in media access controller, receive and send FIFO to carry out data buffering, the inside FIFO of media access controller XMACII is easily still less.For avoiding factor data link layer to have little time the situation of a large amount of packet losses of deal with data, integrated FPGA on media access controller XMACII, as data buffering.

Send data module and process the data that router side high-level device sends, its latch one-period is sent into external FIFO, and control it and from FIFO, read and send into XMACII with correct sequential.If be to consider the data that sent by the trackside FIFO that writes direct by the reason of a clock cycle of data latch, when being had quite strict requirement so that realized, the judgement of control signal is difficult to reach.Therefore by data latch once to facilitate judgement and the driving of control logic.In addition also need to be by the cumulative length that obtains each Frame of counter, to can determine the border of each Frame when data reading when data write FIFO.In FIFO, the length of each Frame is deposited in a FIFO of FPGA inside software realization in order.Detailed process: when whole writing after external FIFO of Frame, the byte number that accumulated counts obtains this Frame has also write the FIFO of FPGA inside simultaneously; And soon from FIFO, decide a law case while when Frame, first the byte number of this frame is read from the inside FIFO of FPGA, and when reading frame data, this byte number is corresponding successively decreases, and till zero, a Frame is read by whole, so repeatedly carries out.

Receive data module and process the data that XMACII receives, by sending in FIFO after the clock cycle of its latch, by router side high-level device, data are read from FIFO equally.When data write FIFO, still need to record the length of each Frame, in the time of router side reading out data, once read whole Frame.Specific implementation and sending module are similar.Data width while writing FIFO due to XMACII is 32, and the high-rise data width arranging while reading FIFO of router side is 16, thereby should have corresponding processing when the byte count of Frame.

Below by reference to the accompanying drawings a kind of media access controller XMACII of the present utility model is explained; but protection range of the present utility model is not limited to this, all changes of having done based on above embodiment or distortion all belong to the claimed scope of the utility model.

Claims

1. a media access controller XMACIIACII, is characterized in that: comprise fifo control logic, MAC, PCS, register, ethernet transceiver, FPGA, clock control interface; Described fifo control logic comprises transmission FIFO and receives FIFO; MAC comprises state machine and the accepting state machine of sending; PCS comprises decoding/decoder, the GMII with gmii interface with FC-0 interface; Register comprises supervisor register and control interface;

2. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described media access controller XMACII is by the PQFP encapsulation of 240 pins.

3. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described fifo control logic comprises that the 8KB of 32 bit data width receives FIFO and 4KB sends FIFO.

4. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described decoding/decoder with FC-0 interface is 8B or 10B decoding/decoder.

5. a kind of media access controller XMACIIACII according to claim 1, is characterized in that: described FPGA comprises transmission data module and reception data module, and two modules are independent mutually.