CN106788566B

CN106788566B - Transceiver with continuously variable chip rate based on Ethernet physical layer and transmission method

Info

Publication number: CN106788566B
Application number: CN201611254153.4A
Authority: CN
Inventors: 杨阳; 俞小露; 曹桂平; 胡鑫; 於霞; 唐学峰; 陈静
Original assignee: HEFEI GUOWEI ELECTRONICS CO Ltd
Current assignee: HEFEI GUOWEI ELECTRONICS CO Ltd
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2022-08-09
Anticipated expiration: 2036-12-30
Also published as: CN106788566A

Abstract

The invention discloses a transceiver with continuously variable chip rate based on an Ethernet physical layer and a transmission method, belonging to the technical field of seismic exploration. In addition, a method for data transmission by using the transceiver is disclosed. The invention only adopts the FPGA main control chip to be connected with the PHY chip through the MII interface for data transmission, and adopts the FPGA to directly drive the PHY reference clock, thereby saving the use of devices such as a CPU, a passive 25MHz crystal oscillator and the like, greatly reducing the devices required by data transmission, reducing the cost and the power consumption of a transceiver, and having important significance for the fields of field construction, seismic exploration and the like.

Description

Transceiver with continuously variable chip rate based on Ethernet physical layer and transmission method

Technical Field

The invention relates to the technical field of seismic exploration, in particular to a transceiver based on continuous variable speed of an Ethernet physical layer chip and a transmission method.

Background

At present, in the field of seismic physical exploration, the most commonly used instrument is a seismometer, and with the continuous increase of the number of acquisition channels of the seismometer, the data transmission method is also continuously improved. The conventional data transmission method mainly includes low-speed serial transmission and high-speed serial transmission. However, neither of the two conventional data transmission methods can simultaneously satisfy the requirements of high-speed transmission and low-speed transmission, and therefore, a data transmission scheme based on an ethernet physical layer transceiver is proposed in patent document with publication number CN102692642A, and according to the data transmission requirement, one of 10Mbps, 100Mbps and 1000Mbps can be selected as a working frequency point. However, this data transmission scheme still has a serious drawback in that its operating frequency cannot be continuously adjusted. In practical applications, this brings about a series of problems: firstly, if the maximum data transmission rate on a survey line is 16Mbps, traditional RS485 can directly adjust this frequency point transmission, and use the mode that Ethernet physical layer transceiver can only adopt 100Mbps, and the cable between two acquisition stations of seismometer can be as long as 200 meters or even longer, and if long cable so required work below 100Mbps, the requirement to the cable quality is very high, has increased use cost. Secondly, the data transmission scheme of the existing ethernet physical layer transceiver must complete data transmission by the cooperation of the FPGA and the CPU, and the CPU is used to complete the configuration of the operating mode of the PHY. Thirdly, the existing ethernet physical layer transceiver cannot directly drive the ethernet to work in the 1000Mbps mode through the FPGA.

Disclosure of Invention

The invention aims to provide a transceiver with continuously variable speed based on an Ethernet physical layer chip and a transmission method, so as to solve the problem of higher use cost of the existing Ethernet physical layer transceiver.

In order to realize the purpose, the invention adopts the technical scheme that: in a first aspect, a transceiver with a continuously variable rate based on an ethernet physical layer chip is provided, and the transceiver includes an FPGA control chip, and first and second PHY chips, where the FPGA is connected to input interfaces of the first and second PHY chips through a clock interface, connected to the first and second PHY chips through a data input/output interface RGMII or MII, and connected to the first and second PHY chips through a data management input/output interface MDIO.

In a second aspect, a transmission method based on ethernet physical layer chip rate continuously variable is provided, the method includes:

the first PHY chip receives data of a bottom layer and sends the received data of the bottom layer to the FPGA control chip through the RGMII or MII interface;

and the FPGA control chip sends the bottom layer data to the second PHY chip through the RGMII or MII interface.

Compared with the prior art, the invention has the following technical effects: in the invention, the FPGA main control chip is connected with the PHY chip through the MII interface for data transmission, and the reference clock is directly driven by the FPGA, so that the use of devices such as a CPU (central processing unit), a passive 25MHz crystal oscillator and the like is saved, the devices required by data transmission are greatly reduced, the cost and the power consumption of a transceiver are reduced, and the method has important significance in the fields of field construction, seismic exploration and the like.

Drawings

Fig. 1 is a schematic structural diagram of a transceiver with a continuously variable chip rate based on an ethernet physical layer according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a connection structure of a transceiver with a continuously variable chip rate based on Ethernet physical layer and an analog-to-digital converter according to an embodiment of the present invention

FIG. 3 is a schematic structural diagram of an FPGA control chip according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a transceiver with a continuously variable chip rate based on Ethernet physical layer in an embodiment of the present invention applied to a seismograph data transmission system;

FIG. 5 is a flow chart illustrating a transmission method based on a continuously variable Ethernet physical layer chip rate according to an embodiment of the present invention;

fig. 6 is a schematic flow chart of another transmission method based on ethernet physical layer chip rate continuous variable according to an embodiment of the present invention;

FIG. 7 is a timing diagram for the MDIO bus write in accordance with an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating the read of the MDIO bus according to one embodiment of the present invention;

fig. 9 is a timing diagram of signals related to a transmitting end of an FPGA main control chip according to an embodiment of the present invention;

fig. 10 is a timing diagram of signals related to a receiving end of the FPGA main control chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to fig. 1 to 10.

As shown in fig. 1, the present embodiment discloses a transceiver with continuously variable chip rate based on the ethernet physical layer, which is characterized in that the transceiver includes an FPGA control chip 10, and first and

second PHY chips

21 and 22, where the FPGA10 is connected to input interfaces of the first and

second PHY chips

21 and 22 through a clock interface, connected to the first and

second PHY chips

21 and 22 through a data input and output interface RGMII or MII, and connected to the first and

second PHY chips

21 and 22 through a data management input and output interface MDIO.

Specifically, the first and

second PHY chips

21 and 22 in this embodiment are ethernet Physical layer chips (PHYs).

In the embodiment, a Field-Programmable Gate Array (FPGA) replaces a CPU to configure a PHY and read the state of the PHY through an MDIO bus, so that the complexity and power consumption of the system are greatly reduced, and the use cost is saved.

As shown in fig. 2, the transceiver further includes an analog-to-digital converter ADC30 connected to the input end of the FPGA control chip (10).

It should be noted that, in this embodiment, an ethernet transformer may be further disposed to protect the circuits inside the FPGA control chip 10 and the first and

second PHY chips

21 and 22 from being interfered by external strong pulses.

Specifically, in this embodiment, a BCM54610 PHY chip manufactured by Broadcom corporation is used, and an FPGA manufactured by Altera corporation and having model EP3C40F484 is used, wherein the connection between the FPGA and the PHY mainly includes three parts:

(1) and the reference clock refclk is directly transmitted to the PHY chip by the FPGA according to a specific speed and by referring to the table 1 to select a reference clock signal with a corresponding frequency.

TABLE 1

Actual rate

20Mbps

30Mbps

40Mbps

50Mbps

60Mbps

80Mbps

Mode selection

10Mbps

100Mbps

Reference clock

50MHz

75MHz

10MHz

12.5MHz

15MHz

20MHz

(2) The data interface is RGMII interface in 1000Mbps mode, and MII interface in 100Mbps or 10Mbps mode. Taking the MII interface as an example, it includes two parts, receiving and transmitting. The FPGA needs to drive the corresponding signals according to the standard MII interface timing, specifically, when sending data, the transmit enable signal txen is set to high level, and simultaneously the data is driven to txd [3:0] according to the rising edge of the transmit clock txclk at the same time every 4 bits, and when receiving data, the receive data valid signal rxdv is high level, and simultaneously the 4 bits data on rxd [3:0] are stored at the rising edge of rxclk. The difference for the RGMII mode is the need to drive or store data on both the rising and falling edges of txclk or rxclk.

(3) The data management input output interface MDIO is mainly used for configuring corresponding registers of the PHY to operate in a specific configuration and querying the operating state of the PHY. This interface includes only two signal lines, MDC and MDIO. When accessing the corresponding register of the PHY, the FPGA as a master device needs to output a clock signal to the MDC, when writing the register, the MDC needs to be driven at the same time on the rising edge of the MDC, and when reading the register, the MDC needs to read the MDIO signal line on the rising edge of the MDC.

Specifically, as shown in fig. 3, the FPGA10 includes a scheduling module 11 and first and second duplicate data input and

output DDIOs

12, 13;

the input end of the first double data input/output DDIO12 is connected with the first PHY chip 21 through an RGMII or MII interface, and the input end of the RXFIFO14 is connected after the upper/lower edge output interfaces are connected in parallel;

the output end of the second double data input/output DDIO13 is connected with the second PHY chip 22 through a data interface RGMII or MII interface, and the output end of the TXFIFO15 is connected after the upper/lower edge input interfaces are connected in parallel;

an output of the RXFIFO14 is connected to an input of the TXFIFO15 through a scheduling module 11.

It should be noted that the RXFIFO14 is a Receive queue (Receive First In First Out), the TXFIFO15 is a Transmit queue (Transmit First In First Out), and the ADCFIFO16 is an Analog-to-Digital Converter queue (Analog Digital Converter First In First Out).

Specifically, the main control chip 10 in this embodiment further includes an ADC control module 16,

the input end of the ADC control module 17 is connected to the analog-to-digital converter ADC30 through an ADC interface, and the output end is connected to the ADCFIFO 16.

Specifically, the main control chip 10 includes the following parts:

(1) the FPGA master chip 10 uses the first double data input/output DDIO12, i.e. the DDIO module, to take out the data of the first PHY chip 21 from the rxd [3:0] at the rising edge and the falling edge of rxclk, respectively, to generate data [3:0] and data [3:0], and these two 4-bit data are combined into one and written into the RXFIFO14, and finally the data is read out under the control of the scheduling module 11 to continue processing.

(2) The ADC control module 17 is responsible for driving the ADC30 to collect data and write all the data collected by the ADC30 into the ADCFIFO16, and finally, the data is also read out under the control of the scheduling module 11 and processed.

(3) The scheduling module 11 writes the data to be transmitted in ADCFIFO, RXFIFO14 into TXFIFO15, and when the second PHY chip 22 is ready to receive the data, reads out 8-bit data txdata from TXFIFO15, and the data is divided into two 4-bit data and transmitted to the second double data input output DDIO13, and the second double data input output DDIO13 drives the two 4-bit data to txd [3:0] on the rising edge and the falling edge of txclk, respectively.

(4) The scheduling module 11 is responsible for continuously listening to the RXFIFO14 status, and when it reaches the minimum frame length, it starts reading the RXFIFO14 and writes the read data into the TXFIFO 15. On the other hand, the data collected by the ADC control module 17 is organized into data of one frame and one frame according to a predetermined format and written into the TXFIFO 15.

It should be noted that the scheduling module 11 also configures the first and

second PHY chips

21 and 22 through the MDIO bus at each reset, but generally only needs to configure a control register with an address of 0x0 to select a proper speed mode.

It should be noted that although the present solution only utilizes the physical layer of the ethernet transceiver, the frame format defined by IEEE802.3 may not be used. However, since the actual PHY chip still needs to transmit a preamble (preamplle) during operation, the FPGA needs to comply with certain frame format requirements when transmitting data through the PHY, specifically, a preamble (01010101) of 7 bytes needs to be added before valid data that needs to be transmitted, and then a frame start character (11010101) needs to be transmitted. Also, the data receiving part needs to store valid data after receiving the start of frame.

Specifically, as shown in fig. 4, when the transceiver based on the ethernet physical layer chip with continuously variable rate disclosed in this embodiment is applied to a seismograph data acquisition system, the practicability of a seismograph using a long-distance cable as a transmission medium is greatly improved. The specific process is as follows:

the whole seismograph consists of a master control station, a cross station, an acquisition station, a cross line and a sensor. The acquisition station is a basic unit forming the whole system, the acquisition station acquires and digitizes signals of the sensors and then transmits the signals upwards step by step, namely, the acquisition station faces the direction of the cross station, the cross station is responsible for collecting data transmitted by all the acquisition stations on a measuring line and then transmits the data to the upper cross station, the last cross station is connected with the master control station, and all the acquired data are finally collected on the master control station and stored. The master control station is responsible for issuing all commands and storing and converting formats of all uploaded data.

Because the rate on a single measuring line can not exceed 100Mbps, the PHY between the acquisition stations works in a10 Mbps mode or a 100Mbps mode, and the 100Mbps mode or a 1000Mbps mode is adopted between the cross stations. The acquisition stations are directly connected through only two pairs of twisted pairs, and the two pairs of twisted pairs are connected to two pairs of differential pins, namely a TRD0 and a TRD1, on a PHY chip in the acquisition stations, so that the full-time duplex transmission and reception functions can be completed. While operating in 1000Mbps mode between the cross stations requires the use of all 4 pairs of differential pins, TRD0 through TRD 3. The PHY chip is generally implemented by using a 25MHz clock as a reference source and connecting a passive 25MHz crystal oscillator between the two pins, namely, XTALI and XTALO. In the embodiment, the FPGA directly outputs clocks with different frequencies to the PHY chip from PLLCLKOUT, namely a special clock output pin, and basically covers all frequency points between 10Mbps and 100Mbps by a mode of frequency increasing operation in a10 Mbps mode and frequency decreasing operation in 100 Mbps.

Here, twisted pair is responsible for connecting data in the PHY chip to the cable, and two or four twisted pairs are selected according to the actual speed mode, for example, two twisted pairs are used in 100Mbps mode, and four twisted pairs are used in 1000Mbps mode.

It should be noted here that, because the reference of the existing clock signal is 25Mbps, as shown in table 1, for example, the actually required data transmission rate on the measurement line is 20Mbps, the frequency of the clock signal can be changed to 50Mbps by the FPGA main control chip 10, that is, the frequency is doubled compared with the reference frequency, and therefore, the data transmission rate on the measurement line is also doubled, that is, 20 Mbps. Therefore, in the embodiment, by changing the frequency of the output clock signal, the data transmission rate on the measuring line can be controlled to be continuously changed. In this embodiment, when the on-line rate is required to be 30Mbps or less, the rate is continuously changed by raising the frequency from the 10Mbps mode, and when the on-line rate is 40Mbps or more, the rate is continuously changed by lowering the frequency from the 100Mbps mode. Thus, all frequency points between 10Mbps and 100Mbps can be covered, so that the data transmission rate on the measuring line is continuously variable between 10Mbps and 100 Mbps.

Specifically, as shown in fig. 5, the present embodiment discloses a transmission method based on continuous variable ethernet physical layer chip rate, which includes the following steps S1 to S2:

s1, the first PHY chip 21 receives the bottom layer data and sends the received bottom layer data to the FPGA control chip 10 through the RGMII or MII interface;

s2, FPGA control chip 10 sends the underlying data to second PHY chip 22 through RGMII or MII interface.

Specifically, as shown in fig. 6, the data transmission method further includes the following steps S3 to S4:

s3, the FPGA control chip 10 outputs clock signals with different frequencies to the first and

second PHY chips

21 and 22 through the clock interface;

s4, the first and

second PHY chips

21 and 22 change the data transmission rate on the line connected to the first and

second PHY chips

21 and 22 according to the frequency of the received clock signal.

Specifically, step S2 further includes:

the FPGA control chip 10 sends the data collected by the analog-to-digital converter ADC30 to the second PHY chip 22 through the RGMII or MII interface.

Specifically, the FPGA control chip 10 selects the data input/output interface as the RGMII interface or the MII interface according to the working frequency points of the first PHY chip 21 and the second PHY chip 22. Wherein, adopt RGMII interface under 1000Mbps mode, adopt the MII interface under 100Mbps mode.

Specifically, step S2 includes the steps of:

the first double data input and output DDIO12 reads data uploaded by the first PHY chip 21 on the rising edge and the falling edge of rxclk, and writes the data into the RXFIFO 14;

the scheduling module 11 writes the data in the ADCFIFO16 and the data in the RXFIFO14 into the TXFIFO15,

the second double data input and output DDIO13 reads the data in the TXFIFO15 at the rising edge and the falling edge of txclk respectively, and outputs the two data to the second PHY chip 22.

Specifically, the FPGA master chip 10 replaces the CPU to configure the PHY and read the PHY status through the MDIO bus as shown in fig. 7 and 8. Fig. 7 shows a waveform corresponding to 16-bit number 0x3100 written into a register with address 0 of PHY, 64-bit data 0 xfffffffff 50023100 is written in total, the first 32 bits are all bit 1 as leading symbols, the next 0101 bits are respectively a start code and an operation code of a write operation, the next 5 bit 0 bits represent the address of PHY, the next 5 bit 0 bits represent the start address of register, the next 2 bit 10 bits are used for read-write conversion, and the next 16 bit is a specific value written into the register.

When the connection status of the PHY needs to be polled after configuration is completed, the value of the PHY status register, which is a register with an offset address of 0x11, is read, and whether the tenth bit, i.e., the link status bit, is 1 is determined. If 1, this indicates that the PHY has established a connection with another PHY. Fig. 8 shows the reading process, which is to write 48 bits 0xfffffff 6046 to PHY, where the first 32 bits are 1 or preamble, the next 0110 is start code and operation code of read operation, the next five bits are 0 PHY address, the next 5 bits are 10001 register address, and the next 2 bits are 10 for read-write conversion. The MDIO bus is then switched to the read state and the 16-bit register value is read into the register named rd _ buf [15:0], which by measuring to be 0xBC5C, indicates that a full-duplex 1000Mbps mode link has now been established. The logic of the FPGA can determine from this that the PHY is ready for transmission.

Specifically, the data transmission method in this embodiment is tested in the 1000Mbps mode, and a method of transmitting data from one circuit board to another circuit board for reception is adopted. FIG. 9 is a state diagram of the internal registers of the FPGA of the sender captured by using a tool Signaltap II dedicated to online debugging of the FPGA by Altera corporation. Each scale in the figure represents 8ns, i.e., corresponding to 125MHz frequency, rgmii _ txen is a transmit enable signal, and rgmii _ txd _ n [3:0] and rgmii _ txd _ p [3:0] are signals of a rising edge and a falling edge transmitted to a DDIO module, and the two signals are txd [3:0] synthesizing the change of the upper edge and the lower edge after passing through the DDIO and output to the PHY.

FIG. 10 is a diagram of the state of the internal registers of the receiving FPGA captured by Signaltap II, again with each scale representing 8 ns. The lower two signals, which are generated after DDIO, are valid for dataout _ h [3:0] and dataout _ l [3:0] generated after DDIO of rgmii _ rxd [3:0], respectively. Comparing fig. 9 and fig. 10, it can be found that the data at the transmitting end is received and stored by the receiving end without errors, and no error is found even after a long-time test of 16 hours is performed on a 100-meter ultra-five-class line.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are merely illustrative of the principles of the invention, but that various changes and modifications may be made without departing from the spirit and scope of the invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A transceiver based on continuous variable Ethernet physical layer chip rate is characterized by comprising an FPGA control chip (10), a first PHY chip and a second PHY chip (21, 22), wherein the FPGA (10) is respectively connected with input interfaces of the first PHY chip and the second PHY chip (21, 22) through clock interfaces, connected with the first PHY chip and the second PHY chip (21, 22) through data input and output interfaces RGMII or MII, and connected with the first PHY chip and the second PHY chip (21, 22) through a data management input and output interface MDIO;

the transceiver is applied to a seismograph data acquisition system, the seismograph data acquisition system comprises a main control station, a multi-stage cross station, acquisition stations and a sensor, the sensor is connected with the current-stage cross station through the acquisition stations, the current-stage cross station collects data transmitted by all the acquisition stations on a measuring line and then transmits the collected data to the upper-stage cross station, and the last-stage cross station is connected with the main control station;

the transceivers are arranged in the two acquisition stations, the transceivers are arranged in the upper and lower-level cross stations, the first PHY chips (21 and 22) and the second PHY chips (21 and 22) in the transceivers are connected through two pairs of twisted pairs or four pairs of twisted pairs, the two pairs of twisted pairs are connected with the TRD0 and the TRD1 differential pins of the first PHY chips (21 and 22) and the four pairs of twisted pairs are connected with the TRD0, the TRD1, the TRD2 and the TRD3 differential pins of the first PHY chips (21 and 22);

the FPGA control chip (10) in the transceiver directly outputs different frequency clocks to the first PHY chip (21) and the second PHY chip (22) from a clock interface thereof, the data transmission rate is controlled to be continuously changed, and all frequency points between 10Mbps and 100Mbps are covered by the mode of up-conversion operation in the 10Mbps mode and down-conversion operation in the 100Mbps mode.

2. The transceiver of claim 1, wherein the FPGA (10) comprises a scheduling module (11) and first and second duplicate data input and output DDIOs (12, 13);

the input end of a first double data input/output DDIO (12) is connected with a first PHY chip (21) through an RGMII or MII interface, and the input end of an RXMFIFO (14) is connected after the upper/lower edge output interfaces are connected in parallel;

the output end of the second double data input/output DDIO (13) is connected with a second PHY chip (22) through a data interface RGMII or an MII interface, and the output end of the TXFIFO (15) is connected after the upper/lower edge input interfaces are connected in parallel;

the output end of the RXFIFO (14) is connected with the input end of the TXFIFO (15) through a scheduling module (11).

3. A transmission method based on ethernet physical layer chip rate continuous variable, which is implemented by the transceiver based on ethernet physical layer chip rate continuous variable according to claim 1 or 2, and comprises:

s1, the first PHY chip (21) receives the data of the bottom layer and sends the received data of the bottom layer to the FPGA control chip (10) through the RGMII or MII interface;

s2, the FPGA control chip (10) sends the bottom layer data to the second PHY chip (22) through the RGMII or MII interface;

s3, the FPGA control chip (10) outputs clock signals with different frequencies to the first PHY chip and the second PHY chip (21, 22) through the clock interface;

s4, the first PHY chip and the second PHY chip (21, 22) change the data transmission rate on the measuring line connected with the first PHY chip and the second PHY chip (21, 22) according to the frequency of the received clock signal.

4. The transmission method of claim 3, further comprising:

the FPGA control chip (10) selects the data input/output interface to be an RGMII interface or an MII interface according to the working frequency points of the first PHY chip and the second PHY chip (21 and 22).

5. The transmission method according to claim 4, wherein the step S2 includes:

the first double data input and output DDIO (12) respectively reads data uploaded by the first PHY chip (21) on the rising edge and the falling edge of rxclk, and the data are combined into one and written into the RXFIFO (14);

the scheduling module (11) writes the data in the RXFIFO (14) into the TXFIFO (15),

the second double data input and output DDIO (13) reads data in the TXFIFO (15) at the rising edge and the falling edge of the txclk respectively, and outputs the data to the second PHY chip (22) in a combined mode.