CN114116563B - High-speed synchronous serial port module based on PCIE bus - Google Patents
High-speed synchronous serial port module based on PCIE bus Download PDFInfo
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- CN114116563B CN114116563B CN202111240916.0A CN202111240916A CN114116563B CN 114116563 B CN114116563 B CN 114116563B CN 202111240916 A CN202111240916 A CN 202111240916A CN 114116563 B CN114116563 B CN 114116563B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a high-speed synchronous serial port module based on a PCIE bus, which is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge chip conversion circuit, a dual-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port transceiver circuit and a synchronous serial port connector circuit. The invention has the advantages and beneficial effects that: the PCIE golden finger is introduced into the PCIE high-speed serial bus, a high-speed synchronous serial bus protocol is realized through protocol conversion, communication with external equipment is realized through the high-speed transceiver, and the PCIE bus conversion high-speed synchronous serial port is realized.
Description
Technical Field
The invention relates to the field of industrial control and military communication, in particular to the field of industrial control and military communication.
Background
PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard originally named "3GIO" and was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards.
PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected equipment allocates exclusive channel bandwidth without sharing bus bandwidth and mainly supports functions of active power management, error reporting, end-to-end reliability transmission, hot plug, quality of service (QOS) and the like. PCIE has the main advantage of high data transmission rate and has considerable development potential. PCI Express also has a variety of specifications, from PCI Express x1 to PCI Express x32, which can meet the demands of low-speed devices and high-speed devices that occur in a certain time in the future. The PCI-Express interface is a PCIE3.0 interface, with a bit rate of 8Gbps, which is about twice the bandwidth of the previous generation of products, and contains a series of important new functions such as transmitter and receiver equalization, PLL improvement, and clock data recovery, for improving data transmission and data protection performance.
Serial communication can be classified into synchronous communication and asynchronous communication. Synchronous communication means that the frequencies and phases of clock signals of a transmitting end and a receiving end are always consistent (synchronous) under the agreed communication rate, so that the two parties of communication are ensured to have a completely consistent timing relationship when transmitting and receiving data. Serial communication refers to the serial transfer of data between a computer host and a peripheral device and between a host system and a host system. When serial communication is used, each character transmitted and received is actually transmitted one bit at a time, each bit being either 1 or 0.
Synchronous serial communication groups a number of characters into an information group, otherwise known as an information frame, the beginning of each frame being indicated by a synchronous character. Since both transmitting and receiving parties use the same clock, a clock signal is transmitted at the same time as the data so that the receiving party can use the clock signal to determine each information bit.
Synchronous serial communication requires that a continuous character bit stream be maintained throughout the transmission line, and if the computer has no data to transmit, the line is filled with dedicated "idle" characters or synchronous characters.
The number of bits of information transmitted by synchronous serial communication is almost unlimited, and generally, data transmitted by one communication has tens to thousands of bytes, so that the communication efficiency is higher. It requires precise synchronization clocks to be maintained in the communication, so that its transmitter and receiver are complex and costly, and are typically used in applications where transmission rates are high.
At present, synchronous serial ports are still applied in many occasions, such as military aircraft, aviation guidance, missile and rocket transportation and the like, so that the ground test equipment also needs to be synchronous serial ports. At present, PCIE interfaces of a computer and an industrial personal computer become the most basic peripheral interfaces, and communication and test of an extended synchronous serial port are realized through the interfaces, so that the PCIE interface becomes a good method.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a high-speed synchronous serial port module based on a PCIE bus.
The technical scheme of the invention is as follows:
the high-speed synchronous serial port module based on the PCIE bus is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge chip conversion circuit, a dual-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port receiving and transmitting circuit and a synchronous serial port connector circuit, wherein the FPGA protocol processing control circuit, the dual-port RAM data storage circuit, the PCIE bridge chip conversion circuit and the PCIE golden finger interface circuit are sequentially connected; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port receiving and transmitting circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and a 12V power supply, a 5V power supply, a reset signal RST, a homologous difference differential PCIE reference clock and a PCIE bus are introduced from the joint of the golden fingers; the PCIE bridge chip conversion circuit is used for converting PCIE serial buses into LOCAL BUS parallel buses and completing PCIE enumeration and mapping; the dual-port RAM data storage circuit is used for storing communication data, and is provided with two 70V28 chips of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip conversion circuit writes the needed sending data into a sending data buffer through a LOCAL BUS, and reads the received data from a receiving data buffer; the FPGA protocol processing control circuit is just opposite, generates LOCAL BUS through decoding to read and send data cache, and writes the data cache into the interface data cache, so that data exchange on two sides is realized.
The invention has the advantages and beneficial effects that: the PCIE golden finger is introduced into the PCIE high-speed serial bus, a high-speed synchronous serial bus protocol is realized through protocol conversion, communication with external equipment is realized through the high-speed transceiver, and the PCIE bus conversion high-speed synchronous serial port is realized.
Drawings
Fig. 1 is a connection schematic block diagram of a high-speed synchronous serial port module based on a PCIE bus provided by the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be the communication between the two parts. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
As shown in fig. 1, a PCIE bus-based high-speed synchronous serial port module includes a PCIE gold finger interface circuit, a power supply circuit, a PCIE bridge conversion circuit, a dual-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port transceiver circuit, and a synchronous serial port connector circuit, where the FPGA protocol processing control circuit, the dual-port RAM data storage circuit, the PCIE bridge conversion circuit, and the PCIE gold finger interface circuit are sequentially connected; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port receiving and transmitting circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and a 12V power supply, a 5V power supply, a reset signal RST, a homologous difference differential PCIE reference clock and a PCIE bus are introduced from the joint of the golden fingers; the PCIE bridge chip conversion circuit is used for converting PCIE serial buses into LOCAL BUS parallel buses and completing PCIE enumeration and mapping; the dual-port RAM data storage circuit is used for storing communication data, and is provided with two 70V28 chips of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip conversion circuit writes the needed sending data into a sending data buffer through a LOCAL BUS, and reads the received data from a receiving data buffer; the FPGA protocol processing control circuit is just opposite, generates LOCAL BUS through decoding to read and send data cache, and writes the data cache into the interface data cache, so that data exchange on two sides is realized.
The power supply circuit is a circuit for providing DC power conversion of the device, adopts an LTM4644 DC conversion module of ADI company to realize conversion of 12V main power supply and provides 3.3V, 2.5V, 1.8V and 1.2V secondary power supply for the rear-stage circuit.
The PCIE bridge chip conversion circuit is used for converting PCIE serial buses into LOCAL BUS parallel buses and completing PCIE enumeration and mapping, and a PEX8311 chip of PLX company is adopted, and configuration information is read from an EEPROM through an SPI interface when equipment is powered on to complete an enumeration process. And then converting the PCIE BUS into a LOCAL BUS, and reading and writing the later-stage storage circuit.
The FPGA protocol processing control circuit is used for communication data exchange, protocol conversion and data and clock synchronization; the protocol data processing is realized by adopting an EP3C5144I7 FPGA of ALTERA company, specifically, when data is transmitted, the data to be transmitted is packed, a transmission synchronous clock TXD_CLK is generated through a PLL phase-locked loop, and the data is sequentially transmitted to TXD according to a serial port protocol on the rising edge of the synchronous clock TXD_CLK. When receiving data, the clock rising edge latches the received RXD data in sequence under the excitation of the external input synchronous clock rxd_clk.
The signal isolation circuit is used for isolating the high-speed synchronous serial port receiving and transmitting circuit from each digital circuit at the front stage, 5V power supply is converted into 5V isolation power supply through Jin Shengyang B0505 isolation power supply, the power supply is supplied to the isolation chip ISO7240 of TI and the high-speed synchronous serial port receiving and transmitting circuit at the rear stage, 3.3V power supply is adopted for digital measurement, and the receiving and transmitting signals and clocks of the device are electrically isolated from the outside through the device.
The high-speed synchronous serial port transceiver circuit is used for receiving and transmitting data and clocks, converting and transmitting single-ended signals and differential signals, converting RXD and TXD into standard RS422 differential signals by adopting a MAX490 chip of Messaging company, and converting RXD_CLK and TXD_CLK into standard RS422 differential signals by adopting a MAX490 chip of Messaging company.
The synchronous serial port connector circuit is used for connecting the module with external equipment, and adopts a standard DB9 interface to connect the RXD, TXD, RXD _CLK and TXD_CLK differential signals and the isolated power supply GND with the external equipment so as to realize data communication.
The foregoing detailed description of the embodiments of the invention has been presented only to illustrate the preferred embodiments of the invention and should not be taken as limiting the scope of the invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (7)
1. The high-speed synchronous serial port module based on the PCIE bus is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge conversion circuit, a dual-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port receiving and transmitting circuit and a synchronous serial port connector circuit; the FPGA protocol processing control circuit, the dual-port RAM data storage circuit, the PCIE bridge chip conversion circuit and the PCIE golden finger interface circuit are connected in sequence; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port receiving and transmitting circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and a 12V power supply, a 5V power supply, a reset signal RST, a homologous difference differential PCIE reference clock and a PCIE bus are introduced from the joint of the golden fingers; the PCIE bridge chip conversion circuit is used for converting PCIE serial buses into LOCAL BUS parallel buses and completing PCIE enumeration and mapping; the dual-port RAM data storage circuit is used for storing communication data, and is provided with two 70V28 chips of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip conversion circuit writes the needed sending data into a sending data buffer through a LOCAL BUS, and reads the received data from a receiving data buffer; the FPGA protocol processing control circuit is just opposite, generates LOCAL BUS through decoding to read and send data cache, and writes the data cache into the interface data cache, so that data exchange on two sides is realized.
2. The PCIE bus-based high-speed synchronous serial port module according to claim 1 wherein the power supply circuit is a circuit for providing DC power conversion of the device, and the DC conversion module is used to realize conversion of 12V main power supply and provide 3.3V, 2.5V, 1.8V and 1.2V secondary power supply to the back-stage circuit.
3. The PCIE BUS-based high-speed synchronous serial port module according to claim 1 wherein the PCIE bridge slice conversion circuit is configured to convert a PCIE serial BUS into a LOCAL BUS parallel BUS and complete PCIE enumeration and mapping, read configuration information from an EEPROM through an SPI interface when the device is powered on, complete an enumeration process, then convert the PCIE BUS into the LOCAL BUS, and read and write a post-stage storage circuit.
4. The PCIE bus-based high-speed synchronous serial port module according to claim 1 wherein the FPGA protocol processing control circuit is configured to communicate data exchange, protocol conversion and data and clock synchronization; and the protocol data processing is realized by adopting an EP3C5144I7 FPGA, specifically, when data is transmitted, the data to be transmitted is packaged, a transmission synchronous clock TXD_CLK is generated through a PLL phase-locked loop, the TXD is sequentially transmitted according to a serial port protocol by the data at the rising edge of the synchronous clock TXD_CLK, and when the data is received, the RXD data is sequentially latched and received along the rising edge of the clock under the excitation of the external input synchronous clock RXD_CLK.
5. The PCIE bus-based high-speed synchronous serial port module according to claim 1 wherein the signal isolation circuit is configured to isolate the high-speed synchronous serial port transceiver circuit from each of the preceding stage digital circuits, convert a 5V power supply to generate a 5V isolated power supply by the isolated power supply, power the isolated chip ISO7240 and the subsequent stage high-speed synchronous serial port transceiver circuit, and use 3.3V power for digital measurement, and electrically isolate the device from external signals and clocks via the signal isolation circuit.
6. The PCIE bus-based high-speed synchronous serial port module according to claim 1 wherein the high-speed synchronous serial port transceiver circuit is configured to receive and transmit data and clocks, convert and transmit single-ended signals and differential signals, convert RXD and TXD into standard RS422 differential signals by using a MAX490 chip, and convert rxd_clk and txd_clk into standard RS422 differential signals by using a MAX490 chip.
7. The PCIE bus-based high-speed synchronous serial port module according to claim 1 wherein the synchronous serial port connector circuit is configured to connect the module with an external device, and connect the RXD, TXD, RXD _clk, txd_clk four sets of differential signals and the isolation power supply GND with the external device by using a standard DB9 interface to implement data communication.
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| CN202111240916.0A CN114116563B (en) | 2021-10-25 | 2021-10-25 | High-speed synchronous serial port module based on PCIE bus |
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| CN115442178B (en) * | 2022-08-31 | 2023-12-15 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
| CN115481063A (en) * | 2022-11-04 | 2022-12-16 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
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| CN206209088U (en) * | 2016-12-02 | 2017-05-31 | 广东电网有限责任公司汕头供电局 | A kind of zinc oxide arrester tester calibrating installation |
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