CN202617157U

CN202617157U - PCI express (PCIE) switched circuit

Info

Publication number: CN202617157U
Application number: CN 201120488041
Authority: CN
Inventors: 高毅; 余松涛; 麻晓博; 何立军; 吴�琳
Original assignee: AVIC No 631 Research Institute
Current assignee: AVIC No 631 Research Institute
Priority date: 2011-11-30
Filing date: 2011-11-30
Publication date: 2012-12-19
Anticipated expiration: 2021-11-30

Abstract

The utility model provides a PCI express (PCIE) switched circuit. The circuit comprises a processor unit of a PCIE signal, a switching unit and a plurality of sending and receiving function units. The processor unit is connected with an uplink interface of the switching unit. The function units are connected with a downlink interface of the switching unit respectively. By using the PCIE switched circuit of the utility model, high-speed interconnections among the plurality of function units in a system can be realized; and system performance and fault tolerance capability are effectively increased.

Description

A kind of PCIE switched circuit

Technical field

The utility model relates to a kind of switched circuit of embedded computer, relates in particular to a kind of PCIE switched circuit.

Background technology

Along with the development of embedded system, function from strength to strength, internal system needs the information processed amount increasing, dominant frequency is increasingly high, the interface rate of communication system will be higher also, need the bussing technique of a new generation to adapt with it.

PCI Express (hereinafter to be referred as PCIE) bus possesses high bandwidth, high-performance, low delay, low-power consumption and transmits advantages such as reliable, is applied to embedded computer system inside and not only can higher bandwidth can also be provided with existing PCI technical compatibility; Make a plurality of PCIE apparatus interconnections become possibility, surmounted the bottleneck that traditional PCI bus can only the internal system interconnection; Improved the point-to-point transmission of equipment room, made that equipment can intercom quickly and easily mutually in the system.

Switching technology based on the PCIE bus is applied in the embedded computer, can realize the high-speed interconnect between a plurality of functional units of internal system; Realize as independent crosspoint, help generalization, standardization and the miniaturization of each functional unit, make things convenient for system maintenance simultaneously, improved Percent Isolated, and then improved system survivability.

The utility model content

In order to solve existing technical problem in the background technology, the utility model provides a kind of PCIE switched circuit, can realize the high-speed interconnect between a plurality of functional units of internal system, effectively improve systematic function and fault-tolerant ability.

The technical solution of the utility model is: a kind of PCIE switched circuit; Its special character is: said PCIE switched circuit comprises crosspoint and a plurality of functional unit of PCIE Signal Processing device unit, PCIE signal, and said processor unit is connected with the upstream Interface of crosspoint; Said functional unit is connected with the downstream interface of crosspoint respectively.

Above-mentioned processor unit comprises PCIE ROOT interface circuit, and said PCIE ROOT interface circuit is connected with the crosspoint upstream Interface.

Above-mentioned a plurality of functional unit is that parallel mode is connected with a plurality of downstream interfaces of crosspoint respectively.

The above-mentioned functions unit comprises a PCIE interface circuit respectively, and said PCIE interface circuit is connected with the downstream interface of crosspoint respectively.

Above-mentioned crosspoint comprises 100MHz difference crystal oscillator, clock driver, exchange chip and storage chip, and said clock driver, exchange chip and storage chip are connected successively.

Above-mentioned PCIE ROOT interface circuit is realized to the bridging chip of the conversion of PCIE bus through 32bit 66MHz pci bus.

Above-mentioned PCIE interface circuit comprises the bridger of realizing PCIE single channel port, realize LOCAL BUS to the FPGA of the control data of internal resource, the 5V power source conversion is become the required power-switching circuit that respectively keeps off power supply in inside, and said FPGA, power-switching circuit are connected with bridger respectively.

Above-mentioned exchange chip is the PI7C9X20508GPANDE exchange chip.

Above-mentioned clock driver is PIC620800AE.

PCIE switched circuit of the present invention has adopted the PCIE interconnection technique; The PCIE switching technology is applied in the embedded computer; Realize the high-speed interconnect between a plurality of functional units of internal system, compare that PCIE has accelerated transmission rate with embedded computer interconnected mode in the past; Strengthen signal quality, improved systematic function;

By crosspoint the integrated system clock is provided, has ensured the high speed signal quality; The PCIE switching technology realizes as independent crosspoint; Be connected to the PCIE bus with original each unit through PCIE bridge sheet and compare, help generalization, standardization and the miniaturization of each functional unit, make things convenient for system maintenance simultaneously; Improve Percent Isolated, and then improved system survivability;

This embedded system internal transfer rate has reached 2.5Gbps, has realized multichannel full-duplex communication; Through software scans each equipment on the PCIE bus, each unit in the control system.

Description of drawings

Fig. 1 is the switched circuit structure chart of the utility model;

Fig. 2 is the crosspoint structure chart of the utility model switched circuit;

Fig. 3 is the clock driver structure chart of the utility model switched circuit;

Fig. 4 is a PCIE ROOT interface circuit sketch map;

Fig. 5 is a PCIE interface circuit sketch map;

Embodiment

Referring to Fig. 1; The utility model provides a kind of PCIE switched circuit; Comprise the crosspoint 2 and a plurality of functional unit 3 that send PCIE Signal Processing device unit 1, exchange PCIE signal; Processor unit 1 is connected with the upstream Interface 21 of crosspoint, and functional unit 3 is connected with the downstream interface 22 of crosspoint respectively; Processor unit 1 comprises PCIE ROOT interface circuit, and PCIE ROOT interface circuit is connected with crosspoint upstream Interface 21; A plurality of functional units 3 are that parallel mode is connected with a plurality of downstream interfaces 22 of crosspoint respectively.Functional unit 3 comprises a PCIE interface circuit 31 respectively, and PCIE interface circuit 31 is connected with the downstream interface 22 of crosspoint respectively;

The principle of total framework of the utility model is: the PCIE bus adopts processor bridge mode to be applied between the unit internal processor more usually; When systemic-function is tending towards complicated, processor independently becomes processor unit, and when each functional circuit develops into each independent functional units, the PCIE bus of bridge mode also will be evolved and expanded to embedded system inside for exchanged form.Realize PCIE ROOT interface function by processor unit in this example; Other functional units are realized the conversion of PCIE bus to LOCAL BUS bus through the PCIE interface circuit; Crosspoint is connected to processor unit through line interface on the way, and the multichannel downstream interface connects other functional units.

The PCIE circuit design mainly comprises following 3 points: 1) the PCIE crosspoint 2; 2) processor unit PCIE ROOT interface circuit; The PCIE interface circuit 31 of each functional unit 3.

The PCIE crosspoint provides maximum 8 ports, and the exchanges data between the PCIE EBI of the highest 4-lane adopts switch/exchange chip to provide a plurality of PCIE passages to realize the transfer of data between the unit.

Referring to Fig. 2, Fig. 3, crosspoint 2 mainly comprises following functional block: reset circuit; Clock driver 23; Voltage conversion circuit; Exchange chip 24, storage chip 25; Exchange chip 24 comprises I2C serial line interface, PCIE interface, jtag interface.Clock driver is PIC620800AE; Exchange chip 24 adopts the PI7C9X20508GPANDE exchange chip of PERICOM company; Maximum 8 ports are provided; Exchanges data between the PCIE EBI of the highest 4-lane, integrated following functional unit: the 1) PCIEs switch/exchange chip of 8-lane working method; 2) 8 road PCIE communication channels (* 1, * 2, * 4) are provided at most; 3) each port all provides a tunnel interface; 4) every passage all provides full rate communication transmission; 5) point-to-point exchanges data and central host are sent; 6) 3 standard hot-plug controllers are supported PCI SHPC V1.0; 7) main frame, I2C, three kinds of configuration modes of EEPROM are provided; 8) jtag interface is provided, supports boundary scan technique.

Be designed with storage chip 25 on the crosspoint 2, storage chip 25 is eeprom memories, is used for memory transactions chip configuration information.The unit can directly read the configuration information that is stored among the EEPROM and realize correct configuration after powering on; Also can dispose to accomplish through the configuration information that the reception signal processing unit sends.

Clock Generation Circuit is characteristics of the utility model.It is 7 tunnel clock signals that the clock signal that 100MHz difference crystal oscillator provides drives via multipath clock driver 23, and wherein one tunnel clock signal supplies exchange chip 24 to use, and all the other 6 tunnel clock signals supply the functional unit 3 on the PCIE bus to use.Incogruent each functional unit in the past of this homology clock circuit implementation uses the mode of differential clocks circuit separately; Effectively raise signal quality; Strengthen transmission stability, simplified system design, solved the unified difficult problem of clock signal in the high speed transmission of signals cleverly.

Referring to Fig. 4, Fig. 5, PCIE ROOT interface circuit realize the conversion of 32bit 66MHz pci bus to the PCIE bus, and its core circuit is a slice bridging chip, and circuit structure is as shown in Figure 4.PCIE interface circuit 31 structures are as shown in Figure 5, and in this circuit, bridger is realized PCIE single channel port (X1 pattern), and data transmission rate is 2.5Gbps.FPGA realizes the control of LOCAL BUS to internal resource.Power-switching circuit realize with the 5V power source conversion become inner required respectively keep off power supply (1.5V, 2.5V, 3.3V).

Claims

1. PCIE switched circuit is characterized in that: said PCIE switched circuit comprises crosspoint and a plurality of functional unit that sends PCIE Signal Processing device unit, PCIE signal, and said processor unit is connected with the upstream Interface of crosspoint; Said functional unit is connected with the downstream interface of crosspoint respectively.

2. PCIE switched circuit according to claim 1 is characterized in that: said processor unit comprises PCIE ROOT interface circuit, and said PCIE ROOT interface circuit is connected with the crosspoint upstream Interface.

3. PCIE switched circuit according to claim 2 is characterized in that: said a plurality of functional units are that parallel mode is connected with a plurality of downstream interfaces of crosspoint respectively.

4. PCIE switched circuit according to claim 3 is characterized in that: said functional unit comprises a PCIE interface circuit respectively, and said PCIE interface circuit is connected with the downstream interface of crosspoint respectively.

5. PCIE switched circuit according to claim 4 is characterized in that: said crosspoint comprises 100MHz difference crystal oscillator, clock driver, exchange chip and storage chip, and said clock driver, exchange chip and storage chip are connected successively.

6. PCIE switched circuit according to claim 5 is characterized in that: said PCIE ROOT interface circuit is to realize the bridging chip of 32bit 66MHz pci bus to the conversion of PCIE bus.

7. PCIE switched circuit according to claim 6 is characterized in that: said PCIE interface circuit comprises the bridger of realizing PCIE single channel port, realize that LOCAL BUS is to the FPGA of the control data of internal resource, become the required power-switching circuit that respectively keeps off power supply in inside with the 5V power source conversion; Said FPGA, power-switching circuit are connected with bridger respectively.

8. PCIE switched circuit according to claim 7 is characterized in that: said exchange chip is the PI7C9X20508GPANDE exchange chip.

9. PCIE switched circuit according to claim 8 is characterized in that: said clock driver is PIC620800AE.