CN115481063A - Distributed high-speed signal receiving and transmitting processing system - Google Patents
Distributed high-speed signal receiving and transmitting processing system Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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Abstract
The invention discloses a distributed high-speed signal transceiving processing system, which comprises a front-end signal transceiver, a high-speed bus adapter and a rear-end signal processor, wherein the high-speed bus adapter comprises a main lightning interface and a cascading lightning interface, the front-end signal transceiver is connected with the high-speed bus adapter through PCIE cable communication, the high-speed bus adapter is connected with the rear-end signal processor through the main lightning interface communication, the high-speed bus adapter is connected with an extended high-speed bus adapter through the cascading lightning interface communication, the extended high-speed bus adapter is connected with a next extended high-speed bus adapter through the internal cascading lightning interface communication, and the extended high-speed bus adapter is provided with an extended PCIE cable interface; therefore, the invention can realize remote distributed connection physically, has the advantages of small size, strong calculation power, low cost, hot plugging, flexible combination, remote connection and distributed expansion, and is suitable for large-scale application and popularization.
Description
Technical Field
The invention belongs to the technical field of high-speed signal receiving, transmitting and processing, and particularly relates to a distributed high-speed signal receiving, transmitting and processing system.
Background
With the rapid development of analog circuits, digital circuits and signal processing technologies, the demands for high-speed signal transceiving and real-time signal processing are increasing, applications in the fields of radar, communication, transient signals, complex electromagnetic environments and the like involve receiving and transmitting high-bandwidth or high-speed signals, and high-performance computing demands for real-time analysis and real-time generation of signals exist, especially, when researchers perform external field multichannel signal transceiving and processing, portable, remote and distributed signal transceiving and processing systems are required, therefore, high-speed signal transceiving systems have come into force, the systems generally need to use sampling rates of hundreds of MS/s to 1GS/s, even ADCs (analog-to-digital converters) and DACs (digital-to-analog converters) above 1GS/s to acquire or transmit analog signals, so that the data rate of generated digital signals can reach several GB/s, not only the distance and rate requirements for data transmission are high, but also the real-time processing performance requirements for data are high, and if a distributed multichannel system needs to be constructed, the data volume and the requirements for both increasing and processing and the high-variable data transmission rate, and the high-performance requirements for transmission and the high-variable communication characteristics of the systems are difficult to be combined.
At present, equipment capable of receiving and transmitting high-speed and high-bandwidth signals, especially equipment capable of simultaneously processing real-time signals, mainly commercial desktop instruments and special customized equipment, a commercial desktop instrument system is usually designed for indoor desktop working scenes, such as common real-time spectrum analyzers, high-speed arbitrary waveform generators, vector signal transceivers and the like, and although the equipment has the advantages of high index and strong function, the equipment is provided with a plurality of internal components, is large in size, heavy in weight and high in power consumption, and the equipment can not meet changeable user application requirements often due to fixed function, and can not be applied to portable, remote and distributed deployment application scenes.
The special customization equipment can realize good matching of user requirements through software and hardware customization, but often because hardware, a driver, application software and the like need customization realization, the design optimization iteration times are few, the maturity is low, the usability is poor, the expansion capability is weak, the upgradable maintainability is poor, the size, the weight and the power consumption are difficult to realize in an ideal state, especially for remote and distributed signal transceiving and processing systems, high-speed long-distance communication connection needs to be established among a plurality of subsystems, so that a high-speed serial interface or a high-speed Ethernet is usually adopted for connecting an upper computer and a lower computer, so that distributed expansion is realized, common high-speed serial protocols such as a RapidIO protocol and an Aurora (an extensible lightweight link layer protocol for moving data between point-to-point serial links), although the requirements on functions and performances can be met, the hardware and software standardization and development complexity are high, and the cost and the maintenance upgrading difficulty are caused; however, if a high-speed ethernet interface is adopted, although the system construction cost can be reduced, the IP network needs switches to construct a multi-node topology, and the data transmission delay jitter is large, which cannot meet the requirements for some applications requiring real-time closed-loop response.
Meanwhile, no matter a system is constructed by utilizing RapidIO, aurora or IP network, system programs of an upper computer and a lower computer need to be independently developed, especially the development difficulty is obviously increased when a distributed multi-channel system is involved, and the unified system structure is difficult to adapt to the requirements of users with multiple changed ends; therefore, it is urgent to provide a small-sized signal transmission/reception processing system that has a simple structure, is highly scalable, and is easy to develop.
Disclosure of Invention
The invention aims to provide a distributed high-speed signal transceiving processing system, which is used for solving the problems of large volume, heavy weight and incapability of being applied to portable, remote and distributed deployment application scenes of commercial desktop instruments, and the problems of weak expansion capability, poor upgradeable maintainability and high development difficulty of special customized equipment.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a distributed high-speed signal transceiving processing system, including: the system comprises a front-end signal transceiver, a high-speed bus adapter and a rear-end signal processor;
the high-speed bus adapter comprises a main lightning interface and a cascade lightning interface, wherein the front-end signal transceiver is in communication connection with the high-speed bus adapter through a PCIE cable and is used for transmitting a first signal sent by external equipment to the high-speed bus adapter or receiving a second signal sent by the high-speed bus adapter;
the high-speed bus adapter is in communication connection with the rear-end signal processor through the main lightning interface and is used for sending the first signal to the rear-end signal processor or receiving a second signal sent by the rear-end signal processor;
the high-speed bus adapter passes through cascade thunder and lightning interface communication connection extension high-speed bus adapter, wherein, extension high-speed bus adapter is through the next extension high-speed bus adapter of inside cascade thunder and lightning interface communication connection to realize cascade connection between high-speed bus adapter and a plurality of extension high-speed bus adapters, just extension high-speed bus adapter is provided with extension PCIE cable interface, is used for passing through extension PCIE cable interface communication connection extension front end signal transceiver, in order to realize cascade connection between front end signal transceiver and a plurality of extension front end signal transceiver.
Based on the above disclosure, the invention decomposes the traditional transceiver system integrating three functions of signal transceiving and processing, fast equipment cascade connection and high-speed data transmission, and signal processing and system control into three subsystems of a front-end signal transceiver, a high-speed bus adapter and a rear-end signal processor, the design can fully decouple and standardize the system functions, and can realize high integration of the whole system while being easily combined into a complex distributed system, and simultaneously, each subsystem has corresponding functions and can greatly reduce the size of the whole system, thereby not only reducing the cost and facilitating portable application, but also realizing high-precision calculation and processing of signals.
Secondly, the front-end signal transceiver adopts the PCIE cable to be connected with the high-speed bus adapter, and the high-speed bus adapter is through thunder and lightning interface connection rear-end signal processor, therefore, integration and interconversion of thunder and lightning technique and cable formula PCIE technique have been realized, make entire system possess high-speed communication, but the hot plug, the characteristic of low delay and long distance transmission, and simultaneously, every high-speed bus adapter all is equipped with cascading thunder and lightning interface, usable cascading thunder and lightning interface connects extension high-speed bus adapter, and extension high-speed bus adapter is provided with extension PCIE cable interface, based on this, cascade among a plurality of high-speed bus adapters and the cascade of a plurality of front-end signal transceivers are realized to the last cascading thunder and extension PCIE interface of every high-speed bus adapter, thereby improve the scalability of system by a wide margin, satisfy the user demand of different application fields.
Finally, the high-speed bus adapter is connected with the front-end signal transceiver based on the PCIE technology, so that all the front-end signal transceivers can be identified as local PCIE equipment in the rear-end signal processor, and therefore, the equipment is accessed and controlled by adopting the PCIE technology, compared with the equipment which is accessed and controlled by a remote device through Ethernet, aurora and RapidIO protocols, the development complexity of the system is greatly reduced.
Through the design, the system can physically realize remote distributed connection, has small size, strong computing power and low cost, has the advantages of hot plug, flexible combination, remote connection and distributed expansion, and is suitable for large-scale application and popularization.
In one possible design, the front-end signal transceiver includes: the system comprises a first cable type PCIE connector, a first FPGA processing unit, a data conversion unit and an analog front end;
the first transmission end of the first cable-type PCIE connector is in communication connection with the high-speed bus adapter through the PCIE cable and is used for receiving the second signal, and the second transmission end of the first cable-type PCIE connector is in communication connection with the first receiving end of the first FPGA processing unit and is used for inputting the second signal into the first FPGA processing unit for signal processing to obtain a processed second signal;
the first sending end of the first FPGA processing unit is in communication connection with the digital signal input end of the data conversion unit and is used for inputting the processed second signal into the data conversion unit for digital-to-analog conversion to obtain an analog second signal;
an analog signal output end of the data conversion unit is in communication connection with the analog front end and is used for transmitting the analog second signal to the external equipment through the analog front end;
the analog front end is further configured to receive a first signal sent by the external device, and the analog front end is communicatively connected to an analog signal input end of the data conversion unit and configured to input the first signal to the data conversion unit for analog-to-digital conversion to obtain a digital first signal;
a digital signal output end of the data conversion unit is in communication connection with a second receiving end of the first FPGA processing unit and is used for transmitting the digital first signal to the first FPGA processing unit for signal processing to obtain a processed first signal;
the second transmitting end of the first FPGA processing unit is communicatively connected to the second transmitting end of the first cable-type PCIE connector, and is configured to transmit the processed first signal to the high-speed bus adapter through the first cable-type PCIE connector.
In one possible design, the front-end signal transceiver further includes: a clock and trigger signal interface, a phase-locked loop control unit and an oven controlled crystal oscillator;
the clock and trigger signal interface is electrically connected with the phase-locked loop control unit and used for sending a received external clock signal to the phase-locked loop control unit, and the constant-temperature crystal oscillator is electrically connected with the phase-locked loop control unit and used for generating a time base signal and sending the time base signal to the phase-locked loop control unit;
the phase-locked loop control unit is used for generating a system clock signal according to the external clock signal and the time base signal so as to enable the front-end signal transceiver and the extended front-end signal transceiver to synchronously run based on the system clock signal;
the clock and trigger signal interface is also electrically connected with the first FPGA processing unit and used for sending the received trigger signal to the first FPGA processing unit so that the first FPGA processing unit triggers an internal processing mechanism based on the trigger signal.
Based on the above disclosure, the front-end signal transceiver of the present invention is further provided with a clock and trigger signal interface, an oven controlled crystal oscillator, and a phase-locked loop control unit based on a phase-locked loop mechanism, wherein the clock and trigger signal interface is configured to receive an external clock signal and a trigger signal, and the oven controlled crystal oscillator is configured to generate a time-based signal, so that the phase-locked loop control unit can generate a system clock signal based on the time-based signal and the external clock signal, thereby ensuring that a plurality of front-end signal transceivers connected in parallel or in a distributed manner can simultaneously operate to achieve synchronous receiving and transmitting of a plurality of signals when a plurality of front-end signal transceivers exist, and meanwhile, the first FPGA processing unit can trigger an internal processing logic based on the trigger signal to perform corresponding signal processing for subsequent signal receiving or transmitting.
In one possible design, the high-speed bus adapter further includes: the lightning protection device comprises a second cable type PCIE connector, a two-way PCIE clock generator and a lightning controller;
a first transmission end of the second cable-type PCIE connector is in communication connection with the front-end signal transceiver through the PCIE cable, and a second transmission end of the second cable-type PCIE connector is in communication connection with the lightning controller, wherein the two-way PCIE clock generator is in communication connection with the second cable-type PCIE connector and the lightning controller respectively, and the lightning controller is in communication connection with a main lightning interface so as to be in communication connection with the rear-end signal processor based on the main lightning interface;
the extension high-speed bus adapter is in communication connection with the lightning controller through the cascading lightning interfaces, so that when a plurality of extension high-speed bus adapters exist, the high-speed bus adapters and the extension high-speed bus adapters are in cascading connection based on the cascading lightning interfaces on each extension high-speed bus adapter.
Based on the above disclosure, the invention discloses a specific structure of a high-speed bus adapter, wherein a second cable-type PCIE connector is arranged on the adapter, and the adapter establishes communication connection with a first cable-type PCIE connector on a front-end signal transceiver through a PCIE cable to realize transmission and reception of signals, and meanwhile, a lightning controller is matched with a two-way PCIE clock generator to connect the second cable-type PCIE connector, so that the highest transmission rate of 32GB/s can be realized, and the transmission delay can be as low as microsecond level, thereby the requirement of high-speed data transmission can be met; in addition, the high-speed bus adapter is connected with the expansion high-speed bus adapter through the cascade lightning interface, the expansion high-speed bus adapter is connected with the next expansion high-speed bus adapter through the internal cascade lightning interface, and based on the connection, the cascade connection between the bus adapter and the expansion high-speed bus adapters can be realized, so that the expandability of the system is greatly improved.
In one possible design, the high speed bus adapter further includes: a first USB port controller, a second USB port multiplexer, and a third USB port controller;
the cascade lightning interface is also respectively in communication connection with the first USB port controller and the second USB port multiplexer, wherein the first USB port controller and the second USB port multiplexer are respectively in communication connection with the lightning controller through an I2C bus, and the second USB port multiplexer is also in communication connection with the main lightning interface;
the main lightning interface is also in communication connection with the lightning controller through the third USB port controller, so that USB communication with the lightning controller is realized based on the third USB port controller.
Based on the disclosure, the invention is further provided with three USB port controllers, wherein the first USB port controller and the third USB port controller are USB3.1 port controllers, and the second USB port multiplexer is a USB2.0 port multiplexer, and when the invention is applied specifically, the first USB port controller and the third USB port controller are connected to the lightning controller and the cascade lightning interface through the USB2.0 port controller, so that the control connection of the lightning controller and the cascade connection of the USB2.0 interface can be realized, and meanwhile, the cascade lightning interface of the high-speed bus adapter can realize USB communication for the high-speed bus adapter by matching with the first USB port controller, and the connection path of the second USB port multiplexer and the first USB port controller can be used for performing parameter configuration and data reading on each functional component in the high-speed bus adapter and the cascaded extended high-speed bus adapter.
In one possible design, the high speed bus adapter further includes: a first power circuit, wherein the first power circuit is electrically connected to the primary lightning interface for powering the high-speed bus adapter based on the primary lightning interface.
In one possible design, the back-end signal processor includes: the system comprises a central processing unit, an image processing unit, a second FPGA processing unit, a main board chip, a slave lightning controller and a slave lightning interface;
the central processing unit is respectively in communication connection with the image processing unit and the second FPGA processing unit, the central processing unit is also in communication connection with the slave lightning controller through the mainboard chip, and the slave lightning controller is in communication connection with the high-speed bus adapter through the slave lightning interface so as to receive a first signal sent by the high-speed bus adapter and send a second signal to the high-speed bus adapter.
In one possible design, the back-end signal processor further includes: the second power circuit is respectively and electrically connected with the slave lightning interface and the fourth USB port controller and is used for supplying power to the rear-end signal processor through the slave lightning interface;
the slave lightning interface is also in communication connection with the fourth USB port controller and is used for realizing USB communication based on the fourth USB port controller.
In one possible design, the motherboard chip is further electrically connected with a peripheral device, and the central processing unit and the image processing unit, and the central processing unit and the second FPGA processing unit are connected by PCIE buses.
In one possible design, the PCIE cable includes: PCIE copper wire cable or PCIE fiber optic cable, and the extension PCIE cable interface includes PCIE Gen 3x4 bus interface, PCIe Gen1 x4 bus interface or PCIE Gen 2x4 bus interface.
The invention has the following beneficial effects:
(1) The invention designs a high-speed bus adapter, and a signal receiving and transmitting component and a signal processing component are independently decoupled into a front-end signal transceiver and a rear-end signal processor; due to the design, each independent component can utilize a standardized and highly integrated commercial technology, customization and development are greatly reduced, the size of each component can be greatly reduced, and high-performance calculation and processing can be realized while the cost is reduced; meanwhile, the customization requirement can be met by changing the design of the front-end signal transceiver, so that the cost of customization modification and design is reduced, and the customization period is shortened.
(2) Based on a cascading thunder and lightning interface and an expanding PCIE cable interface, the cascading of a plurality of high-speed bus expanding interfaces and a plurality of front-end signal transceivers can be realized, so that the expandability of the system is greatly improved to meet the use requirements of different fields and environments, meanwhile, the front-end signal transceivers are connected with a rear-end signal processor, and the interconversion between the PCIE technology and the thunder and lightning interface technology is realized through a high-speed bus adapter, so that the system has the advantages of the PCIE technology and the thunder and lightning interface technology, namely, the system realizes the characteristics of high-speed communication, cascading and hot plugging, and the rear-end signal processor can still finish the access and the starting of equipment in a starting state; in addition, the front-end signal transceiver designs an external sampling clock, a reference clock, a GPS pulse per second and trigger signal receiving and triggering logic, and can realize the synchronization and triggering work among a plurality of front-end signal transceivers, thereby completing the receiving and transmitting of equipment and distributed coherent signals, and enabling the system to be also used for applications such as array signal receiving and transmitting or MIMO (multiple input multiple output) systems.
(3) The system uses PCIE technology to realize the communication connection between the front-end signal transceiver and the high-speed bus adapter, therefore, all the front-end signal transceivers can be identified as local PCIE equipment in the rear-end signal processor, compared with the traditional method that the equipment is remotely connected by using communication protocols such as Ethernet, rapidIO or Aurora, the management complexity and the development complexity of the system are simpler, and in addition, the system can also inherit the advantages of large data transmission bandwidth and low transmission delay of the PCIE bus.
(4) By designing the FPGA coprocessor in the distributed front-end signal transceiver and designing the CPU, the GPU image processor and the FPGA coprocessor in the centralized rear-end signal processor, the distributed edge calculation and the centralized heterogeneous calculation capability are realized, so that the large-scale distributed signal processing and high-performance rear-end signal processing of multiple nodes are realized, and the calculation requirements of distributed high-bandwidth or high-speed signal processing application are met.
Drawings
Fig. 1 is a schematic diagram of a distributed high-speed signal transceiving processing system according to the present invention;
fig. 2 is a schematic structural diagram of a front-end signal transceiver according to the present invention;
FIG. 3 is a schematic structural diagram of a high-speed bus adapter according to the present invention;
FIG. 4 is a schematic structural diagram of a back-end signal processor according to the present invention;
fig. 5 is a structural diagram of a first distributed high-speed signal transceiving processing system based on PCIE copper wire cable connection provided in the present invention;
fig. 6 is a structural diagram of a second distributed high-speed signal transceiving processing system based on PCIE copper cable connection according to the present invention;
fig. 7 is a structural diagram of a first distributed high-speed signal transceiving processing system based on PCIE optical fiber cable connection provided in the present invention;
fig. 8 is a structural diagram of a second distributed high-speed signal transceiving processing system based on PCIE optical fiber cable connection provided in the present invention;
fig. 9 is a circuit diagram of a second cable-type PCIE connector provided in the present invention;
FIG. 10 is a circuit diagram of a cascading lightning interface provided by the present invention;
fig. 11 is a circuit diagram of a two-way PCIE clock generator provided in the present invention;
FIG. 12 is an overall circuit diagram of a first portion of a lightning controller provided by the invention;
FIG. 13 is a detailed circuit diagram at A of FIG. 12 according to the present invention;
FIG. 14 is a detailed circuit diagram at B of FIG. 12 according to the present invention;
FIG. 15 is a detailed circuit diagram at C of FIG. 12 provided in accordance with the present invention;
FIG. 16 is a detailed circuit diagram at D of FIG. 12 provided in accordance with the present invention;
FIG. 17 is an overall circuit diagram of a second portion of the lightning controller provided by the present invention;
FIG. 18 is a detailed circuit diagram at A of FIG. 17 provided in accordance with the present invention;
FIG. 19 is a detailed circuit diagram at B of FIG. 17 provided in accordance with the present invention;
FIG. 20 is a specific circuit diagram at C of FIG. 17 according to the present invention
FIG. 21 is a circuit diagram of a third portion of a lightning controller provided by the invention;
FIG. 22 is a circuit diagram of a fourth portion of a lightning controller provided by the invention;
FIG. 23 is a circuit diagram of a fifth portion of a lightning controller provided by the present invention;
FIG. 24 is a circuit diagram of a USB3.1 port controller provided in accordance with the present invention;
FIG. 25 is a circuit diagram of a USB2.0 port controller provided in accordance with the present invention;
FIG. 26 is a circuit diagram of a non-volatile memory provided by the present invention;
fig. 27 is a circuit diagram of a first power supply circuit provided by the present invention;
FIG. 28 is a circuit diagram of a primary lightning interface provided by the present invention for connection to a back end signal processor.
Detailed Description
Examples
Referring to fig. 1 to 4, the distributed high-speed signal transceiving processing system provided in the first aspect of this embodiment may include, but is not limited to: the system comprises a front-end signal transceiver, a high-speed bus adapter and a rear-end signal processor, wherein the high-speed bus adapter is connected with the front-end signal transceiver through a PCIE (peripheral component interconnect express) cable and a main lightning interface respectively through conversion adaptation of the PCIE cable and the main lightning interface, and is connected with the rear-end signal processor through the main lightning interface to realize a high-speed and low-delay data transmission link between the front-end signal transceiver and the rear-end signal processor, meanwhile, the front-end signal transceiver is responsible for receiving a second signal transmitted by the high-speed bus adapter or transmitting a first signal transmitted by external equipment, and meanwhile, preprocessing and real-time feedback or control of the signal can be completed inside the front-end signal transceiver, and the rear-end signal processor is responsible for receiving the first signal transmitted by the front-end signal transceiver or transmitting a second signal to the front-end signal transceiver, carrying out real-time signal processing, man-machine interaction, hardware control, data management and the like of the whole set of equipment.
In a specific application, for example, the high-speed bus adapter may include, but is not limited to: the lightning interface comprises a main lightning interface, wherein the front-end signal transceiver is in communication connection with the high-speed bus adapter through a PCIE cable and is used for transmitting a first signal sent by an external device to the high-speed bus adapter or receiving a second signal sent by the high-speed bus adapter.
Meanwhile, the high-speed bus adapter is in communication connection with the rear-end signal processor through the main lightning interface and is used for sending the first signal to the rear-end signal processor or receiving a second signal sent by the rear-end signal processor; therefore, the invention is equivalent to decomposing the traditional receiving and transmitting system integrated with three functions of signal receiving and transmitting and controlling, signal high-speed transmission and signal processing into the three subsystems of the front-end signal transceiver, the high-speed bus adapter and the rear-end signal processor, thereby fully decoupling and standardizing the functions of the traditional system, realizing the high integration degree of the whole system while the three subsystems are easily combined into a complex distributed system, and in addition, decomposing the traditional receiving and transmitting system into the three subsystems can also greatly reduce the size of the whole system, thereby not only reducing the cost, but also being convenient for portable application.
In addition, because the system uses the PCIE technology to realize the communication connection between the front-end signal transceiver and the high-speed bus adapter, all the front-end signal transceivers are recognized as local PCIE devices in the back-end signal processor, and the PICE technology is used to access and control the devices, compared with the traditional remote connection device using the communication protocols such as ethernet, rapidIO, or Aurora, the management complexity and the development complexity are simpler, so that the entire system is physically a distributed remote connection structure, but the back-end signal processor is a local device.
Furthermore, in order to improve the expandability of the system and meet the signal transceiving requirements of different use environments and fields, the embodiment further arranges a cascading thunder and lightning interface on the high-speed bus adapter, and when in specific application, the high-speed bus adapter is connected with the expanding high-speed bus adapter through the cascading thunder and lightning interface in a communication manner, wherein the expanding high-speed bus adapter is connected with the next expanding high-speed bus adapter through the cascading thunder and lightning interface in the expanding high-speed bus adapter in a communication manner; through the design, the high-speed bus adapter is connected with an expansion high-speed bus adapter through the cascading thunder interface, the expansion high-speed bus adapter can also be connected with the next expansion high-speed bus adapter through the internal cascading thunder interface, and therefore, the connection operation is repeated, a plurality of expansion high-speed bus adapters can be connected into the system, and the cascading connection between the high-speed bus adapter and the expansion high-speed bus adapters is achieved.
Correspondingly, in this embodiment, an extended PCIE cable interface is further disposed on the extended high-speed bus adapter, and is used to connect an extended front-end signal transceiver through the extended PCIE cable interface in a communication manner, so that an extended front-end signal transceiver can be connected when introducing one extended high-speed bus adapter, and through the above design, the cascade connection between the front-end signal transceiver and the multiple extended front-end signal transceivers can be implemented.
In this embodiment, for example, the extended PCIE cable interface includes a PCIE Gen 3x4 bus interface, a PCIE Gen1 x4 bus interface, or a PCIE Gen 2x4 bus interface.
Therefore, based on the cascade lightning interface and the extension PCIE cable interface, the cascade connection of a plurality of high-speed bus extension interfaces and a plurality of front-end signal transceivers can be realized, thereby greatly improving the expandability of the system, and adapting to the use requirements of different fields and environments, meanwhile, the connection of the front-end signal transceiver and the rear-end signal processor realizes the mutual conversion between the PCIE technology and the lightning interface technology through the high-speed bus adapter, therefore, the system has the advantages of the PCIE technology and the lightning interface technology, namely, the front-end signal transceiver can adopt the PCIE copper wire cable to realize short-distance transmission, and realize the long-distance transmission of the PCIE pipeline cable, thereby realizing the transmission of portable and long-range signals, and the lightning interface technology has the characteristic of hot plug and pull, and is very convenient for the extension of any type of equipment, therefore, not only can provide the bidirectional 40Gbps output transmission, but also can enable the whole system to support the hot plug and pull mechanism, so that the rear-end signal processor can still complete the access and the start of the equipment in the broadband processing and form a distributed type hot plug and pull system in the startup state.
To further illustrate the system provided in this embodiment, the following detailed structures of the front-end signal transceiver, the high-speed bus adapter, and the back-end signal processor are described:
first, the front-end signal transceiver may include, but is not limited to: the system comprises a first cable type PCIE connector, a first FPGA processing unit, a data conversion unit and an analog front end; in this embodiment, the front-end signal transceiver has signal receiving and transmitting functions, so the following describes the specific structure of the front-end signal transceiver with the above two functions respectively:
referring to fig. 2, for receiving the second signal transmitted from the high-speed bus adapter, the connection structure is as follows:
in this embodiment, on one hand, signal processing in the first FPGA processing unit performs preprocessing on the second signal based on the characteristic of high-speed parallel fixed-point number calculation, such as coding and decoding and/or closed-loop feedback control, and on the other hand, extraction and compression of valid data can be completed, so that the amount of data transmitted between the first FPGA processing unit and the back-end signal processor is reduced, and meanwhile, the first FPGA processing unit has ns-level signal processing delay and can meet requirements for signal processing and transmission.
After the second signal is subjected to signal processing, the processed second signal needs to be sent to a data conversion unit for corresponding data conversion, that is, a first sending end of the first FPGA processing unit is communicatively connected to a digital signal input end of the data conversion unit and is used for inputting the processed second signal to the data conversion unit for digital-to-analog conversion to obtain an analog second signal, and an analog signal output end of the data conversion unit is communicatively connected to the analog front end and is used for transmitting the analog second signal to the external device through the analog front end; thus, the transmission of the second signal to the external device can be completed.
Similarly, for sending the first signal transmitted from the external device, the processing procedure is opposite to the transmission procedure of the second signal, as follows:
still referring to fig. 2, the analog front end is further configured to receive a first signal sent by the external device, where the analog front end is communicatively connected to an analog signal input end of the data conversion unit, and is configured to input the first signal into the data conversion unit for analog-to-digital conversion to obtain a digital first signal, a digital signal output end of the data conversion unit is communicatively connected to a second receiving end of the first FPGA processing unit, and is configured to transmit the digital first signal to the first FPGA processing unit for signal processing to obtain a processed first signal, and a second sending end of the first FPGA processing unit is communicatively connected to a second transmitting end of the first cable PCIE connector, and is configured to transmit the processed first signal to the high-speed bus adapter through the first cable PCIE connector; therefore, the first signal transmitted by the external equipment can be sent to the back-end processor, and the sending of the external signal is realized.
In this embodiment, referring to fig. 2, the data conversion unit includes an ADC converter and a DAC converter, so that it is combined with the analog front end for frequency conversion, amplification, conditioning, filtering, receiving and transmitting the analog signal, and converting between the analog signal and the digital signal, thereby satisfying the signal transmission requirement.
In this embodiment, for example, a PCIE bus interface in the first cable-type PCIE connector may be, but is not limited to, a PCIE Gen 3x4 bus interface, a PCIE Gen1 x4 bus interface, or a PCIE Gen 2x4 bus interface, where preferably, the PCIE Gen 3x4 bus interface is adopted, and the PCIE Gen 3x4 bus interface has a theoretical data throughput rate of 4GB/s and transmission delay as short as microsecond level, which may provide a sufficiently large transmission bandwidth and a sufficiently short transmission delay for most real-time signal processing applications, ensure continuity and timeliness of data transmission, and provide a basic condition for real-time signal processing; when the requirement on transmission performance is not high, a PCIE Gen1 x4 bus interface or a PCIE Gen 2x4 bus interface can be adopted.
Furthermore, in the present embodiment, it is preferable to use an SFF-8644 type (Mini-SAS HD 4 x) connector and a copper wire cable or an optical fiber cable, that is, the PCIE cable includes a PCIE copper wire cable or a PCIE optical fiber cable, where the SFF-8644 type connector supports cable-type PCIE Gen3 and Gen4 standards, and when the copper wire cable is used, the longest cable length may reach 10 meters, and when the optical fiber cable is used, the longest cable length may reach 100 meters, so that the short-distance and long-distance transmission requirements may be met.
In this embodiment, the PCIE Gen 3x4 bus interface represents a PCIE bus of a third generation and having 4 lanes, similarly, the PCIE Gen1 x4 bus interface represents a PCIE bus of a first generation and having 4 lanes, and the PCIE Gen 2x4 bus interface represents a PCIE bus of a second generation and having 4 lanes.
Furthermore, since the system can cascade the extended front-end signal transceivers, in order to ensure synchronous operation of each extended front-end signal transceiver when a plurality of extended front-end signal transceivers are connected, the front-end signal transceiver of the embodiment is further provided with a clock and trigger signal interface, a phase-locked loop control unit and a constant temperature crystal oscillator.
Referring to fig. 2, the clock and trigger signal interface is electrically connected to the phase-locked loop control unit, and is configured to send a received external clock signal to the phase-locked loop control unit, where the external clock signal may include, but is not limited to: the external sampling clock signal, the reference clock signal and/or the GPS pulse per second signal may be selected according to the number of specific signal frequencies, and the present invention is not limited to the foregoing examples.
Meanwhile, the oven controlled crystal oscillator is electrically connected with the phase-locked loop control unit, and is used for generating a time base signal and sending the time base signal to the phase-locked loop control unit, so that the phase-locked loop control unit can be used for generating a system clock signal according to the external clock signal and the time base signal, thereby enabling the front-end signal transceiver and the expanded front-end signal transceiver to synchronously run based on the system clock signal and ensuring the synchronous sending of the signals; specifically, the system clock signal is sent to the first FPGA processing unit, the digital conversion unit, and the analog front end of each front-end signal transceiver to implement synchronous operation of each front-end signal transceiver.
In addition, the clock and trigger signal interface is electrically connected to the first FPGA processing unit and configured to send the received trigger signal to the first FPGA processing unit, so that the first FPGA processing unit triggers an internal processing mechanism based on the trigger signal, thereby implementing signal preprocessing.
Of course, in this embodiment, as shown in fig. 2, the front-end signal transceiver is further connected to a DRAM (Dynamic Random Access Memory) and a FLASH chip through the FPGA chip, where the DRAM is used for local caching and temporary storage of high-speed signal data, and the FLASH chip is used for storing a firmware program, so as to implement signal processing and data caching of the first FPGA processing unit.
Therefore, through the detailed description of the front-end signal transceiver, the receiving and sending of signals, digital-to-analog conversion, analog-to-digital conversion, preprocessing and closed-loop control can be realized.
Next, referring to fig. 3, one specific structure of the high-speed bus adapter is provided as follows:
in this embodiment, for example, the high-speed bus adapter may include, but is not limited to: the lightning protection device comprises a second cable type PCIE connector, a two-way PCIE clock generator and a lightning controller, wherein a first transmission end of the second cable type PCIE connector is in communication connection with a first cable type PCIE connector of the front-end signal transceiver through a PCIE cable, a second transmission end of the second cable type PCIE connector is in communication connection with the lightning controller, the two-way PCIE clock generator is in communication connection with the second cable type PCIE connector and the lightning controller respectively, and the lightning controller is in communication connection with a main lightning interface so as to be in communication connection with the rear-end signal processor based on the main lightning interface; through the design, the integration and the conversion of the PCIE technology and the lightning interface technology can be realized based on the high-speed bus adapter, so that a data communication link which is arranged between one or more front-end signal transceivers and a rear-end signal processor and has the characteristics of high speed, low delay, long distance, distribution and hot plug is established; meanwhile, the thunder and lightning controller is matched with the two-way PCIE clock generator to be connected with the second cable type PCIE connector, the highest 32GB/s transmission speed can be achieved, the transmission delay can be as low as microsecond level, and therefore the requirement for high-speed data transmission can be met.
Alternatively, a specific circuit diagram of the second cable-type PCIE connector can be shown in fig. 9, and a specific circuit diagram of the two-way PCIE clock generator can be shown in fig. 11, which uses a Si52112-B6 type clock chip and a 25MHz clock source (i.e., Y3 in fig. 11) to generate the clock signal used by the data communication link; in this embodiment, a circuit diagram for connecting the main lightning interface of the back-end signal processor can be seen in fig. 28; in addition, the model of the lightning controller can adopt, but is not limited to, intel JHL8440, and specific circuit diagrams thereof can be seen in fig. 12-23.
Furthermore, the extension high-speed bus adapters are in communication connection with the lightning controllers through the cascade lightning interfaces, so that when a plurality of extension high-speed bus adapters exist, the next-stage extension high-speed bus adapter can be connected into the system based on the cascade lightning interfaces on each extension high-speed bus adapter, and accordingly cascade connection between the high-speed bus adapters and the plurality of extension high-speed bus adapters is achieved, expandability of the system is improved, and cascade extension requirements of the system are met; alternatively, a specific circuit diagram of the cascading lightning interface may be, but is not limited to, as shown in FIG. 10.
In addition, in a specific application, for example, the high-speed bus adapter may further include, but is not limited to: a first USB port controller, a second USB port multiplexer, and a third USB port controller, as shown in fig. 3, wherein the lightning cascading interfaces are further in communication connection with the first USB port controller and the second USB port multiplexer, respectively, wherein the first USB port controller and the second USB port multiplexer are further in communication connection with the lightning controller through an I2C bus, respectively, and the second USB port multiplexer is further in communication connection with the main lightning interface, and simultaneously, the main lightning interface is further in communication connection with the lightning controller through the third USB port controller, so as to implement USB communication with the lightning controller based on the third USB port controller.
In this embodiment, for example, the first USB port controller and the third USB port controller are USB3.1 port controllers (see fig. 24 for specific circuit diagrams), and the second USB port multiplexer is a USB2.0 port multiplexer (see fig. 25 for specific circuit diagrams), so that the lightning controller and the lightning cascade interface are connected through the USB2.0 port controller, so as to implement control connection of the lightning controller and cascade connection of the USB2.0 interface, and meanwhile, the lightning cascade interface of the high-speed bus adapter can implement USB communication of the high-speed bus adapter in cooperation with the first USB port controller, and the connection path of the second USB port multiplexer and the first USB port controller can be used for parameter configuration and data reading of each functional component in the high-speed bus adapter and the cascaded extended high-speed bus adapter; therefore, through the design, the high-speed bus adapter can support USB communication while supporting lightning interface technology communication.
Optionally, a first power circuit is further disposed in the high-speed bus adapter, where the first power circuit is electrically connected to the main lightning interface and is configured to supply power to the high-speed bus adapter based on the main lightning interface, and of course, the first power circuit is also electrically connected to a third USB port controller and supplies power to the third USB port controller, as shown in fig. 3 and 27.
Of course, in this embodiment, the function configuration program of the lightning controller is stored in the onboard BIOS FLASH (non-volatile memory), so that the high-speed bus adapter starts to operate by the loader when the power is turned on, and the high-speed data transmission function is realized, as shown in fig. 3, and meanwhile, the specific circuit of the non-volatile memory can be seen in fig. 26.
In this embodiment, for example, the main lightning interface and the cascade lightning interface may be, but are not limited to, a lightning 4 interface or a lightning 3 interface, and the second cable-type PCIE connector is identical in structure to the first cable-type PCIE connector, which is not described herein again.
Therefore, through the detailed transmission of the high-speed bus adapter, the high-speed bus adapter can support the hot plugging characteristic based on the internal lightning interface, and further the hot plugging performance of the whole equipment connected with the front-end signal transceiver is realized, so that the equipment can be switched in and started in the starting state of the rear-end signal processor, meanwhile, the expandable characteristic of the system can be realized through the arrangement of the cascade lightning interface, and the hot plugging distributed signal transceiving and processing system can be formed based on the hot plugging characteristic.
Finally, referring to fig. 4, one specific structure of the back-end signal processor is provided as follows:
in this embodiment, for example, the backend signal processor may include, but is not limited to: the intelligent lightning protection system comprises a central processing unit, an image processing unit, a second FPGA processing unit, a mainboard chip, a slave lightning controller and a slave lightning interface, wherein the central processing unit is respectively in communication connection with the image processing unit and the second FPGA processing unit, the central processing unit is used for carrying out complex application logic execution optimization and is responsible for overall control of the system, the image processing unit and the second FPGA processing unit are used for completing the cooperative processing operation of floating points and fixed points and are matched with the central processing unit to realize the calculation and processing of signals, and therefore, a rear-end signal processor can comprise three computing devices with different architectures, and therefore the intelligent lightning protection system has general and powerful processing capacity and meets the requirement for high-speed signal processing.
Meanwhile, referring to fig. 4, the central processing unit is further communicatively connected to the slave lightning controller through the motherboard chip, and the slave lightning controller is communicatively connected to the high-speed bus adapter through the slave lightning interface to receive the first signal sent by the high-speed bus adapter and send the second signal to the high-speed bus adapter.
Similarly, the second power circuit and the fourth USB port controller are also provided for the backend signal processor in this embodiment, as shown in fig. 4, where the second power circuit is electrically connected to the slave lightning interface and the fourth USB port controller respectively, and is configured to supply power to the backend signal processor through the slave lightning interface, and the slave lightning interface is further communicatively connected to the fourth USB port controller, and is configured to implement USB communication based on the fourth USB port controller.
Furthermore, the motherboard chip is further electrically connected to peripheral devices, such as an SSD (Solid State Disk or Solid State Drive) and other peripherals (such as a network port and a USB interface) so that a user performs human-computer interaction based on the peripheral devices, and meanwhile, the central processing unit and the image processing unit, and the central processing unit and the second FPGA processing unit are connected by PCIE buses to implement high-speed data exchange.
Of course, in this embodiment, the central processing unit, the graphics processing unit, and the second FPGA processing unit are all equipped with corresponding DRAM memories for temporarily storing operation and logic data, so as to implement calculation and processing of signals.
Therefore, through the above detailed description of the back-end signal processor, the high-speed data stream received from the front-end signal transceiver can be processed in real time, or the high-speed data stream required to be sent to the front-end signal transceiver via the high-speed bus adapter is calculated in real time, and the sending and receiving of the signal are completed.
In this embodiment, the structure of the extended high-speed bus adapter is the same as the structure of the high-speed bus adapter, and the structure of the extended front-end signal transceiver is the same as the structure of the front-end signal transceiver, which are not described herein again.
In a possible design, a second aspect of this embodiment provides a specific application structure of the distributed high-speed signal transceiving processing system according to the first aspect of the embodiment, and refer to fig. 5:
in the second aspect of this embodiment, only one front-end signal transceiver and one high-speed bus adapter are provided, where, for example, the high-speed bus adapter is connected to the back-end signal processor through the main lightning interface and the active lightning cable, the cable length is not more than 2 meters, the front-end signal transceiver and the high-speed bus adapter can be connected through a PCIE copper wire cable, the copper cable length is not more than 10 meters, and meanwhile, the front-end signal transceiver can receive an external clock signal and a trigger signal.
In a possible design, a third aspect of this embodiment provides another specific application structure of the distributed high-speed signal transceiving processing system in the first aspect of the embodiment, as shown in fig. 6:
compared with the second aspect of the embodiment, in the third aspect of the embodiment, the high-speed bus adapter may be connected to the next-stage extended high-speed bus adapter through the cascaded lightning interface, and the cascaded extension supports hot plug operation, as shown in fig. 5, meanwhile, the front-end signal transceiver and the corresponding high-speed bus adapter are also connected by a PCIE copper wire cable, and coherent synchronization signals may be transmitted and received between the plurality of front-end signal transceivers through an external clock signal and a trigger signal, so that the structure is suitable for quickly constructing a multi-channel coherent high-speed signal transmitting and receiving processing system.
In a possible design, a fourth aspect of this embodiment provides a third specific application structure of the distributed high-speed signal transceiving processing system in the first aspect, and as shown in fig. 7:
compared with the second aspect of the embodiment, the fourth aspect of the embodiment adopts the PICE optical fiber cable connection instead between the front-end signal transceiver and the high-speed bus adapter, so that the connection distance can reach 100 meters at the longest, and similarly, the front-end signal transceiver can receive the external clock signal and the trigger signal, therefore, the structure is suitable for quickly constructing the remote high-speed signal transceiving processing system.
In a possible design, a fifth aspect of the present implementation provides a fourth specific application structure of the distributed high-speed signal transceiving processing system in the first aspect, and refer to fig. 8:
compared with the second aspect of the embodiment, the front-end signal transceivers and the high-speed bus adapter are connected by PCIE optical fiber cables instead, the connection distance can reach 100 meters at the longest, the high-speed bus adapter can be connected with the next-stage expansion high-speed bus adapter through the cascade lightning interface of the high-speed bus adapter, the cascade expansion supports hot plug operation, and meanwhile, the front-end signal transceivers can perform coherent synchronization signal transceiving through high-precision distributed clock signals and trigger signals, so that the structure is suitable for constructing a remote distributed high-speed signal transceiving processing system.
Claims (10)
1. A distributed high-speed signal transceiving processing system, comprising: the system comprises a front-end signal transceiver, a high-speed bus adapter and a rear-end signal processor;
the high-speed bus adapter comprises a main lightning interface and a cascade lightning interface, wherein the front-end signal transceiver is in communication connection with the high-speed bus adapter through a PCIE cable and is used for transmitting a first signal sent by external equipment to the high-speed bus adapter or receiving a second signal sent by the high-speed bus adapter;
the high-speed bus adapter is in communication connection with the rear-end signal processor through the main lightning interface and is used for sending the first signal to the rear-end signal processor or receiving a second signal sent by the rear-end signal processor;
the high-speed bus adapter passes through cascade thunder and lightning interface communication connection extension high-speed bus adapter, wherein, extension high-speed bus adapter is through the next extension high-speed bus adapter of inside cascade thunder and lightning interface communication connection, in order to realize cascade connection between high-speed bus adapter and a plurality of extension high-speed bus adapters, just extension high-speed bus adapter is provided with extension PCIE cable interface, is used for passing through extension PCIE cable interface communication connection extension front end signal transceiver is in order to realize cascade connection between front end signal transceiver and a plurality of extension front end signal transceiver.
2. The distributed high-speed signal transceiving processing system of claim 1, wherein the front-end signal transceiver comprises: the system comprises a first cable type PCIE connector, a first FPGA processing unit, a data conversion unit and an analog front end;
the first transmission end of the first cable-type PCIE connector is in communication connection with the high-speed bus adapter through the PCIE cable and is used for receiving the second signal, and the second transmission end of the first cable-type PCIE connector is in communication connection with the first receiving end of the first FPGA processing unit and is used for inputting the second signal into the first FPGA processing unit for signal processing to obtain a processed second signal;
the first sending end of the first FPGA processing unit is in communication connection with the digital signal input end of the data conversion unit and is used for inputting the processed second signal to the data conversion unit for digital-to-analog conversion to obtain an analog second signal;
an analog signal output end of the data conversion unit is in communication connection with the analog front end and is used for transmitting the analog second signal to the external device through the analog front end;
the analog front end is further configured to receive a first signal sent by the external device, and the analog front end is communicatively connected to an analog signal input end of the data conversion unit and configured to input the first signal to the data conversion unit for analog-to-digital conversion to obtain a digital first signal;
the digital signal output end of the data conversion unit is in communication connection with the second receiving end of the first FPGA processing unit and is used for transmitting the digital first signal to the first FPGA processing unit for signal processing to obtain a processed first signal;
the second transmitting end of the first FPGA processing unit is in communication connection with the second transmitting end of the first cable-type PCIE connector, and is configured to transmit the processed first signal to the high-speed bus adapter through the first cable-type PCIE connector.
3. The distributed high-speed signal transceiving processing system of claim 2, wherein the front-end signal transceiver further comprises: a clock and trigger signal interface, a phase-locked loop control unit and an oven controlled crystal oscillator;
the clock and trigger signal interface is electrically connected with the phase-locked loop control unit and used for sending a received external clock signal to the phase-locked loop control unit, and the constant temperature crystal oscillator is electrically connected with the phase-locked loop control unit and used for generating a time base signal and sending the time base signal to the phase-locked loop control unit;
the phase-locked loop control unit is used for generating a system clock signal according to the external clock signal and the time-base signal so as to enable the front-end signal transceiver and the extended front-end signal transceiver to synchronously run based on the system clock signal;
the clock and trigger signal interface is also electrically connected with the first FPGA processing unit and used for sending the received trigger signal to the first FPGA processing unit so that the first FPGA processing unit triggers an internal processing mechanism based on the trigger signal.
4. The distributed high-speed signal transceiving processing system of claim 1, wherein the high-speed bus adapter further comprises: the lightning protection device comprises a second cable type PCIE connector, a two-way PCIE clock generator and a lightning controller;
a first transmission end of the second cable-type PCIE connector is in communication connection with the front-end signal transceiver through the PCIE cable, and a second transmission end of the second cable-type PCIE connector is in communication connection with the lightning controller, wherein the two-way PCIE clock generator is in communication connection with the second cable-type PCIE connector and the lightning controller respectively, and the lightning controller is in communication connection with a main lightning interface so as to be in communication connection with the rear-end signal processor based on the main lightning interface;
the extension high-speed bus adapter is in communication connection with the lightning controller through the cascading lightning interfaces, so that when a plurality of extension high-speed bus adapters exist, the high-speed bus adapters and the extension high-speed bus adapters are in cascading connection based on the cascading lightning interfaces on each extension high-speed bus adapter.
5. The distributed high-speed signal transceiving processing system of claim 4, wherein the high-speed bus adapter further comprises: a first USB port controller, a second USB port multiplexer, and a third USB port controller;
the cascade lightning interface is also respectively in communication connection with the first USB port controller and the second USB port multiplexer, wherein the first USB port controller and the second USB port multiplexer are respectively in communication connection with the lightning controller through an I2C bus, and the second USB port multiplexer is also in communication connection with the main lightning interface;
the main lightning interface is also in communication connection with the lightning controller through the third USB port controller, so that USB communication with the lightning controller is realized based on the third USB port controller.
6. The distributed high-speed signal transceiving processing system of claim 4, wherein the high-speed bus adapter further comprises: a first power circuit, wherein the first power circuit is electrically connected to the primary lightning interface for powering the high speed bus adapter based on the primary lightning interface.
7. The distributed high-speed signal transceiving processing system according to claim 1, wherein the back-end signal processor comprises: the lightning protection system comprises a central processing unit, an image processing unit, a second FPGA processing unit, a main board chip, a slave lightning controller and a slave lightning interface;
the central processing unit is respectively in communication connection with the image processing unit and the second FPGA processing unit, the central processing unit is also in communication connection with the slave lightning controller through the mainboard chip, and the slave lightning controller is in communication connection with the high-speed bus adapter through the slave lightning interface so as to receive a first signal sent by the high-speed bus adapter and send a second signal to the high-speed bus adapter.
8. The distributed high-speed signal transceiving processing system of claim 7, wherein the back-end signal processor further comprises: the second power circuit is respectively and electrically connected with the slave lightning interface and the fourth USB port controller and is used for supplying power to the rear-end signal processor through the slave lightning interface;
the slave lightning interface is also in communication connection with the fourth USB port controller and is used for realizing USB communication based on the fourth USB port controller.
9. The distributed high-speed signal transceiving processing system according to claim 7, wherein the motherboard chip is further electrically connected to a peripheral device, and PCIE buses are adopted for connection between the central processing unit and the image processing unit, and between the central processing unit and the second FPGA processing unit.
10. The distributed high-speed signal transceiving processing system according to claim 1, wherein the PCIE cable includes: and the extended PCIE cable interface comprises a PCIE Gen 3x4 bus interface, a PCIE Gen1 x4 bus interface or a PCIE Gen 2x4 bus interface.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211375496.1A CN115481063A (en) | 2022-11-04 | 2022-11-04 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310663750.6A CN116647247B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN202310666458.XA CN116841932B (en) | 2022-11-04 | 2023-06-06 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN202310662181.3A CN116680220B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system |
| CN202310666462.6A CN116680221B (en) | 2022-11-04 | 2023-06-06 | Distributed high-speed signal receiving and transmitting processing system |
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| CN202211375496.1A CN115481063A (en) | 2022-11-04 | 2022-11-04 | Distributed high-speed signal receiving and transmitting processing system |
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| CN202310662181.3A Active CN116680220B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system |
| CN202310666458.XA Active CN116841932B (en) | 2022-11-04 | 2023-06-06 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN202310666462.6A Active CN116680221B (en) | 2022-11-04 | 2023-06-06 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310663750.6A Active CN116647247B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
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| CN202310662181.3A Active CN116680220B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system |
| CN202310666458.XA Active CN116841932B (en) | 2022-11-04 | 2023-06-06 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN202310666462.6A Active CN116680221B (en) | 2022-11-04 | 2023-06-06 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310663750.6A Active CN116647247B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
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| CN116383107A (en) * | 2023-06-06 | 2023-07-04 | 成都立思方信息技术有限公司 | Flexibly-expandable signal receiving and transmitting system |
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| CN116955258B (en) * | 2023-09-19 | 2023-11-28 | 成都立思方信息技术有限公司 | Flexibly-connectable trigger connector, signal acquisition control equipment and system |
| CN117289236B (en) * | 2023-11-27 | 2024-02-09 | 成都立思方信息技术有限公司 | Short-time radar signal intra-pulse modulation type identification method, device, equipment and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116383107A (en) * | 2023-06-06 | 2023-07-04 | 成都立思方信息技术有限公司 | Flexibly-expandable signal receiving and transmitting system |
| CN116383107B (en) * | 2023-06-06 | 2023-08-22 | 成都立思方信息技术有限公司 | Flexibly-expandable signal receiving and transmitting system |
Also Published As
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| CN116680220A (en) | 2023-09-01 |
| CN116647247B (en) | 2024-01-26 |
| CN116680220B (en) | 2023-11-28 |
| CN116680221A (en) | 2023-09-01 |
| CN116841932B (en) | 2024-03-26 |
| CN116680221B (en) | 2024-03-26 |
| CN116647247A (en) | 2023-08-25 |
| CN116841932A (en) | 2023-10-03 |
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Application publication date: 20221216 |