CN212009563U - VPX bus dual-redundancy DBF processing module - Google Patents

Abstract

The utility model discloses a two redundant DBF processing module of VPX bus, including printing board, heat dissipation apron, panel, DBF processing unit, ethernet interface, reset button, LED signal lamp, high-speed high density electric connector and plug ware. The utility model belongs to the technical field of integrated circuit, specifically be a VPX bus DBF processing module based on autonomic core chip "HuaRui DBF chip" to on the basis of the dual-redundancy hot backup system, single module contains 2 groups of complete independent DBF processing unit, adopts multichannel parallel transmission and full flowing water parallel processing framework, with the DBF processing platform that founds high density, high reliability, universality developments reconfigurable, satisfies the application demand of radar integrated signal processing system. The module has the characteristics of strong operation processing capability, flexible parallel processing structure, dynamic reconfiguration, high reliability and the like, can be widely applied to digital beam forming in military and civil fields, and has strong universality and adaptability.

Description

VPX bus dual-redundancy DBF processing module

Technical Field

The utility model belongs to the technical field of integrated circuit, specifically indicate a two redundant DBF processing modules of VPX bus.

Background

With the rapid development of integrated circuit technology, application systems of modern radar systems are developed in the direction of giant arrays, multiple functions, multiple channels and large broadband, and Digital Beam Forming (DBF) systems are required to have technical characteristics of high integration level, high-speed data transmission, high reliability, dynamic reconfiguration and the like. The radar DBF processing system is in a modular design and comprises a plurality of DBF processing modules, each DBF processing module comprises a plurality of processing cores, and parallel transmission and full-flow parallel processing systems are formed by high-speed, low-delay and reliable optical fiber channels, so that the radar DBF processing function is realized; the DBF processing system is one of the core components of the radar, and the development level and the localization degree of the DBF processing system have great influence on the information safety of radar equipment. For a long time, a core device FPGA of a radar signal processing system in China always depends on import, the development of the radar technology in China is severely restricted, the national defense information safety is damaged, and the core technology is limited by people, the technical innovation capability is weak, and great potential safety hazards exist, so that the localization of the core device of the DBF processing system is imperative; the phased array radar array antenna has the advantages that the number of output channels of the phased array radar array antenna is large, the data rate is high, therefore, FPGA is mostly adopted to realize digital beam forming, but FPGA multiplier resources are insufficient, the data rate and the number of channels of array downlink in various radars and the number of beams needing to be synthesized are different, respective digital beam forming FPGA programs need to be repeatedly developed aiming at various radars frequently, manpower and material resources are consumed very much, the radar development period is prolonged, and the development difficulty is increased. Therefore, it is necessary to design a module based on a dynamic reconfigurable digital beam forming method with general applicability, so as to avoid repeated design of a digital beam former in various radars; digital beam forming is a data source for radar signal processing, but high-speed data transmission characteristics are easily affected by factors such as environment, and if downlink data of a certain optical fiber is wrong, potential safety hazards of target misjudgment can be brought to the whole system. Therefore, it is necessary to adopt dual redundant backup for fault-tolerant design to improve the reliability of beam forming.

SUMMERY OF THE UTILITY MODEL

To the above situation, for overcoming prior art's defect, the utility model provides a VPX bus dual-redundancy DBF processing module, a VPX bus DBF processing module based on autonomic core chip "Hua Rui DBF chip" to the basis of dual-redundancy hot backup system, single module contains 2 groups of complete independent DBF processing unit, adopt multichannel parallel transmission and full flowing water parallel processing framework, in order to found high density, high reliability, but the reconfigurable DBF processing platform of universality developments, satisfy radar integrated signal processing system's application demand. The module has the characteristics of strong operation processing capability, flexible parallel processing structure, dynamic reconfiguration, high reliability and the like, can be widely applied to digital beam forming in military and civil fields, and has strong universality and adaptability.

The utility model adopts the following technical scheme: the utility model relates to a VPX bus dual-redundancy DBF processing module, including printed circuit board, heat dissipation apron, panel, DBF processing unit, ethernet interface, reset button, LED signal lamp, high-speed high density electric connector and plug ware, DBF processing unit locates on the printed circuit board, the heat dissipation apron links to each other with the printed circuit board, the ethernet interface locates on the printed circuit board, reset button locates on the printed circuit board, the LED signal lamp locates on the printed circuit board, high-speed high density electric connector locates on the printed circuit board, the panel lock locates on the printed circuit board, heat dissipation apron and panel link to each other through the plug ware; the DBF processing unit comprises a power supply, a Huari DBF chip, a storage flash chip, an OBC FPGA chip, a network switching chip and an independent clock module, wherein the power supply is arranged on a printed board, the Huari DBF chip is arranged on the printed board, the storage flash chip is arranged on the printed board, the network switching chip is arranged on the printed board, the independent clock module is arranged on the printed board, the DBF processing unit is provided with two groups of main DBF processing units and standby DBF processing units, the main DBF processing units and the standby DBF processing units have the same functions, and the maximum working main frequency of 500MHz is supported; each Chinese Rui DBF chip is externally hung with 1 storage flash chip for storing Chinese Rui DBF chip MCU configuration files, global parameters, static parameters and the like; the OBC FPGA chip realizes the functions of module control management and high-speed data exchange.

Further, the power supply comprises 12 power supply modules, the input voltages of the power supply are +12V _ a, +12V _ B, respectively, and the output voltages of the power supply are: 3.3V, 2.5V, 1.8V, 1.5V, 1.4V, 1.2V, 1.0V, 0.9V, 1.8VA, 0.9VA, 1.2VA, 1.0 VA; take the main DBF processing unit as an example: a DC-DC power supply module generates the core voltage of a core DBF chip of 0.9V; a DC-DC power supply module generates the core voltage of the OBC FPGA chip to be 1.0V, and DDR and the like to supply power to be 1.5V; a DC-DC power supply module generates 2.5V, 3.3V and 1.8V; the nine LDO power supply modules generate OBC FPGA chip high-speed ports 1.0VA and 1.2VA power supplies, Chinese DBF chip high-speed ports 0.9VA and 1.8VA power supplies, network exchange 1.2V power supplies, PHY chip 1.4V power supplies and DDR 0.75V power supplies.

Further, the Chinese Rui DBF chip is a processing core of digital beam forming and works to support the main frequency of 500MHz at maximum.

Furthermore, the Chinese Rui DBF chip provides 72 routes of main channel Serdes RX interfaces for digital beam forming data input, and is directly connected with the high-speed high-density electric connector; and the 6 paths of auxiliary channel Serdes TX interfaces are used for outputting auxiliary channel test data, the auxiliary channel data are output to the high-speed high-density electric connector after passing through the OBC FPGA chip 12, and the main DBF processing unit and the standby DBF processing unit are completely independent.

Furthermore, the network switching chip is connected with the SGMII interface of the Borui DBF chip, the SGMII interface which is connected out from the high-speed high-density electric connector, and the SGMII interface and the Ethernet interface which are converted from the RGMII channel of the OBC FPGA chip.

Further, the OBC FPGA chip realizes board-level control management and monitoring and provides an I2C interface for a system monitoring function.

Further, the flash memory chip is used for storing MCU configuration files and system parameters of the DBF chip.

Further, the high-speed high-density electrical connector comprises P0-P6, P0 provides a module main DBF processing unit and a standby DBF processing unit +12V input power supply, two monitoring I2C interfaces, a chassis number and a SYS _ RST # signal, P1-P6 are all differential connectors, P1 provides 6 auxiliary RockIO outputs of the main DBF processing unit and the standby DBF processing unit and 6 digital wave beam forming RockIO outputs of the main DBF processing unit and the standby DBF processing unit, P2 provides 28 RockIO inputs of the standby DBF processing unit, 1 SGMII interface of the main DBF processing unit and the standby DBF processing unit, P3 provides 32 RockIO inputs of the standby DBF processing unit, P4 provides 12 RockIO inputs of the standby DBF processing unit, 8 RockIO inputs of the main DBF processing unit, 6 RockIO outputs of the main DBF processing unit and the standby DBF processing unit, and RockIO outputs of the DBF processing unit, and RockIO outputs of the RockIO 4 input of the RockIO outputs of the main DBF processing unit, and the RockIO outputs of the DBF processing unit, and the RockIO outputs of the RockIO output of, The main DBF processing unit and the standby DBF processing unit are respectively 4-bit bidirectional GPIOs, and the P6 provides 32-channel RocktIO input, a case ID and a power supply enabling signal of the main DBF processing unit.

Further, the independent clock module comprises a crystal oscillator and a clock driver, the crystal oscillator and the clock driver are arranged on the printed board, the clock power supply is completely independent, and the designed clock signal comprises: 120MHz of serdes link reference clock of Borui DBF chip, 33.33MHz of logic part reference clock, 120MHz of serdes reference clock of OBC FPGA chip, 125MHz of SGMII reference clock of OBC FPGA chip and Borui DBF chip, 25MHz of network exchange chip reference clock, and 50MHz of PS part reference clock of OBC FPGA chip.

Adopt above-mentioned structure the utility model discloses the beneficial effect who gains as follows: according to the VPX bus dual-redundancy DBF processing module, a Huari DBF chip is adopted to replace an imported FPGA to realize digital beam forming, the influence of factors such as insufficient FPGA multiplier resources, repeated design of different application logics, forbidden operation risks and the like is avoided, and the module adopts a multi-channel parallel transmission and full-flow parallel processing architecture and has strong digital beam capacity; two groups of main and standby completely independent digital beam forming units complete error-tolerant designs such as power supply, clock, high-speed data link, beam forming and the like, thereby greatly improving the reliability and safety of the module; the OBC FPGA design realizes the control and management functions of a module system, simultaneously supports the data monitoring of 1-path monitoring, 1-path extraction, 4-path balanced Serdes and other auxiliary data interfaces, and has the BIT collection and transmission functions; the module interface conforms to the vita65 standard and has stronger universality and expansibility; the chip is independently controllable, supports super-large-scale parallel flow computation, dynamically reconfigurable simplified logic repeated design and redundant backup high reliability, and meets the application requirements of a new generation of high-performance digital beam forming system.

Drawings

FIG. 1 is a block diagram of a VPX bus dual redundant DBF processing module of the present invention;

fig. 2 is a schematic structural diagram of a heat dissipation cover plate of the VPX bus dual-redundancy DBF processing module of the present invention.

The LED lamp comprises a printed circuit board 1, a heat dissipation cover plate 2, a panel 3, a DBF processing unit 4, an Ethernet interface 5, an Ethernet interface 6, a reset button 7, an LED signal lamp 8, a high-speed high-density electric connector 9, a power supply 10, a Huari DBF chip 11, a storage flash chip 12, an OBC FPGA chip 13, a network switching chip 14, an independent clock module 15, a main DBF processing unit 16 and a standby DBF processing unit.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments; based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1-2, the utility model discloses two redundant DBF processing modules of VPX bus, including printed board 1, heat dissipation apron 2, panel 3, DBF processing unit 4, ethernet interface 5, reset button 6, LED signal lamp 7, high-speed high density electric connector 8 and plug, DBF processing unit 4 locates on printed board 1, heat dissipation apron 2 links to each other with printed board 1, ethernet interface 5 locates on printed board 1, reset button 6 locates on printed board 1, LED signal lamp 7 locates on printed board 1, high-speed high density electric connector 8 locates on printed board 1, panel 3 lock locates on printed board 1, heat dissipation apron 2 and panel 3 link to each other through the plug; the DBF processing unit 4 comprises a power supply 9, a Chinese DBF chip 10, a storage flash chip 11, an OBC FPGA chip 12, a network switching chip 13 and an independent clock module 14, the power supply 9 is arranged on the printed board 1, the Chinese DBF chip 10 is arranged on the printed board 1, the storage flash chip 11 is arranged on the printed board 1, the network switching chip 13 is arranged on the printed board 1, the independent clock module 14 is arranged on the printed board 1, the DBF processing unit 4 is provided with two groups of main DBF processing units 15 and standby DBF processing units 16, the main DBF processing units 15 and the standby DBF processing units 16 have the same functions and support the maximum working main frequency of 500 MHz; each Chinese Rui DBF chip 10 is externally hung with 1 storage flash chip 11 for storing Chinese Rui DBF chip 10MCU configuration files, global parameters, static parameters and the like; the OBC FPGA chip 12 realizes the functions of module control management and high-speed data exchange.

The power supply 9 comprises 12 power supply modules, the input voltage of the power supply 9 is +12V _ a, +12V _ B, and the output voltage of the power supply 9 is: 3.3V, 2.5V, 1.8V, 1.5V, 1.4V, 1.2V, 1.0V, 0.9V, 1.8VA, 0.9VA, 1.2VA, 1.0 VA; taking the main DBF processing unit 15 as an example: a DC-DC power supply module generates core voltage 0.9V of the core DBF chip 10; a DC-DC power supply module generates the core voltage 1.0V of the OBC FPGA chip 12 and supplies power 1.5V for DDR and the like; a DC-DC power supply module generates 2.5V, 3.3V and 1.8V; the nine LDO power supply modules generate OBC FPGA chip 12 high-speed ports 1.0VA and 1.2VA power supplies, Chinese DBF chip 10 high-speed ports 0.9VA and 1.8VA power supplies, network switching 1.2V power supplies, PHY chip 1.4V power supplies and DDR 0.75V power supplies.

The Borui DBF chip 10 is a processing core of digital beam forming and works to support the main frequency of 500MHz at most.

The Borui DBF chip 10 provides 72 main channel Serdes RX interfaces for digital beam forming data input, and is directly connected with the high-speed high-density electric connector; and the 6 paths of auxiliary channel Serdes TX interfaces are used for outputting auxiliary channel test data, and the auxiliary channel data are output to the high-speed high-density electric connector after passing through the OBC FPGA chip 12.

The network switch chip 13 is connected to the SGMII interface of the chinese-Rui DBF chip 10, the SGMII interface behind the high-speed high-density electrical connector, the SGMII interface converted from the RGMII channel of the OBC FPGA chip 12, and the Ethernet interface 5.

The OBC FPGA chip 12 realizes board-level control management and monitoring and provides an I2C interface for system monitoring function.

The flash memory chip 11 is used for storing MCU configuration files and system parameters of the DBF chip.

The high-speed high-density electric connector 8 comprises P0-P6, wherein P0 provides a module main DBF processing unit 15 and a standby DBF processing unit 16+12V input power supply, two monitoring I2C interfaces, a chassis number and a SYS _ RST # signal, P1-P6 are all differential connectors, P1 provides 6 auxiliary RockIO outputs of the main DBF processing unit 15 and the standby DBF processing unit 16 and 6 digital beam forming RockIO outputs of the main DBF processing unit 15 and the standby DBF processing unit 16, P2 provides 28 RockIO inputs of the standby DBF processing unit 16, 1 SGMII interface of the main DBF processing unit 15 and the standby DBF processing unit 16, P3 provides 32 RockIO inputs of the standby DBF processing unit 16, P4 provides 12 RockIO inputs of the standby DBF processing unit 16, 8 RockF inputs of the main DBF processing unit 15, 6 RockIO outputs of the standby DBF processing unit 15 and RockIO output of the standby DBF processing unit 16, the P5 provides 32-way rockio input of the main DBF processing unit 15, 4-bit bidirectional GPIOs of the main DBF processing unit 15 and the backup DBF processing unit 16, and the P6 provides 32-way rockio input of the main DBF processing unit 15, a chassis ID and a power enable signal.

The independent clock module 14 includes a crystal oscillator and a clock driver, the crystal oscillator and the clock driver are disposed on the printed board 1, the clock supply is completely independent, and the designed clock signal includes: 120MHz of a Borui DBF chip 10serdes link reference clock, 33.33MHz of a logic part reference clock, 120MHz of a serdes reference clock of an OBC FPGA chip 12, 125MHz of SGMII reference clocks of the OBC FPGA chip 12 and the Borui DBF chip 10, 25MHz of a network switching chip 13 reference clock, and 50MHz of a PS part reference clock of the OBC FPGA chip 12.

When the module is used specifically, the power supply of the module is +12V _ a and +12V _ B, which correspond to the input voltages of the main DBF processing unit 15 and the standby DBF processing unit 16, respectively, and the output voltages of the power supply modules of the main DBF processing unit 15 and the standby DBF processing unit 16 are respectively: 3.3V, 2.5V, 1.8V, 1.5V, 1.4V, 1.2V, 1.0V, 0.9V, 1.8VA, 0.9VA, 1.2VA, 1.0VA, produced by 3 DC-DC power supply modules and 9 LDO module designs, 0.9V is the core voltage of Huari DBF chip 10, and two paths of HCE4630ML are output in parallel; 1.0V is the core voltage of the OBC FPGA chip 12, 1.5V is the DDR interface voltage of the OBC FPGA chip 12 and the input of part of LDO power supply, and one HCE4630ML outputs; 1.8V is the input of the 1.8V IO BANK voltage, part of the interface circuit voltage and part of the LDO power of the Borui DBF chip 10 and the OBC FPGA chip 12, two of a piece of HCE4644MB are output in parallel, 2.5V is the IO voltage of PHY, the network switching voltage, the 2.5V IO BANK voltage of the OBC FPGA and the input of part of the LDO power, one of the output of a piece of HCE4644MB, 3.3V is the 3.3V IO BANK voltage and part of the interface circuit voltage of the OBC FPGA, and one of the output of a piece of HCE4644 MB; the high-speed serial port power supply 1.8V of the Borui DBF chip 10 is generated by two sheets of SM74401 RGWT; the high-speed serial port power supply 1.0V of the Borui DBF chip 10 is generated by two sheets of SM74401 RGWT; the high-speed serial port power supply 1.2V of the OBC FPGA chip 12 is generated by an SM74401 RGWT; the high-speed serial port power supply 1.0V of the OBC FPGA chip 12 is generated by an SM74401 RGWT; the 1.2V power supply of the network switching chip 13 is generated by a SM74401 RGWT; the power supply 1.4V of the PHY chip is generated by an SM74401 RGWT; the DDR power supply of 0.75V is generated by an SM51200 DRCR; each power supply in the board adopts an integrated design scheme, the DC/DC and LDO power supply modules generate required power supply varieties, output filtering and power supply plane design are optimized, continuous and stable power supply of each chip is provided, and stable and reliable work of the modules is facilitated; p0 provides input power of +12V for the main DBF processing unit 15 and the standby DBF processing unit 16, the main DBF processing unit 15 and the standby DBF processing unit 16 monitor I2C interfaces, chassis numbers and SYS _ RST # signals, P1-P6 are all differential connectors, P1 provides 6 auxiliary RockIO outputs of the main DBF processing unit 15 and the standby DBF processing unit 16 and 6 digital beam forming RockIO outputs of the main DBF processing unit 15 and the standby DBF processing unit 16, P2 provides 28 RockIO inputs of the standby DBF processing unit 16, 1 SGMII interfaces of the main DBF processing unit 15 and the standby DBF processing unit 16, P3 provides 32 RockIO inputs of the standby DBF processing unit 16, P4 provides 12 RockIO inputs of the standby DBF processing unit 16, 8 RockTIO inputs of the main DBF processing unit 15, 6 RockTRST processing units 15 and 6 digital beam forming RockIO outputs of the main DBF processing unit 16, and RockTIO outputs of the standby DBF processing unit 16 and RocketIO outputs of the RocketIO processing unit 5 provide 12 RockTIO inputs of the standby DBF processing unit 16, and RockTIO outputs of the main DBF processing unit 16, and the RockTQ processing unit 16 and the RocktIO outputs of the backup, The main DBF processing unit 15 and the standby DBF processing unit 16 are respectively 4-bit bidirectional GPIOs, P6 provides 32-channel RockIO input, chassis ID and power enable signals of the main DBF processing unit 15, system debugging is carried out through the Ethernet interface 5, a reset button and the LED signal lamp 7, and the Huari DBF chip 10 supports the maximum working main frequency of 500 MHz; each Chinese Rui DBF chip 10 is externally hung with 1 storage flash chip 11 for storing Chinese Rui DBF chip 10MCU configuration files, global parameters, static parameters and the like; two OBC FPGA chips 12 realize module control management, high-speed data exchange function, and main DBF processing unit 15 and the DBF processing unit 16 that is equipped with are constituteed by the crystal oscillator and the clock driver of each unit, and the clock power supply is completely independent, and the clock signal of design includes: 120MHz of a Borui DBF chip 10serdes link reference clock, 33.33MHz of a logic part reference clock, 120MHz of a serdes reference clock of an OBC FPGA chip 12, 125MHz of SGMII reference clocks of the OBC FPGA chip 12 and the Borui DBF chip 10, 25MHz of a network switching chip 13 reference clock, and 50MHz of a OBC FPGA chip 12PS part reference clock; after receiving 72 routes of Serdes front-end antenna array data, each of the main DBF processing unit 15 and the standby DBF processing unit 16 respectively carries out DBF processing such as parallel-serial conversion, weighted calculation, time-sharing accumulation synthesis, splitting output and the like, outputs 12 routes of Serdes data to a VPX connector, and converts the Serdes data into optical signals through a rear interface board and outputs the optical signals to the next stage; meanwhile, the main DBF processing unit 15 and the backup DBF processing unit 16 respectively output 1 path of monitoring Serdes (ASST0), 4 paths of balancing Serdes (ASST1) and 1 path of extracting Serdes (ASST2) to the OBC FPGA chips 12 of the main DBF processing unit 15 and the backup DBF processing unit 16 respectively corresponding to the paths, and the OBC FPGA chips 12 provide 6 paths of auxiliary interfaces to output to the VPX connector. The two Borui DBF chips 10 and the two OBC FPGA chips 12 on the module are designed completely the same, the Borui DBF chip 10 program design comprises a plurality of independent sub-modules such as MCU startup program, static parameter configuration, RAM parameter configuration, additional parameter configuration, description table, M value, N value, frequency point, sine line, phase correction, amplitude correction and amplitude weight, the FPGA design comprises a plurality of independent sub-modules such as Borui DBF chip 10 configuration module, BIT module and auxiliary Serdes module, the main DBF processing unit 15 and the auxiliary DBF processing unit 16 have respective network switching systems, the network switching function realizes flexible data exchange among all communication interfaces, the network interface of the internal processor, the network interface of the OBC FPGA chip 12 and the external network interface of the module are all connected with the network switching chip 13 to realize network data exchange, the typical power consumption of a single module design is less than 80W, and the devices on the printed board 1 are densely arranged, adopt the forced air cooling radiating mode to dispel the heat to the module and consolidate, heat dissipation apron 2 is hugged closely to the high-power consumption device, and the during operation is with heat transfer to heat dissipation apron 2 on for the high-power consumption device can not surpass the festival temperature and lead to damaging in the module, above just the utility model discloses holistic work flow, repeat this step when using next time can.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

The present invention and the embodiments thereof have been described above, but the description is not limited thereto, and the embodiment shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should understand that they should not be limited to the embodiments described above, and that they can design the similar structure and embodiments without departing from the spirit of the invention.

Claims (8)

1. A VPX bus dual redundant DBF processing module, characterized in that: the LED signal lamp comprises a printed board, a heat dissipation cover plate, a panel, a DBF processing unit, an Ethernet interface, a reset button, an LED signal lamp, a high-speed high-density electric connector and a plug-in device, wherein the DBF processing unit is arranged on the printed board; DBF processing unit includes power, huari DBF chip, storage flash chip, OBC FPGA chip, network switching chip and independent clock module, the power is located on the printing board, huari DBF chip is located on the printing board, storage flash chip is located on the printing board, the network switching chip is located on the printing board, independent clock module is located on the printing board, DBF processing unit is equipped with two sets ofly respectively for main DBF processing unit and be equipped with DBF processing unit.

2. The VPX bus dual redundant DBF processing module of claim 1, wherein: the power supply comprises 12 power supply modules, the input voltage of the power supply is +12V _ A, +12V _ B respectively, and the output voltage of the power supply is: 3.3V, 2.5V, 1.8V, 1.5V, 1.4V, 1.2V, 1.0V, 0.9V, 1.8VA, 0.9VA, 1.2VA, 1.0 VA.

3. The VPX bus dual redundant DBF processing module of claim 2, wherein: the Borui DBF chip is a processing core of digital beam forming.

4. A VPX bus dual redundant DBF processing module according to claim 3, characterized in that: the Borui DBF chip externally provides 72 paths of main channel Serdes RX interfaces; a 12-way main channel Serdes TX interface is provided, as well as a 6-way auxiliary channel Serdes TX interface.

5. The VPX bus dual redundant DBF processing module of claim 4, wherein: the network switching chip is connected with an SGMII interface of a Borui DBF chip, an SGMII interface which is arranged behind the high-speed high-density electric connector, an SGMII interface which is converted from an RGMII channel of the OBC FPGA chip and an Ethernet interface.

6. The VPX bus dual redundant DBF processing module of claim 5, wherein: the OBC FPGA chip realizes board-level control management and monitoring and provides an I2C interface for a system monitoring function.

7. The VPX bus dual redundant DBF processing module of claim 6, wherein: the high-speed high-density electric connector comprises P0-P6, P0 provides a main DBF processing unit and a standby DBF processing unit +12V input power supply, two monitoring I2C interfaces, a cabinet number and SYS _ RST # signals, P1-P6 are all differential connectors, P1 provides 6 auxiliary RockIO outputs of the main DBF processing unit and the standby DBF processing unit and 6 digital beam forming RockIO outputs of the main DBF processing unit and the standby DBF processing unit, P2 provides 28 RockIO inputs of the standby DBF processing unit, 1 SGMII interfaces of the main DBF processing unit and the standby DBF processing unit, P3 provides 32 RockIO inputs of the standby DBF processing unit, P4 provides 12 RockIO inputs of the standby DBF processing unit, 8 RockIO inputs of the main DBF processing unit, 6 RockIO inputs of the main DBF processing unit and the standby DBF processing unit, and a bidirectional digital beam forming GPIO output of the main DBF processing unit and DBF 5, and the bidirectional DBF processing unit provide bidirectional digital beam forming RockIO inputs of the 12 and DBF processing unit, p6 provides the 32-way RocketIO input, chassis ID, and power enable signal for the master DBF processing unit.

8. The VPX bus dual redundant DBF processing module of claim 7, wherein: the independent clock module comprises a crystal oscillator and a clock driver, and the crystal oscillator and the clock driver are arranged on the printed board.

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