CN2791752Y - High-speed data storage apparatus - Google Patents

Abstract

The utility model relates to a high-speed data storage apparatus which is characterized in that a circuit is composed of a data input /output module, a data partition /coalition module, a data check module and a hard disc interface module, wherein the data input /output module comprises a PCI/PCI bus controller and control logic, a large capacity FIFO and a data block buffer area; the data partition /coalition module comprises data partition logic, data coalition logic, a group of N small data block buffer areas, a data buffering management and a relational control circuit; the data check module comprises XOR logic, a check block buffer area and a relational control circuit; the hard disc interface module comprises a high-speed data interface and an SCSI interface controller. The scheme carries out distributed parallel processing for the data to be stored, and supports an over 400MB/s sustaining data storage and reading rate, supports the data collecting and playback cards of various PCI and PCI buses, and causes the real-time data storage and playback applied by high end data collection to be possible.

Description

The high-speed data memory device

Technical field

The utility model relates to the data acquisition field of storage, the especially application of high speed, the storage of high-resolution signal real-time data acquisition, and particularly the high speed to image data continues memory technology.

Background technology

Lasting high speed storing technology for image data is a data collecting field, especially the high-speed data acquisition area research important topic.Along with the continuous development of data acquisition in the every field application, such as, software radio, radar and laser radar data record, sonar data record, remotely-sensed data record, seismic data recording, high-energy physics test figure record etc., the sampling rate of data acquisition and acquisition precision are all improving constantly, the real-time storage technology of tackling image data is mutually had higher requirement, and (as sampling rate is 200MS/s, acquisition precision is the acquisition system of 14Bit, will produce the data of 400MB/s).

Under present technical conditions, still can not carry out real-time storage to the data that high-speed data acquisition produces, general memory device is only supported the lasting storage speed of 100MB/s.At the preservation of high speed acquisition data, the alternative solution that goes out is slowly gone in general employing soon, and the data cache that is about to gather after collection is finished, is derived data in buffer low speed to store for analyzing from now on again and used in the sampling point buffer memory of capture card.But the major limitation that this solution exists is: can only store the data in several seconds the short time, can not adapt to the long-time needs of acquired data storage in real time.In the world, Canadian ICS company claims and can produce the high-speed data memory device of supporting 400MB/s to continue storage speed, but can only reach 300MB/s through surveying its speed, and do not support the data fault tolerance.Obviously, for now, the high-speed data memory device that can support 400MB/s to continue storage speed remains a difficult problem technically.

Summary of the invention

The purpose of this utility model is in order to overcome the weak point of prior art, a kind of high-speed data storage solution is proposed, design and be adapted to the real-time data storage facilities that various high-end data acquisitions are used, carrying out distributed parallel for the data that will store handles, support to surpass duration data storage and the reading rate of 400MB/s, the real-time data memory and the playback that make high-end data acquisition use become possibility.

For achieving the above object, the technical solution adopted in the utility model is: a kind of high-speed data memory device, and its circuit is made up of data input, data partition/merging module, data check module, hard-disk interface module four parts;

Described data input comprises PCI/cPCI bus controller and steering logic, high capacity FIFO and data block buffer, wherein, PCI/cPCI bus controller and steering logic realize that with the PCI/cPCI bus data interaction is connected, and steering logic realizes control to the PCI/cPCI bus controller; The FIFO of PCI/cPCI bus controller, high capacity FIFO and data block buffer constitute a multistage data buffering successively, steering logic according to the almost empty of FIFO and almost full scale ambition FIFO write or from the FIFO reading of data; Data block buffer is made of jumbo DDR SDRAM and control circuit thereof;

Described data partition/merging module comprises data partition logic, data merge logic, one group of N small data block buffer, data buffering management and relevant control circuit, above-mentioned data block buffer is realized being connected by high-speed data path with N small data block buffer, and links up through data partition logic and data merging logic;

Described data check module comprises xor logic, check block buffer zone and relevant control circuit, the data check module is carried out the XOR computing by xor logic to the partition data through N small data block buffer, form corresponding checking data piece, deposit the check block buffer zone in; The pooled data that reads from hard-disk system is carried out the xor logic computing, the result is compared with the checking data that reads from check disk, realize the data fault-tolerant function of system;

Described hard-disk interface module comprises high speed interface and scsi interface controller, and high speed interface adopts the high-speed serial bus interface of multi-channel parallel work, and each scsi interface controller is controlled No. one hard disk, realizes the parallel data visit of disk array.

The utility model principle of work is: described data input realizes carrying out exchanges data with external unit, realizes the high speed input and output of data by the PCI/cPCI bus; Described data partition/merging module realizes the partition and the merging of data, the data partition is that the data block that data input module is imported is split into the plurality of data piece, be written in parallel to hard disk by the hard-disk interface module, data merging module reads the hard-disk interface module from hard disk data block is merged into a complete data block, sends by data outputting module; Described data check module realizes the verifying function of data, the data check module is carried out data check with each data block of data partition/merging module partition by the hardware check logic, forms the checking data piece, write check disk by the hard-disk interface module, realize the data fault-tolerant function of system; Described hard-disk interface module realizes the interface function with the SCSI hard disk, by the high speed access of scsi interface agreement realization to hard disc data.

The advantage that the utility model compared with prior art has: can real time high-speed ground be stored and playback with file mode by image data, support the data acquisition and the playback card of various PCI and cPCI bus.The utility model can be achieved as follows the key technical indexes:

1, bus type: PCI/cPCI

2, data recording rate: 400MB/s

3, data readback speed: 400MB/s

4, memory capacity: 1.4TB～9.6TB

5, RAID rank: RAID 0,1,5

The utility model can be used for following field:

1, radar and laser radar data registering instrument

2, sonar data registering instrument

3, remotely-sensed data registering instrument

4, seismic data recorder

5, high-energy physics test figure registering instrument

Description of drawings

Fig. 1 is the utility model hardware structure diagram;

Fig. 2 is the connection block diagram of the utility model high-speed data memory device in data acquisition is used.

Embodiment

Below in conjunction with drawings and Examples the utility model is further described:

Embodiment: a kind of high-speed data memory device is made up of data input I, data partition/merging module ii, data check module ii I, hard-disk interface module I V four parts, as shown in Figure 1.

The composition and the function declaration of each module are as follows:

I, data input comprise pci bus controller and steering logic, high capacity FIFO and data block buffer, wherein:

1) pci bus controller and steering logic

Pci bus controller and steering logic realize the data interaction with pci bus, consider the bandwidth requirement of high-speed data storage, adopt the pci bus controller of 64 133M, realize the peak value transfer rate of 1GB/s.The PCI steering logic realizes the control to pci bus controller, realizes register access on the plate, functions such as high-speed data path and interrupt management.Pci bus controller carries out the two-way visit of chunk data by dma operation and system.

2) high capacity FIFO

In order to prevent in the high speed data transfer process that continues because the temporary bottleneck of system causes overflowing of data, be provided with jumbo two-way FIFO, constitute a multistage data buffering with the FIFO and the data block buffering of pci bus controller, effectively avoid overflowing of data, guaranteed the continuity of data.Steering logic according to the almost empty of FIFO and almost full scale ambition FIFO write or from the FIFO reading of data.

3) data block buffer

Data block buffering storage need be written to the data block of hard-disk system, perhaps reads from each disk, through the data block after merging.Data block buffer realized by jumbo DDR SDRAM and control circuit thereof, compares with traditional SRAM, and it is fast that DDR SDRAM has access speed, the advantage that cost performance is high, but control is than the SRAM complexity.We adopt the DDR SDRMController IP kernel of Altera to carry out the data block buffering design, on original IP kernel basis, done big change, it is low to have improved its access speed, control unsettled defective, improved the performance of access memory, realized DDR SDRAM is carried out high speed alternately read-write and dynamic refresh.

II, data partition/merging module comprise data partition logic, data merging logic, one group of 1～N small data block buffer, data buffering management and relevant control circuit.Wherein:

1) data partition logic

The partition of data partition logic realization chunk data, the chunk data that module I is read by bus, on average split into some little data blocks (the hard disk quantity according to the actual connection of system is decided), be deposited into corresponding 1～N data block buffer respectively, by the scsi interface module data parallel write in the corresponding disk block again.

2) data merge logic

Data merge logic realization plurality of small blocks data and are merged into chunk data, are the inverse process of data partition logic, will be merged into a big data block from the parallel data block that reads of hard disk, by module I data are sent through system bus again.

3) data buffering management

The data buffering management realizes the management of chunk data buffering and fritter data buffering, realize being connected of chunk data buffering and fritter data buffering by high-speed data path, adopt hardware control logic to realize that the immediate data between the DDR SDRAM copies, reduce the number of times that data are landed, thereby improve the efficient of internal storage access.

III, data check module

The data check module comprises xor logic, check block buffer zone and relevant control circuit, realize the verifying function of data, by each data block is carried out data check, form the checking data piece, write check disk, realize the data redundancy function, when certain hard disk causes loss of data owing to physical damage, can carry out the recovery of data by checking data.

The data check module realizes by hardware xor logic and relevant control circuit, the hardware xor logic is to carrying out the XOR computing through the data block of module ii partition, form corresponding checking data piece, deposit the check block buffer zone in, write in the check disk by the scsi interface module again.

From hard disk reading of data process, the data check module is carried out the xor logic computing to each data block that reads from hard-disk system, the result is compared with the checking data that reads from check disk, to guarantee the correctness and the integrality of data read.

IV, hard-disk interface module comprise high speed interface and scsi interface controller, wherein:

1) high speed interface

High speed interface is the high-speed data channel between data buffering and the scsi interface, because system need reach the data storage speed above 400MB/s, improve reliability in order to reduce the connection scale simultaneously, we adopt the high-speed serial bus interface, select the TLK4015 of TI company for use, 4 channel transceiver, 4 channel parallel work, this interface rate reaches 4.8Gb/s.

2) scsi interface controller

The scsi interface controller is realized the visit of SCSI hard disc data, SCSI bus can articulate a plurality of hard disc apparatus, conduct interviews by serial mode between each hard disc apparatus, if adopt a SCSI bus to articulate the connected mode of a plurality of hard disc apparatus, then can not really realize the parallel data visit of disk array, thereby can not satisfy call data storage at a high speed.

Therefore, we adopt a scsi interface controller to control the mode of No. one hard disk, realize the parallel data visit of a plurality of hard disks, realize the data storage speed of 400MB/s, if adopt No. 8 hard disks to work simultaneously, every road hard disk will be realized the data throughput of 50MB/s, when selecting the scsi interface controller, select the FAS566 Ultra160 scsi interface controller of Qlogic for use, FAS566 can realize the message transmission rate of 160MB/s.

When disk is conducted interviews, the seek time of disk is a principal element that influences disk performance, and therefore, we are optimized on disk block addressing algorithm, guarantee that as far as possible data write disk physical block continuously, thereby guarantee disk block ground effect access efficiency to a greater degree.

Above we have described the formation of high-speed data hardware of memory device and the principle of work of each several part, below we illustrate the concrete application of high-speed data memory device in data collecting field in conjunction with Fig. 2.

As shown in Figure 2, what dotted portion was represented among the figure is the high-speed data memory device that the utility model proposes, the high-speed data memory device is connected with system by pci bus, carry out data interaction by pci bus and system, and, be written in parallel to data or reading of data to disk by high-speed data path visit disk array.

The high-speed data memory device is supported the data acquisition and the playback card of various accord with PCI protocol specifications, comprises collection of simulant signal, playback card and digital signal acquiring, playback card.

When carrying out data acquisition, the capture card image data, and send the data to the high-speed data memory device by pci bus, the high-speed data memory device carries out dma operation by pci controller, obtain the data that capture card is gathered, and data parallel is write disk array.

When carrying out data readback, the high-speed data memory device is from the parallel reading of data of disk array, be merged into a chunk data after, by the dma operation of pci controller, data are sent to the data readback card by pci bus, data are carried out playback by the data readback card.

The foregoing description only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present utility model and enforcement according to this, can not limit protection domain of the present utility model with this.All equivalences of being done according to the utility model spirit change or modify, and all should be encompassed within the protection domain of the present utility model.

Claims (1)

1, a kind of high-speed data memory device is characterized in that: circuit is made up of data input, data partition/merging module, data check module, hard-disk interface module four parts;

Described data input comprises PCI/cPCI bus controller and steering logic, high capacity FIFO and data block buffer, wherein, PCI/cPCI bus controller and steering logic realize that with the PCI/cPCI bus data interaction is connected, and steering logic realizes control to the PCI/cPCI bus controller; The FIFO of PCI/cPCI bus controller, high capacity FIFO and data block buffer constitute a multistage data buffering successively, steering logic according to the almost empty of FIFO and almost full scale ambition FIFO write or from the FIFO reading of data; Data block buffer is made of jumbo DDR SDRAM and control circuit thereof;

Described data partition/merging module comprises data partition logic, data merge logic, one group of N small data block buffer, data buffering management and relevant control circuit, above-mentioned data block buffer is realized being connected by high-speed data path with N small data block buffer, and links up through data partition logic and data merging logic;

Described data check module comprises xor logic, check block buffer zone and relevant control circuit, the data check module is carried out the XOR computing by xor logic to the partition data through N small data block buffer, form corresponding checking data piece, deposit the check block buffer zone in; The pooled data that reads from hard-disk system is carried out the xor logic computing, the result is compared with the checking data that reads from check disk, realize the data fault-tolerant function of system;

Described hard-disk interface module comprises high speed interface and scsi interface controller, and high speed interface adopts the high-speed serial bus interface of multi-channel parallel work, and each scsi interface controller is controlled No. one hard disk, realizes the parallel data visit of disk array.

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