CN102012876A - Big bit width data writing and reading method and controller - Google Patents
Big bit width data writing and reading method and controller Download PDFInfo
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- CN102012876A CN102012876A CN2010105524344A CN201010552434A CN102012876A CN 102012876 A CN102012876 A CN 102012876A CN 2010105524344 A CN2010105524344 A CN 2010105524344A CN 201010552434 A CN201010552434 A CN 201010552434A CN 102012876 A CN102012876 A CN 102012876A
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Abstract
The invention discloses a big bit width data writing and reading method and a controller. The writing method comprises: the controller receives big bit width data from a processor; the controller splits the big bit width data into multiple small bit width data; the controller carries out synchronization on the small bit width data; and the controller transmits each small bit width data after synchronization to a dynamic random access memory (DRAM) corresponding to the small bit width data in a parallel way. The reading method comprises: the controller receives the small bit width data from each DRAM; the controller samples and caches the received small bit width data; the controller merges the cached small bit width data into big bit width data; and the controller transmits the merged big bit width data to the processor. By utilizing the technical scheme, wiring difficulty in single board design is reduced, and further interface time sequence between a DRAM controller and the DRAM is enhanced.
Description
Technical field
The present invention relates to data communication field and field of storage, in particular to the writing of a kind of big bit wide data, read method and controller.
Background technology
Along with enriching constantly and the continuous fusion of telecommunications operation of data communication service, operator improves day by day to the bandwidth requirement of data carrying product, therefore to business transmit, the performance and the capacity of statistical memory proposed higher demand.The pattern of the plug-in DRAM of core processor can realize more high-performance, the more jumbo professional function of tabling look-up and adding up storage of transmitting, and is one of gordian technique that is currently applied to data communication and field of data storage.
Enriching of the complexity of network structure and communication service proposing also the data bit wide to be had higher requirement in the bigger depth requirements to the DRAM storer, and this also objectively needs to improve constantly the data bit width and the handling property of dram controller.And the connected mode of current dram controller and big bit wide DRAM storer all adopts scheme shown in Figure 1.
Fig. 1 is the prior art scheme that dram controller 102 is communicated by letter with 105 of DRAM storeies, data channel 103 (bit wide of data is represented with N) and control channel 104 have been comprised, wherein processor/programming device 101 sends read write command by the control channel 104 of dram controller 102 to DRAM storer 105, transmits by data channel 103 to read and write data.Wherein, above-mentioned dram controller 102 generally comprises in processor/programming device 101, and promptly dram controller generally occurs as the submodule of processor/programming device.
Current raising along with processor/programming device arithmetic speed, system requires also strictness more to the sequential of dram controller interface, when data bit width was big, scheme shown in Figure 1 can reduce the interface sequence of dram controller, increased the wiring difficulty of single board design.For example, if data bit width is 32bit in actual applications, also will keep the alignment of all bit data under the situation of high speed data transfer, this difficulty for the wiring of single board design is bigger.
The inventor finds in the above-mentioned correlation technique, needs each data bit of data channel to have identical cabling time-delay when veneer connects up, and along with the increase of data bit width, this scheme will strengthen the wiring difficulty of single board design, the performance of reduction dram controller.
Summary of the invention
When connecting up, veneer strengthens the single board design difficulty at big bit wide data in the correlation technique owing to needing each data bit to have identical time-delay, the performance issue that reduces dram controller the invention provides the writing of a kind of big bit wide data, read method and controller, one of to address the above problem.
According to an aspect of the present invention, provide a kind of wiring method of big bit wide data, having comprised: controller receives the big bit wide data that come from processor; Above-mentioned controller is split as a plurality of little bit wide data with above-mentioned big bit wide data; Above-mentioned controller carries out synchronous processing to each above-mentioned little bit wide data; Above-mentioned controller each little bit wide data parallel after with above-mentioned synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.
According to another aspect of the present invention, provide a kind of read method of big bit wide data, having comprised: controller receives the little bit wide data that come from each dynamic RAM DRAM; Controller is sampled and buffer memory to the little bit wide data that receive; Above-mentioned controller is merged into big bit wide data with the little bit wide data of above-mentioned buffer memory; The big bit wide data of above-mentioned controller after with above-mentioned merging send processor to.
According to another aspect of the invention, provide a kind of controller, having comprised: first receiver module is used to receive the big bit wide data that come from processor; Split module, be used for above-mentioned big bit wide data are split as a plurality of little bit wide data; Synchronous processing module is used for each above-mentioned little bit wide data are carried out synchronous processing; First delivery module is used for each the little bit wide data parallel after the above-mentioned synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.
In accordance with a further aspect of the present invention, provide a kind of controller, having comprised: second receiver module is used to receive the little bit wide data that come from each dynamic RAM DRAM; Sampling module is used for the little bit wide data of above-mentioned reception are sampled and buffer memory; Merge module, be used for the little bit wide data behind the above-mentioned buffer memory are merged into big bit wide data; Second delivery module is used for sending the big bit wide data after the above-mentioned merging to processor.
Technical solution of the present invention only needs little bit wide data to have identical cabling time-delay on veneer, all bit aligned that do not need big bit wide data, solved in the correlation technique big bit wide data when veneer connects up owing to needing each data bit to have the problem that identical time-delay has strengthened the single board design difficulty, reduced the problem of the performance of dram controller, wiring difficulty when having reduced single board design, and then promoted interface sequence between dram controller and DRAM storer.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is for according to the structural representation of communicating by letter between the dram controller of correlation technique and outside DRAM storer;
Fig. 2 is a controller structured flowchart when according to the embodiment of the invention DRAM being carried out write operation;
Fig. 3 is a controller structured flowchart when according to the embodiment of the invention DRAM being carried out read operation;
Fig. 4 is the connection diagram according to preferred embodiment of the present invention dram controller and outside DRAM;
Fig. 5 is the inner structure synoptic diagram of dram controller according to the preferred embodiment of the invention;
Fig. 6 is the process flow diagram according to the big bit wide method for writing data of the embodiment of the invention;
Fig. 7 is for writing the data flow synoptic diagram according to dram controller embodiment illustrated in fig. 6;
Fig. 8 is the process flow diagram according to the big bit wide method for reading data of the embodiment of the invention;
Fig. 9 is the reading of data flow process synoptic diagram according to the dram controller of Fig. 8 embodiment.
Embodiment
Hereinafter will describe the present invention with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Fig. 2 is a controller structured flowchart when according to the embodiment of the invention DRAM being carried out write operation.As shown in Figure 2, this controller comprises:
First receiver module 20 is used to receive the big bit wide data that come from processor;
In preferred implementation process, above-mentioned fractionation module 22 on average splits into above-mentioned a plurality of little bit wide data with above-mentioned big bit wide data.
Synchronous processing module 24 is used for each above-mentioned little bit wide data are carried out synchronous processing;
First delivery module 26 is used for each the little bit wide data parallel after the above-mentioned synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.Preferably, above-mentioned a plurality of little bit wide data are corresponding one by one with described DRAM.
It should be noted that the structure that controller must comprise when dynamic RAM DRAM is carried out write operation embodiment illustrated in fig. 2.
Fig. 3 is a controller structured flowchart when according to the embodiment of the invention DRAM being carried out read operation.As shown in Figure 3, this controller comprises:
Merge module 34, be used for the little bit wide data behind the above-mentioned buffer memory are merged into big bit wide data;
It should be noted that the structure that controller must comprise when dynamic RAM DRAM is carried out read operation embodiment illustrated in fig. 3.
From Fig. 2 and as can be seen embodiment illustrated in fig. 3, the scheme of the foregoing description mainly comprises two parts: the selection of DRAM storer and the realization of dram controller.Promptly when the data bit width between dram controller and DRAM storer was big, the DRAM storer can be selected to be spliced by a plurality of less data bit widths, the constant DRAM storage chip of the degree of depth.Above-mentioned all little bit wide DRAM storeies connect identical control signal, and processor/programming device carries out read-write operation to above-mentioned little bit wide DRAM storer simultaneously by above-mentioned dram controller, finishes the fractionation and the merging of data in described dram controller.
Be to be understood that, Fig. 2 and embodiment illustrated in fig. 3 in the structure of controller form when concrete the application and can adopt same controller to realize, wherein, on function realizes, the function that this controller is realized comprise Fig. 2 and embodiment illustrated in fig. 3 described in the function that realizes of controller, on hardware is formed, then can comprise Fig. 2 and embodiment illustrated in fig. 3 in each module of controller.
The scheme of Fig. 2 and description embodiment illustrated in fig. 3 can adopt scheme execution as shown in Figure 4 when concrete the application.Fig. 4 is the connection diagram between dram controller 404 and outside DRAM storer (DRAM_1414, DRAM_2416, DRAM_W 418), if 404 data bit widths of communicating by letter of processor/programming device 402 and dram controller are N, the data bit width of selecting the DRAM storer for use is M (wherein N is the integral multiple of M), then adopts the technical program to need W=N/M DRAM storer altogether.Above-mentioned DRAM memory set links to each other with dram controller 404 by identical control channel 406, and bit wide is that the data channel of M adopts parallel processing mode to finish the merging and the fractionation of data in dram controller 404.Wherein, above-mentioned dram controller 404 generally comprises in processor/programming device 402 when concrete the application, and promptly dram controller generally occurs as the submodule of processor/programming device.
Synthesizing map 2, Fig. 3 and Fig. 4 embodiment can learn, carry out synchronous processing when the little bit wide data after the foregoing description splits big bit wide data send, the merging of during reception little bit wide data being sampled.Because above-mentioned little bit wide data are sampled under each self-clock of DRAM storer, therefore the present invention does not need big all bit of bit wide data to have identical cabling time-delay on veneer, only needs each little bit wide data and corresponding clock signal to have identical cabling time-delay on veneer and gets final product.This shows, adopt the scheme of the foregoing description, can improve the interface capability of dram controller, the wiring difficulty when reducing single board design simultaneously.
Fig. 5 is the inner structure synoptic diagram of dram controller according to the preferred embodiment of the invention.As shown in Figure 5, this controller comprises: DRAM control module 502, fractionation module 22, merging module 34, two-way processing module 504, logic control submodule 506.Wherein,
DRAM control module 502: finish the information interaction with processor/programming device, the read-write DRAM instruction that parsing processor/programming device sends sends to logic control submodule 506 to the control information of parsing.When processor/programming device sends write operation, big bit wide deal with data is transferred to fractionation module 22; And when read operation, then giving processor/programming device from the big bit wide data transmission that merges module 34.
It is to be noted, the function that above-mentioned DRAM control module 502 realizes comprise Fig. 2 and embodiment illustrated in fig. 3 in first receiver module 20 and the function that realized of second delivery module 36, from hardware, then can comprise first receiver module 20 and second delivery module 36.
Split module 22: this module realizes the partition of big bit wide data, the big bit wide that DRAM control module 502 is sent is write DRAM data average mark and is splitted into several little bit wide data (quantity of partition is decided according to the ratio size of the data bit width M of the data bit width N of processor and DRAM, be N/M), then little bit wide data are deposited into each transmission buffer area of two-way processing module 504 respectively (as sending buffer memory 1, send buffer memory 2, send buffer memory W etc.) in, select module (to select 1 by a plurality of directions again as direction, direction selects 2, direction is selected W etc.) data parallel is written in the corresponding D RAM storer.
Merge module 36: this module realizes the merging of a plurality of little bit wide data, be to send the inverse process that splits, it will be merged into big bit wide data from the little bit wide DRAM read data that two-way processing module receives in the buffer memory, and the conversion by DRAM control module 502 sends to processor/programming device at last and handles again.
Two-way processing module 504: this module is carried out parallel processing to little bit wide data, comprises many group transmission/reception metadata caches and direction and selects module, wherein because the time delay difference of clock network sends the synchronous processing that metadata cache is realized write data; Receive buffer memory and realize the data acquisition of each little bit wide data; Direction selects module to finish the conversion of one-way data and bi-directional data.
It is to be noted, the function that above-mentioned two-way processing module 504 realizes comprise Fig. 2 and embodiment illustrated in fig. 3 in the function that realized of first delivery module 26, synchronous processing module 24, second receiver module 30 and sampling module 32, from hardware, then can comprise first delivery module 26, synchronous processing module 24, second receiver module 30 and sampling module 32.
Logic control submodule 506: by with the information interaction of DRAM control module 502, produce the control signal of DRAM being carried out read-write operation, comprise address wire, chip selection signal, read etc.Also control the direction of two-way processing module 504 data stream simultaneously by the read-write operation of decision processor.
Fig. 6 is the process flow diagram according to the big bit wide method for writing data of the embodiment of the invention.As shown in Figure 6, this wiring method comprises:
Step S602, controller receives the big bit wide data that come from processor;
Step S604, above-mentioned controller is split as a plurality of little bit wide data with above-mentioned big bit wide data; In the preferred implementation process, above-mentioned controller on average splits into a plurality of little bit wide data with described big bit wide data.
Step S606, above-mentioned controller carries out synchronous processing to each above-mentioned little bit wide data;
Step S608, above-mentioned controller each little bit wide data parallel after with above-mentioned synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.Preferably, a plurality of little bit wide data are corresponding one by one with this DRAM.Be above-mentioned little bit wide data number can with above-mentioned this DRAM number correspondent equal.
Fig. 7 for according to dram controller embodiment illustrated in fig. 6 write the data flow synoptic diagram, as shown in Figure 7, this method flow comprises:
Step S702, processor/programming device carries out write operation to outside DRAM storer, and wherein the write data bit wide is Nbits;
Step S704 is by becoming W parallel Mbits data stream after the data fractionation;
Step S706 passes through synchronous processing respectively to above-mentioned parallel Mbits data stream;
Step S708 will send in the DRAM storer that is written to correspondence through the data of synchronous processing.
Fig. 8 is the process flow diagram according to the big bit wide method for reading data of the embodiment of the invention.As shown in Figure 7, this read method comprises:
Step S802, controller receives the little bit wide data that come from each dynamic RAM DRAM;
Step S804, controller is sampled and buffer memory to the little bit wide data that receive;
Step S806, above-mentioned controller is merged into big bit wide data with the little bit wide data of above-mentioned buffer memory;
Step S808, the above-mentioned controller big bit wide data after with above-mentioned merging send processor to.
Fig. 9 is the reading of data flow process synoptic diagram of dram controller embodiment illustrated in fig. 8.As shown in Figure 9, this method flow comprises:
Step S902, processor/programming device carries out read operation to outside DRAM storer, walks abreast by the Data Receiving port and reads W DRAM storer;
Step S904 samples respectively to the data of above-mentioned W DRAM storer reading;
Step S906 is merged into the Nbits data stream with above-mentioned W Mbits data, thereby finishes read operation.W=1/N wherein.
To be described in further detail the specific implementation of the above embodiment of the present invention in actual application below.
If the data processing bit wide of processor/programming device is 32bit, the degree of depth of required outside list item storage space is 16M, and the capacity of then plug-in DRAM storer should be 512Mbits (16M*32bits).
If select the scheme shown in Figure 1 in the correlation technique for use, then only needing to adopt a slice size is the DRAM storer of 4M*32bits*4banks (512Mbits), carries out information interaction by 32bits data line and dram controller.Though this scheme has been saved the space of device on the veneer, objectively also require above-mentioned 32 data lines on veneer, to have the time-delay of identical cabling, this is difficult realization in actual applications.And the delay inequality of any data line all can reduce the interface capability between dram controller and DRAM storer.
If select Fig. 2, need to adopt the little bit wide DRAM storer of multi-disc parallel running to technical solution of the present invention shown in Figure 9.For example select 8bits DRAM storer, then need 4 ability to form 32bits (4*8bits) data.For satisfying above-mentioned design conditions, can select for use the big or small DRAM storer of 4 4M*8bit*4banks (128Mbits) to realize the storage space of 512Mbits.
If employing is embodiment illustrated in fig. 5, above-mentioned data split module 22 the 32bits write data are split into 4 8bits data, through two-way processing module 504 data parallel are written in above-mentioned 4 DRAM storeies respectively then; Above-mentioned two-way processing module 504 sends metadata cache, 4 tunnel reception metadata caches and 4 tunnel directions by 4 the tunnel and selects module to form, and finishes the transmission and the reception of 8bits data respectively; And described merging module 32 is finished the merging of 4 road 8bits data.Specifically, at first being two-way processing module 504 receives the parallel deposit data that read in the buffer memorys in 4 the tunnel, and this module is merged into the 32bits data receiving 4 road 8bits data that buffer memory sends here, goes up sending processor/programming device then and handles.
Adopt the technical scheme of the embodiment of the invention, when current single board design, no longer need the 32bits alignment of data, only need the 8bits data of each DRAM storer correspondence to have identical cabling time-delay and get final product.Wiring difficulty when so just greatly reducing single board design has also improved the interface capability of dram controller simultaneously, can support the demand of the big bit wide data service of present two-forty.
When sending, the little bit wide data after comprehensive the foregoing description splits big bit wide data carry out synchronous processing, the merging of during reception little bit wide data being sampled.Because above-mentioned little bit wide data are sampled under each self-clock of DRAM storer, therefore the present invention does not need big all bit of bit wide data to have identical cabling time-delay on veneer, only needs each little bit wide data and corresponding clock signal to have identical cabling time-delay on veneer and gets final product.This shows, adopt the scheme of the foregoing description, can improve the interface capability of dram controller, the wiring difficulty when reducing single board design simultaneously.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the memory storage and carry out by calculation element, and in some cases, can carry out step shown or that describe with the order that is different from herein, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the wiring method of big bit wide data comprises
Controller receives the big bit wide data that come from processor;
Described controller is split as a plurality of little bit wide data with described big bit wide data;
Described controller carries out synchronous processing to each described little bit wide data;
Described controller each little bit wide data parallel after with described synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.
2. method according to claim 1 is characterized in that, described method also comprises:
Described a plurality of little bit wide data are corresponding one by one with described DRAM.
3. method according to claim 1 is characterized in that, the big bit wide data that come from processor that described controller will receive are split as a plurality of little bit wide data and comprise:
Described controller on average splits into described a plurality of little bit wide data with described big bit wide data.
4. the read method of big bit wide data is characterized in that, comprising:
Controller receives the little bit wide data that come from each dynamic RAM DRAM;
Controller is sampled and buffer memory to the little bit wide data of described reception;
Described controller is merged into big bit wide data with the little bit wide data of described buffer memory;
The big bit wide data of described controller after with described merging send described processor to.
5. a controller is characterized in that, comprising:
First receiver module is used to receive the big bit wide data that come from processor;
Split module, be used for described big bit wide data are split as a plurality of little bit wide data;
Synchronous processing module is used for each described little bit wide data are carried out synchronous processing;
First delivery module is used for each the little bit wide data parallel after the described synchronous processing is sent to the dynamic RAM DRAM corresponding with these little bit wide data.
6. controller according to claim 5 is characterized in that, described a plurality of little bit wide data are corresponding one by one with described DRAM.
7. controller according to claim 5 is characterized in that, described fractionation module on average splits into described a plurality of little bit wide data with described big bit wide data.
8. a controller is characterized in that, comprising:
Second receiver module is used to receive the little bit wide data that come from each dynamic RAM DRAM;
Sampling module is used for the little bit wide data of described reception are sampled and buffer memory;
Merge module, be used for the little bit wide data of described buffer memory are merged into big bit wide data;
Second delivery module is used for sending the big bit wide data after the described merging to described processor.
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