CN103680600B - A kind of storage device of applicable different bit wide data - Google Patents
A kind of storage device of applicable different bit wide data Download PDFInfo
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- CN103680600B CN103680600B CN201310701576.6A CN201310701576A CN103680600B CN 103680600 B CN103680600 B CN 103680600B CN 201310701576 A CN201310701576 A CN 201310701576A CN 103680600 B CN103680600 B CN 103680600B
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Abstract
The invention discloses the storage device of a kind of applicable different bit wide data, including: DI data acquisition unit, DI data outputting unit, data input pre-storing unit, data output pre-storing unit, data volume adjust and control logical block, data read-write control logical block and synchronous DRAM sdram controller；Wherein, the DI data acquisition figure place of every passage of DI data acquisition unit and the output figure place of DI data outputting unit are determined by data volume adjustment control logical block；Data read-write control logical block reads the data of data input pre-storing unit and writes sdram controller, is additionally operable to read the data in sdram controller, and exports to data output pre-storing unit, and is finally exported by DI data outputting unit.The storage device of the present invention, it is adaptable to the data high-speed collection of multichannel difference bit wide and storage；Storage efficiency can be improved, reduce cost；There is versatility, it is possible to adapt to different types of memorizer.
Description
Technical field
The present invention relates to technical field of data storage, particularly relate to the storage device of a kind of applicable different bit wide data.
Background technology
For multichannel digital quantity high speed acquisition module, owing to bus bandwidth limits, it is impossible to data are sent in real time host computer, it is therefore desirable to the data advanced person's row cache that will collect, read digital data by host computer after end to be collected, carry out follow-up data process and analysis.In use, the port number of collection needs user's arbitrary disposition, but the mass storage figure place used is typically all fixing.Therefore, no matter the port number of configuration is how many, all the data of fixing bit wide are sent into memorizer.If input channel number is less than this bit wide number, then a high position being write 0, such thinking is simple, flexible configuration, but shortcoming is also apparent from, only when the input channel number configured or output channel number are identical with the bit wide of memorizer, can effectively utilize storage space.When the port number of configuration is less than the bit wide number determined, will waste major part memory space, therefore, there is the problem often resulting in storage space waste when gathering data in prior art；Especially for the occasion requiring that big data quantity caches, the memory span increase of needs can significantly improve cost.Therefore, the data to the different bit wides collected effectively store, improve storage efficiency, reduce cost become design requirement.
Summary of the invention
The technical problem to be solved in the present invention is to provide the storage device of a kind of applicable different bit wide data, in order to solve the problem that prior art often results in storage space waste when gathering data.
For solving above-mentioned technical problem, the present invention provides the storage device of a kind of applicable different bit wide data, including:
DI data acquisition unit, DI data outputting unit, data input pre-storing unit, data output pre-storing unit, data volume adjust and control logical block, data read-write control logical block and synchronous DRAM sdram controller；Wherein, the DI data acquisition figure place of every passage of DI data acquisition unit and the output figure place of DI data outputting unit are adjusted control logical block by data volume and determine, the data that DI data acquisition unit collects first write data input pre-storing unit, and data read-write control logical block reads the data of data input pre-storing unit and writes sdram controller；Data read-write control logical block reads the data in sdram controller, and to data, the data output read is exported pre-storing unit, and is finally exported by DI data outputting unit.
Further, DI data acquisition unit is used for gathering DI data, by N number of single bit data stream write data input pre-storing unit；The corresponding single bit data stream of each passage, the data amount check comprised in each data stream is identical；DI data outputting unit reverts to the data stream of independent bit wide for data are exported the data in pre-storing unit.
Further, data volume adjusts and controls logical block, for adjusting, according to configuration, the data volume that DI data acquisition unit needs to gather；If data volume to be gathered is the integral multiple of sdram controller input data bits, the most do not adjust this data volume；If it is not, then the data volume that will gather increases to the integral multiple of sdram controller input data bits.
Further, data input pre-storing unit includes the First Input First Output FIFO of M 1 input N position output；Wherein, each FIFO capacity is 2N word；The corresponding single bit data stream of each FIFO；The a width of M of DI port number i.e. dominant bit gathered, sdram controller input data bits is also N.
Further, data output pre-storing unit includes that M N position inputs the FIFO of 1 output；Each FIFO capacity is 2N word；Each FIFO exports a single bit data stream.
Further, data read-write control logical block, it is used for according to the total bit wide of DI, the data of reading data input pre-storing unit, and adjusts the address of sdram controller, send write order to sdram controller, write data into sdram controller.
Further, to carry out writing control specific as follows for data read-write control logical block:
When in data input pre-storing unit, at least a FIFO storage has data, data read-write control logical block is successively read the data in each non-NULL FIFO, and successively the data of fixing bit wide are write sdram controller, until the data entered data in pre-storing unit in all FIFO are all written to sdram controller.
Further, data read-write control logical block is additionally operable to send reading order to sdram controller, reads data, in the data write data output pre-storing unit that then will read from SDRAM.
Further, when in data output pre-storing unit, all of FIFO all has the memory space setting capacity, then data read-write control logical block sends read command to sdram controller, after reading data, adjust address, the data write data read are exported in the FIFO that pre-storing unit is corresponding.
The present invention has the beneficial effect that:
The storage device of the present invention, it is adaptable to the data high-speed collection of multichannel difference bit wide and storage；Storage efficiency can be improved, reduce cost；There is versatility, it is possible to adapt to different types of memorizer.
Accompanying drawing explanation
Fig. 1 is the memory device structure schematic diagram of a kind of applicable different bit wide data in the embodiment of the present invention；
Fig. 2 is the structural representation of data input pre-storing unit in the embodiment of the present invention；
Fig. 3 is the structural representation of data output pre-storing unit in the embodiment of the present invention；
Fig. 4 is the flow chart that in the embodiment of the present invention, data read-write control logical block carries out data reading control logic；
Fig. 5 is the flow chart that in the embodiment of the present invention, data read-write control logical block carries out data write control logic.
Detailed description of the invention
Below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, does not limit the present invention.
The present invention proposes a kind of high-efficiency storage method, and is prone to the logic realization of field programmable logic device (FPGA, Field-ProgrammableGateArray).No matter the port number of configuration is how many, the data of different bit wides effectively can be stored, improve storage efficiency.
As it is shown in figure 1, the present embodiments relate to the storage device of a kind of applicable different bit wide data, including:
DI(DigitalInput, numeral input) data acquisition unit, DI data outputting unit, data input pre-storing unit, data output pre-storing unit, data volume adjust control logical block, data read-write control logical block, SDRAM(SynchronousDynamicRandomAccessMemory, synchronous DRAM) controller；The DI data acquisition figure place of every passage of DI data acquisition unit and the output figure place of DI data outputting unit are adjusted control logical block by data volume and determine, the data that DI data acquisition unit collects first write data input pre-storing unit, and data read-write control logical block reads the data of data input pre-storing unit and writes sdram controller；Data read-write control logical block reads the data in sdram controller, and to data, the data output read is exported pre-storing unit, and is finally exported by DI data outputting unit.
Wherein, DI data acquisition unit, it is used for gathering DI data, by N number of single bit data stream write data input pre-storing unit；The corresponding single bit data stream of each passage, the data amount check comprised in each data stream is identical.
DI data outputting unit, reverts to the data stream of independent bit wide for data are exported the data in pre-storing unit.
Data volume adjusts and controls logical block, for adjusting, according to configuration, the data volume that DI data acquisition unit needs to gather；If data volume to be gathered is the integral multiple of sdram controller input data bits, then this data volume is constant；If it is not, then the data volume that will gather increases to the integral multiple of sdram controller input data bits, so can ensure that the data integrity of data and memory element.
Data input pre-storing unit, including the FIFO(FirstInputFirstOutput of M 1 input N position output, First Input First Output), wherein, each FIFO capacity is 2N word；The corresponding single bit data stream of each FIFO.The a width of M of DI port number i.e. dominant bit gathered, sdram controller input data bits is N.The structure of data input pre-storing unit is as shown in Figure 2.
Data output pre-storing unit, inputs the FIFO of 1 output including M N position, and each FIFO capacity is 2N word；Each FIFO exports a single bit data stream.The structure of data output pre-storing unit is as shown in Figure 3.
Data read-write control logical block, is used for according to the total bit wide of DI, the data of reading data input pre-storing unit, and adjusts the address of sdram controller, send write order to sdram controller, the data of a width of N of fixed bit handled well are write sdram controller.The flow process of data write control logic is as shown in Figure 4:
The data stream that DI data acquisition unit collects is stored in data input pre-storing unit, after every channel data reaches N, after half-full signal is effective, data read-write control logical block is successively read the data in each non-NULL FIFO, and successively the data of fixing bit wide is write sdram controller.Often writing the data in a FIFO, bit wide enumerator can add 1 successively, and judges whether to have read the data in last FIFO according to the result of enumerator, if it is not, then the data read in next non-NULL FIFO；If it is, represent and the data in each non-NULL FIFO read once, bit wide counter O reset, return SBR, again detect, wait pending data stream to be again stored in data input pre-storing unit and re-write data stream.
Data read-write control logical block, is additionally operable to send reading order to sdram controller, reads data, in the data write data output pre-storing unit that then will read from SDRAM.Data are read to control the flow process of logic as shown in Figure 5.
First data read-write control logical block inquires about the currently stored amount of each FIFO in data output pre-storing unit, if at least one half-full, illustrate that data are the most removed, the most do not start reading sdram controller.The most half-full if all of FIFO, then show that data stream is normally read, data next time can be read from sdram controller, read command is sent to sdram controller, after reading data, adjust address, in the FIFO that write data output pre-storing unit is corresponding, and to bit wide rolling counters forward.When count results is less than N, then it is successively read the data in sdram controller, when count results is N, illustrates that an ergodic process completes, return SBR, again detect.
The present invention passes through input and output pre-storing unit and the data read-write control logic realization high efficiency storage technologies for a kind of applicable different bit wide data, and input bit wide is dynamically adapted, and type of memory can choose at random.Storage efficiency can be effectively improved, reduce cost, be highly suitable for multi-channel digital amount high speed acquisition and storage.
Although being example purpose, having been disclosed for the preferred embodiments of the present invention, those skilled in the art will be recognized by various improvement, increases and replace also is possible, and therefore, the scope of the present invention should be not limited to above-described embodiment.
Claims (7)
1. the storage device being suitable for different bit wide data, it is characterised in that including:
DI data acquisition unit, DI data outputting unit, data input pre-storing unit, data output pre-storing unit, data volume adjust and control logical block, data read-write control logical block and synchronous DRAM sdram controller；Wherein, the DI data acquisition figure place of every passage of DI data acquisition unit and the output figure place of DI data outputting unit are adjusted control logical block by data volume and determine, the data that DI data acquisition unit collects first write data input pre-storing unit, and data read-write control logical block reads the data of data input pre-storing unit and writes sdram controller；Data read-write control logical block reads the data in sdram controller, and to data, the data output read is exported pre-storing unit, and is finally exported by DI data outputting unit；
Data input pre-storing unit includes the First Input First Output FIFO of M 1 input N position output；Wherein, each FIFO capacity is 2N word；The corresponding single bit data stream of each FIFO；The a width of M of DI port number i.e. dominant bit gathered, sdram controller input data bits is also N；
Data output pre-storing unit includes that M N position inputs the FIFO of 1 output；Each FIFO capacity is 2N word；Each FIFO exports a single bit data stream.
2. the storage device being suitable for different bit wide data as claimed in claim 1, it is characterised in that DI data acquisition unit is used for gathering DI data, by N number of single bit data stream write data input pre-storing unit；The corresponding single bit data stream of each passage, the data amount check comprised in each data stream is identical；DI data outputting unit reverts to the data stream of independent bit wide for data are exported the data in pre-storing unit.
3. the storage device being suitable for different bit wide data as claimed in claim 1 or 2, it is characterised in that data volume adjusts and controls logical block, for adjusting, according to configuration, the data volume that DI data acquisition unit needs to gather；If data volume to be gathered is the integral multiple of sdram controller input data bits, the most do not adjust this data volume；If it is not, then the data volume that will gather increases to the integral multiple of sdram controller input data bits.
4. the storage device being suitable for different bit wide data as claimed in claim 1, it is characterized in that, data read-write control logical block, for according to the total bit wide of DI, read the data of data input pre-storing unit, and adjust the address of sdram controller, send write order to sdram controller, write data into sdram controller.
5. the storage device being suitable for different bit wide data as claimed in claim 4, it is characterised in that it is specific as follows that data read-write control logical block carries out writing control:
When in data input pre-storing unit, at least a FIFO storage has data, data read-write control logical block is successively read the data in each non-NULL FIFO, and successively the data of fixing bit wide are write sdram controller, until the data entered data in pre-storing unit in all FIFO are all written to sdram controller.
6. the storage device of the applicable different bit wide data as described in claim 1 or 5, it is characterized in that, data read-write control logical block is additionally operable to send reading order to sdram controller, reads data, in the data write data output pre-storing unit that then will read from SDRAM.
7. the storage device being suitable for different bit wide data as claimed in claim 6, it is characterized in that, when in data output pre-storing unit, all of FIFO all has the memory space setting capacity, then data read-write control logical block sends read command to sdram controller, after reading data, adjust address, the data write data read are exported in the FIFO that pre-storing unit is corresponding.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201654772U (en) * | 2010-05-10 | 2010-11-24 | 中国电子科技集团公司第十一研究所 | Storage medium interface conversion device |
| CN102012876A (en) * | 2010-11-19 | 2011-04-13 | 中兴通讯股份有限公司 | Big bit width data writing and reading method and controller |
| CN103076990A (en) * | 2012-12-25 | 2013-05-01 | 北京航天测控技术有限公司 | Data playback device based on FIFO (First In, First Out) caching structure |
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| CN201654772U (en) * | 2010-05-10 | 2010-11-24 | 中国电子科技集团公司第十一研究所 | Storage medium interface conversion device |
| CN102012876A (en) * | 2010-11-19 | 2011-04-13 | 中兴通讯股份有限公司 | Big bit width data writing and reading method and controller |
| CN103076990A (en) * | 2012-12-25 | 2013-05-01 | 北京航天测控技术有限公司 | Data playback device based on FIFO (First In, First Out) caching structure |
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