CN102063274A - Storage array, storage system and data access method - Google Patents
Storage array, storage system and data access method Download PDFInfo
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Abstract
The embodiment of the invention discloses a storage array, a storage system and a data access method. The data access method of a storage device comprises the following steps of: interconnecting data input from a user interface chip through a rapid external assembly to a PCIE (Peripheral Component Interface Express) chain and transmitting the data to a nonvolatile storage device, wherein the user interface chip and the nonvolatile storage device are connected to the PCIE chain and the nonvolatile storage device comprises a memory and a nonvolatile storage medium; writing the data in the memory of the nonvolatile storage device; and writing the data written in the memory of the nonvolatile storage device into the nonvolatile storage medium. The technical scheme provided in the embodiment is beneficial to reducing occupation of the data access to the PCIE chain and improves the performance of the system.
Description
Technical field
The present invention relates to field of computer technology, be specifically related to storage array and storage system and data access method.
Background technology
Traditional mechanical hard disk has mechanical part, and (IO, Input/Output) performance is lower in input and output.The existing system-level device that memory function can be provided mainly is to adopt mechanical hard disk as storage medium, and the method for designing of this series products (for example PC, server, storage array etc.) is to be based upon on the low IO performance basis of conventional hard.
In recent years, solid state hard disc (SSD, solid state disk) progressively rises, and the topmost characteristics of solid state hard disc are almost not have mechanical part, and the IO performance is very high.Utilize the performance of solid state hard disc designed system level product further to be promoted.
Referring to Fig. 1, the typical architecture of existing storage array (for example network attached storage equipment) is the X86 framework, and this system links to each other by user interface chip and user side (for example server etc.).Quick interconnected (the PCIE of peripheral component, Peripheral Component Interconnect Express) the bus switch chip is interconnected with central processing unit (CPU, central processing unit) and peripheral components such as user interface chip and memory interface chip.
Have now in the ablation process of the data that the user interface chip is imported, CPU control writes data into earlier in the internal memory that is connected with the CPU/ north bridge, finishes buffer memory (cache) and handle in this internal memory, and this data image is arrived another internal memory that is connected with the CPU/ north bridge; Then under the control of CPU, data are written to non-volatile memory medium from this internal memory.Existing data writing mode takies more PCIE link, has influence on the further lifting of system performance.
Summary of the invention
The embodiment of the invention provides storage array and storage system and data access method, to reduce data access the PCIE link is taken the elevator system performance.
For solving the problems of the technologies described above, the embodiment of the invention provides following technical scheme:
A kind of storage device data access method comprises:
To be delivered to Nonvolatile memory devices by the interconnected PCIE link of quick peripheral component from the data of user interface chip input, described user interface chip and described Nonvolatile memory devices are connected to the PCIE link, and described Nonvolatile memory devices comprises internal memory and non-volatile memory medium;
Described data are write in the internal memory of described Nonvolatile memory devices;
Data with writing in the internal memory of described Nonvolatile memory devices are written to described non-volatile memory medium.
A kind of storage array comprises:
Central processor CPU, user interface chip, the quick interconnected PCIE exchange chip of peripheral component and one or more Nonvolatile memory devices;
Wherein, the PCIE exchange chip is connected to the PCIE link with CPU, user interface chip and Nonvolatile memory devices; Described Nonvolatile memory devices comprises internal memory and non-volatile memory medium;
Described CPU is used to control and will be delivered to described Nonvolatile memory devices by the PCIE link from the data of described user interface chip input;
Described Nonvolatile memory devices is used for described data are write the internal memory of described Nonvolatile memory devices; Data with writing in the internal memory of described Nonvolatile memory devices write described non-volatile memory medium.
A kind of storage system comprises:
As the described storage array of above-mentioned embodiment, and the ustomer premises access equipment that is connected with the user interface chip of described storage array; Wherein, described ustomer premises access equipment is used for visiting described storage array by described user interface chip.
Therefore, the Nonvolatile memory devices of the storage device configurations in the embodiment of the invention comprises internal memory and non-volatile memory medium, internal memory and non-volatile memory medium are combined, and the data of user interface chip input directly are delivered in this Nonvolatile memory devices by the PCIE link, again it is stored in the non-volatile memory medium of this Nonvolatile memory devices, realize that promptly the user interface chip directly transmits to the data of Nonvolatile memory devices, can need not to carry out transfer through the internal memory of CPU control, this reading and writing data mechanism takies still less PCIE link with respect to prior art, helps promoting performance of storage system.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention and technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment and the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of storage array configuration diagram of prior art;
Fig. 2 is a kind of storage array configuration diagram that the embodiment of the invention provides;
Fig. 3 is a kind of data access method schematic flow sheet that the embodiment of the invention provides;
Fig. 4 is a kind of data access method schematic flow sheet that the embodiment of the invention two provides;
Fig. 5 is that a kind of data that the embodiment of the invention two provides write schematic flow sheet;
Fig. 6 is a kind of storage array synoptic diagram that the embodiment of the invention provides;
Fig. 7 is a kind of storage system synoptic diagram that the embodiment of the invention provides.
Embodiment
The embodiment of the invention provides storage array and storage system and data access method.
In order to make those skilled in the art person understand the present invention program better, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the embodiment of a part of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills should belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
For ease of understand implementing, a kind of framework of storage array at first is provided in the embodiment of the invention, referring to Fig. 2, the configuration diagram of a kind of storage array that Fig. 2 provides for example for the embodiment of the invention.Storage array can comprise at least one CPU and a plurality of Nonvolatile memory devices (for example SSD, mechanical hard disk or other Nonvolatile memory devices, among Fig. 2 be example with SSD), and at least one PCIE exchange chip.Wherein, the PCIE exchange chip disposes a plurality of PCIE interfaces, and the PCIE exchange chip can be connected to the PCIE link with peripheral components such as CPU and user interface chip and Nonvolatile memory devices.Wherein, Nonvolatile memory devices can comprise that (this internal memory can be a physical memory to internal memory, also can be virtual memory) and non-volatile memory medium, Nonvolatile memory devices also can comprise controller, this controller may command writes non-volatile memory medium with data from the internal memory of Nonvolatile memory devices, and with the data read of non-volatile memory medium storage to the internal memory of this Nonvolatile memory devices etc.
Wherein, the data access method of the embodiment of the invention can specifically be implemented based on the storage array of framework shown in Figure 2, also can specifically implement on the flexible distortion framework of this framework certainly.
Embodiment one
An embodiment of data access method of the present invention, can comprise: will be delivered to Nonvolatile memory devices by the interconnected PCIE link of quick peripheral component from the data of user interface chip input, this user interface chip is connected by the PCIE link with this Nonvolatile memory devices, and this Nonvolatile memory devices comprises internal memory and non-volatile memory medium; These data are write in the internal memory of this Nonvolatile memory devices; The non-volatile memory medium that data in the internal memory of this Nonvolatile memory devices are written to this Nonvolatile memory devices will be write.
Referring to Fig. 3, concrete steps can comprise:
310, will be delivered to Nonvolatile memory devices by the interconnected PCIE link of quick peripheral component from the data of user interface chip input;
Under a kind of application scenarios, when certain data of ustomer premises access equipment (for ease of citation, be referred to as first data) in the time of need writing this memory device by the user interface chip of memory device (for example storage array or general memory device), can will be delivered to a certain Nonvolatile memory devices (, can be referred to as first Nonvolatile memory devices) of this memory device from first data of user interface chip input by the PCIE link by CPU control for ease of citation.
Wherein, storage device configurations has and comprises one or more Nonvolatile memory devices (for example Nonvolatile memory devices of SSD, mechanical hard disk or other storage media types); Nonvolatile memory devices comprises internal memory and non-volatile memory medium etc.; The user interface chip provides user interface, mainly is responsible for the data interaction of ustomer premises access equipment and memory device.
Wherein, the internal memory of Nonvolatile memory devices can be: Double Data Rate (DDR, Double Data Rate) volatile storage medium of synchronous DRAM, DDRII synchronous DRAM, the contour performance of DDRIII synchronous DRAM perhaps also can be virtual memory.Non-volatile memory medium can comprise: flash memory (flash), ferroelectric storage medium or other storage medium.
In actual applications, if the user interface chip is access block (Block) equipment directly, then the CPU may command will be written to certain logical storage address (LBA, logic Block address) of first Nonvolatile memory devices from first data of user interface chip input by the PCIE link.If the user interface chip can not directly be visited Block equipment, but can visit storage (Memory) equipment, then CPU is when being the first Nonvolatile memory devices initialization that inserts, can be first Nonvolatile memory devices and distribute one section Memory window address space (wherein, the size in this Memory window address space for example can equal the size of the internal memory (as 4GB) of this Nonvolatile memory devices, perhaps also can equal the size of the logical memory space (for example 400GB) of this Nonvolatile memory devices, can certainly be other value), when the user interface chip is imported first data, the CPU may command will be written to certain PCIE bus Memory window address of first Nonvolatile memory devices from first data of user interface chip input by the PCIE link.
320, above-mentioned data are write in the internal memory of above-mentioned Nonvolatile memory devices;
Wherein, the Nonvolatile memory devices integrated memory has been created condition for cache becomes distributed management by centralized management.
330, will write data in the internal memory of above-mentioned Nonvolatile memory devices, be written to the non-volatile memory medium of above-mentioned Nonvolatile memory devices.
Under a kind of application scenarios, Nonvolatile memory devices can also comprise controller, this controller can carry out buffer memory (cache) management to the internal memory of this Nonvolatile memory devices, comprise: input and output polymerization (IO polymerization), data hit, data are eliminated or the like, wherein, concrete cache operating strategy can specifically be set as the case may be, does not do qualification herein.If first Nonvolatile memory devices is the memory storage that has distributed PCIE bus Memory window address space, then CPU can be by the control signaling, mapping corresponding relation with the logical memory space address of the above-mentioned PCIE bus Memory window address and first Nonvolatile memory devices, notify first Nonvolatile memory devices (certainly, if the mapping corresponding relation of the logical memory space address of PCIE bus Memory window address and Nonvolatile memory devices, be the CPU and first Nonvolatile memory devices a kind of acquiescence corresponding relation of agreement in advance, then CPU can be not be notified to first Nonvolatile memory devices with the mapping corresponding relation of the logical memory space address of the above-mentioned PCIE bus Memory window address and first Nonvolatile memory devices).The controller of first Nonvolatile memory devices can write first data in the internal memory of this Nonvolatile memory devices; This controller can (this cache management strategy can comprise: when the remaining space of the internal memory of Nonvolatile memory devices is lower than certain threshold value, the data in the write memory are write non-volatile memory medium based on default cache management strategy; Perhaps the data instant that will be written in the internal memory writes non-volatile memory medium, can certainly comprise other cache management strategy), and according to the mapping corresponding relation of the logical memory space address of the above-mentioned PCIE bus Memory window address and first Nonvolatile memory devices, and the mapping corresponding relation of the logical memory space address of first Nonvolatile memory devices and amount of physical memory address, control will write first data in the internal memory of first Nonvolatile memory devices, be written in the non-volatile memory medium of first Nonvolatile memory devices.In addition, if CPU has carried out unified addressing to the memory headroom of first Nonvolatile memory devices, then also can first data be write in the internal memory of this Nonvolatile memory devices by CPU control, and, the non-volatile memory medium that first data in the internal memory of this Nonvolatile memory devices write this Nonvolatile memory devices will be write based on default cache management strategy.
In actual applications, when the controller of first Nonvolatile memory devices writes the internal memory of this first Nonvolatile memory devices with first data, this controller can judge whether be cached with the data identical with first data in the internal memory of this Nonvolatile memory devices (for ease of describing earlier, can be referred to as second data), if do not have; Then first data are write the internal memory of this Nonvolatile memory devices; If have, then with these second data as first data in the internal memory that is written to Nonvolatile memory devices (promptly this moment controller no longer control the internal memory that first data is written to Nonvolatile memory devices, and with second data as first data in the internal memory that is written to Nonvolatile memory devices).
Can find that in the such scheme of present embodiment, the ablation process of a certain data only need take the PCIE link one time, this bus resource that will effectively reduce data writing process takies.
Further, if also need from the Nonvolatile memory devices reading of data, then the controller of the Nonvolatile memory devices data read of storing in also can the non-volatile memory medium with this Nonvolatile memory devices is in the internal memory of Nonvolatile memory devices; The data that read in the internal memory of this Nonvolatile memory devices are delivered to the user interface chip by the PCIE link; Perhaps, can pass to CPU by the PCIE link and handle reading data in the internal memory of this Nonvolatile memory devices.
Be understandable that, memory device is in the reading and writing data process, the disparate modules of memory device may carry out certain conversion to the encapsulation format of data, for example, the user interface chip can be converted to the PCIE message with the encapsulation format from the data of ustomer premises access equipment, and need are converted to the pairing encapsulation format of this ustomer premises access equipment to the data that ustomer premises access equipment sends; Nonvolatile memory devices then can be removed the heading from the PCIE message of user's interface chip or other module, and is cached to internal memory and writes non-volatile memory medium; Nonvolatile memory devices also can be the PCIE message and send to the data encapsulation of user interface chip or the transmission of other module the need that read from its internal memory; Certainly, different application scenarioss, the encapsulation format of data correspondence may be different, gives unnecessary details no longer one by one herein.
Therefore, the Nonvolatile memory devices of the storage device configurations in the present embodiment comprises internal memory and non-volatile memory medium, internal memory and non-volatile memory medium are combined, and the data of user interface chip input directly are delivered in the Nonvolatile memory devices by the PCIE link, again it is stored in the non-volatile memory medium of Nonvolatile memory devices, realize that promptly the user interface chip directly transmits to the data of SSD, can need not to carry out transfer through the internal memory of CPU control, this reading and writing data mechanism takies still less PCIE link with respect to prior art, helps promoting performance of storage system.
Further, owing to be the Nonvolatile memory devices allocate memory, memory device provides bigger memory interface bandwidth if a plurality of Nonvolatile memory devices of configuration then can provide the main memory access that is several times as much as prior art, further promotes performance of storage system.
Embodiment two
For ease of better understanding the technical scheme of the embodiment of the invention, be example with the concrete application scenarios that under storage array framework shown in Figure 2, carries out data access below, be described in detail.
Wherein, the Nonvolatile memory devices that mainly comprises with storage array in the present embodiment is that solid state hard disc is that example is described, and adopts the workflow of Nonvolatile memory devices of other type similar in this.
Referring to Fig. 4, embodiment of data access method of the present invention can comprise:
401, the user interface chip writes certain data (for ease of citation, being referred to as data D1) from ustomer premises access equipment by instruction to CPU request;
402, CPU writes the PCIE bus Memory window address (for ease of citation, being referred to as PCIE bus Memory window address add-1) that data D1 distributes certain solid state hard disc (for ease of citation, being referred to as solid-state hard disk SSD-1) for the user interface chip;
Storage array for example shown in Figure 2 can comprise at least one PCIE exchange chip.The PCIE exchange chip disposes a plurality of PCIE interfaces, and various peripheral component PCIE exchange chips such as CPU and user interface chip, solid state hard disc are connected to the PCIE bus links.
Wherein, solid state hard disc in the present embodiment can dispose at least two PCIE interfaces, with the PCIE interface of the different PCIE exchange chips that connect respectively,, can avoid like this can't working because of single point failure causes this solid state hard disc owing to be connected to the PECI exchange chip by many PCIE links.
In actual applications, CPU is when being solid-state hard disk SSD-1 initialization that inserts, CPU can scan the configuration space of this solid state hard disc, can be according to the applications in the PCIE bus Memory window address space of this configuration space record that scans, the PCIE bus Memory window address space of distributing respective amount for this solid state hard disc, (size of this Memory window for example can equal the size of the internal memory (as 4GB) of this solid state hard disc for this solid-state hard disk SSD-1 is distributed one section PCIE bus Memory window address space, perhaps also can equal the size of the logical memory space (for example 400GB) of this solid state hard disc, can certainly be other value), when the request of user interface chip write data D1, CPU can be the user interface chip and writes the PCIE bus Memory window address add-1 that data D1 distributes corresponding solid-state hard disk SSD-1;
403, the user interface chip is written to data D1 the PCIE bus Memory window address add-1 of solid-state hard disk SSD-1 by the PCIE link.
404, the controller of solid-state hard disk SSD-1 writes the internal memory of solid-state hard disk SSD-1 with data D1, and will write the data in solid-state hard disk SSD-1 internal memory, is written to the non-volatile memory medium of this solid-state hard disk SSD-1;
In actual applications, the controller of solid-state hard disk SSD-1 can carry out the cache management to the internal memory of this solid-state hard disk SSD-1, can comprise: input and output polymerization (IO polymerization), data hit, data are eliminated etc., wherein, concrete cache operating strategy can specifically be set as the case may be, does not do qualification herein.
For instance, if the space that the internal memory of solid-state hard disk SSD-1 residue is enough, the controller of solid-state hard disk SSD-1 can write data D1 the internal memory of solid-state hard disk SSD-1, certainly, if its low memory, then the controller of solid-state hard disk SSD-1 can be eliminated the unnecessary data (unnecessary data for example can be long-time not accessed data) in this internal memory earlier, then again data D1 is write the internal memory of solid-state hard disk SSD-1, and this can regard a kind of distributed cache management that solid-state hard disk SSD-1 is carried out as, transfer the cache management function of CPU, to reduce the working load of CPU.
Under a kind of application scenarios, CPU can be with the mapping corresponding relation of the logical memory space address of above-mentioned PCIE bus Memory window address add-1 and solid-state hard disk SSD-1 (wherein, there is certain mapping corresponding relation between the logical memory space address of PCIE bus Memory window address and corresponding solid state hard disc, this mapping corresponding relation available window address mapping table writes down), notice solid-state hard disk SSD-1 (certainly, if the mapping corresponding relation between the logical memory space address of PCIE bus Memory window address and solid state hard disc, be CPU and solid state hard disc a kind of acquiescence corresponding relation of agreement in advance, then CPU can be not notify this solid state hard disc with the mapping corresponding relation of the logical memory space address of PCIE bus Memory window address add-1 and first solid-state hard disk SSD-1).The controller of solid-state hard disk SSD-1 can write data D1 in the internal memory of this solid state hard disc; And according to the corresponding relation of the logical memory space address of above-mentioned PCIE bus Memory window address add-1 and solid-state hard disk SSD-1, and the mapping corresponding relation of the logical memory space address of solid-state hard disk SSD-1 and amount of physical memory address (wherein, the mapping corresponding relation of the logical memory space of solid state hard disc and amount of physical memory, be recorded in the logical address mapping table of solid state hard disc maintenance), control will write the data D1 in the internal memory of solid-state hard disk SSD-1, be written in the non-volatile memory medium of solid-state hard disk SSD-1, for example can write synoptic diagram referring to data shown in Figure 5.
In actual applications, the controller of solid-state hard disk SSD-1 can judge earlier in the internal memory of solid-state hard disk SSD-1 whether the data identical with data D1 have been arranged, if do not have, then can write in the internal memory of solid-state hard disk SSD-1 by data D1; If have, the data identical with data D1 that then can directly this have been write write the non-volatile memory medium of solid-state hard disk SSD-1 as data D1, and need not to carry out data D1 are written to internal memory, are then written to the operation of non-volatile memory medium.And this also can regard a kind of distributed cache management that solid-state hard disk SSD-1 is carried out as, has transferred the cache management function of CPU, to reduce the working load of CPU.
Can find that in the scheme of present embodiment, the ablation process of data D1 only need take the PCIE link one time, this bus resource that will effectively reduce data writing process takies.
Further, if also need from solid-state hard disk SSD-1 reading of data D1, then the data D1 that stores in can the non-volatile memory medium with this solid-state hard disk SSD-1 of the controller of solid-state hard disk SSD-1 reads in the internal memory of solid-state hard disk SSD-1; The data D1 that reads in the internal memory of this solid-state hard disk SSD-1 is delivered to user interface chip (if user interface chip requests data reading D1) by the PCIE link; Perhaps can pass to CPU by the PCIE link and handle (if CPU needs reading of data D1 to handle) reading data in the internal memory of this solid state hard disc.
Therefore, the solid state hard disc of the storage device configurations in the present embodiment comprises internal memory and non-volatile memory medium, internal memory and non-volatile memory medium (being comprised: flash memory, the storage medium of ferroelectric storage medium or other type) combines, and the data of user interface chip input directly are delivered in the solid state hard disc by the PCIE link, again it is stored in the non-volatile memory medium of solid state hard disc, realize that promptly the user interface chip directly transmits to the data of SSD, can need not to carry out transfer through the internal memory of CPU control, this data access mechanism takies still less PCIE link with respect to prior art, helps promoting performance of storage system.
Further, because the solid state hard disc allocate memory, memory device provides bigger memory interface bandwidth if a plurality of solid state hard discs of configuration then can provide the main memory access that is several times as much as prior art, further promotes performance of storage system.
Partly or entirely cache management function (comprising: data read-write control, IO polymerization, data hit, data eliminate etc.) is converted to the distributed management of each solid state hard disc by the CPU centralized management, can reduce the processing load of CPU so relatively, further promote performance of storage system.And, adopt the storage array of this embodiment framework, help reducing the volume and the power consumption of storage array.
For ease of the technical scheme of better implement the foregoing description, the embodiment of the invention also is provided for realizing the equipment of technique scheme.
Referring to Fig. 6, a kind of storage array 600 that the embodiment of the invention provides can comprise:
Wherein, PCIE exchange chip 630 is connected to the PCIE link with central processing unit 610, user interface chip 620 and Nonvolatile memory devices 640; Nonvolatile memory devices 600 comprises internal memory and non-volatile memory medium;
Under a kind of application scenarios, if not volatile storage is the memory storage that has distributed PCIE bus Memory window address space; Central processing unit 610 can specifically be used for, and control will be written to the PCIE bus Memory window address of Nonvolatile memory devices 640 from the data of user interface chip 420 inputs by the PCIE link.
Under a kind of application scenarios, central processing unit 610 also is used for, by the corresponding relation of control signaling with the logical memory space address of PCIE bus Memory window address and Nonvolatile memory devices, notice Nonvolatile memory devices 640;
Wherein, if not the space that the internal memory of volatile storage 640 residue is enough, the controller of Nonvolatile memory devices 640 can write data the internal memory of Nonvolatile memory devices 640, certainly, if its low memory, then the controller of Nonvolatile memory devices 640 can be eliminated the unnecessary data in this internal memory earlier, then again data to be written are write the internal memory of Nonvolatile memory devices 640, and a kind of distributed caching management that this controller that can regard Nonvolatile memory devices 640 as is carried out, transfer the cache management function of CPU, to reduce the working load of CPU.
In actual applications, the controller of Nonvolatile memory devices 640 can judge earlier also in the internal memory of Nonvolatile memory devices 640 whether second data identical with data to be written have been arranged, if have, second then that can directly this have been write the identical data with data to be written, write the non-volatile memory medium of Nonvolatile memory devices 640, be written to internal memory and need not to carry out above-mentioned data to be written, be written into the operation of non-volatile memory medium again.And this also can regard a kind of distributed cache management that Nonvolatile memory devices 640 carries out as, has transferred the cache management function of CPU, to reduce the working load of CPU.
Under a kind of application scenarios, Nonvolatile memory devices 640 also is used for, and the data read of storing in the non-volatile memory medium with Nonvolatile memory devices 640 is in the internal memory of solid state hard disc; The data that read in the internal memory of Nonvolatile memory devices 640 are delivered to the user interface chip by the PCIE link; Perhaps, pass to central processing unit 610 by the PCIE link and handle reading data in the internal memory of Nonvolatile memory devices 640.
Wherein, the Nonvolatile memory devices 640 of present embodiment for example can be SSD, mechanical hard disk or other Nonvolatile memory devices.
The storage array 600 that is appreciated that present embodiment can be separate equipment, also can be used as the memory device of certain equipment.For example, storage array 600 can be used for storage system, server, workstation, PC or the like.
Be appreciated that, the storage array 600 of present embodiment can be as the storage array among the above-mentioned method embodiment, it can be used for realizing whole technical schemes of said method embodiment, the function of its each functional module can be according to the method specific implementation among the said method embodiment, its specific implementation process can repeat no more with reference to the associated description in the foregoing description herein.
Therefore, the Nonvolatile memory devices of storage array 600 configurations in the present embodiment comprises internal memory and non-volatile memory medium, internal memory and non-volatile memory medium are combined, and the data of user interface chip input directly are delivered in the Nonvolatile memory devices by the PCIE link, again it is stored in the non-volatile memory medium of Nonvolatile memory devices, realize that promptly the user interface chip directly transmits to the data of SSD, can need not to carry out transfer through the internal memory of CPU control, this reading and writing data mechanism takies still less PCIE link with respect to prior art, helps promoting performance of storage system.
Referring to Fig. 7, the embodiment of the invention also provides a kind of storage system, can comprise: storage array 600, and the ustomer premises access equipment 700 that is connected with the user interface chip of storage array 600.
Wherein, ustomer premises access equipment 700 can be used for the user interface chip by storage array 600, visit storage array 600, and for example ustomer premises access equipment 700 can write data to storage array 600, and/or, from storage array 600 reading of data etc.
Need to prove, for aforesaid each method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other order or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
In the above-described embodiments, the description of each embodiment is all emphasized particularly on different fields, do not have the part that describes in detail among certain embodiment, can be referring to the associated description of other embodiment.
To sum up, the Nonvolatile memory devices of the storage device configurations in the embodiment of the invention comprises internal memory and non-volatile memory medium, internal memory and non-volatile memory medium are combined, and the data of user interface chip input directly are delivered in the Nonvolatile memory devices by the PCIE link, again it is stored in the non-volatile memory medium of Nonvolatile memory devices, this data writing mechanism takies still less PCIE link with respect to prior art, helps promoting performance of storage system.
Further, because the Nonvolatile memory devices allocate memory, memory device provides bigger memory interface bandwidth if a plurality of Nonvolatile memory devices of configuration then can provide the main memory access that is several times as much as prior art, further promotes performance of storage system.
Partly or entirely cache management function (eliminate as data read-write control, IO polymerization, data hit, data etc.) is changed into the distributed management of each Nonvolatile memory devices by the CPU centralized management, can reduce the processing load of CPU so relatively, further promote performance of storage system.And, adopt the storage array of this framework to help reducing the volume and the power consumption of storage array.
One of ordinary skill in the art will appreciate that all or part of step in the whole bag of tricks of the foregoing description is to instruct relevant hardware to finish by program, this program can be stored in the computer-readable recording medium, and storage medium can comprise: ROM (read-only memory), random access memory, disk or CD etc.
More than storage array that the embodiment of the invention provided and storage system and data access method are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, to sum up, this description should not be construed as limitation of the present invention.
Claims (10)
1. a storage device data access method is characterized in that, comprising:
To be delivered to Nonvolatile memory devices by the interconnected PCIE link of quick peripheral component from the data of user interface chip input, described user interface chip and described Nonvolatile memory devices are connected to the PCIE link, and described Nonvolatile memory devices comprises internal memory and non-volatile memory medium;
Described data are write in the internal memory of described Nonvolatile memory devices;
Data with writing in the internal memory of described Nonvolatile memory devices are written to described non-volatile memory medium.
2. method according to claim 1 is characterized in that,
Describedly will be delivered to Nonvolatile memory devices by the interconnected PCIE link of quick peripheral component, comprise from the data of user interface chip input:
Central processor CPU will be written to the PCIE bus store M emory window address of Nonvolatile memory devices from the data of user interface chip input by the PCIE link; Wherein, described Nonvolatile memory devices is the memory device that has distributed PCIE bus Memory window address space.
3. method according to claim 2 is characterized in that,
Described method also comprises:
CPU notifies described Nonvolatile memory devices by the corresponding relation of steering order with the logical memory space address of described PCIE bus Memory window address and solid state hard disc;
Described Nonvolatile memory devices also comprises controller, in the described internal memory that described data is write described Nonvolatile memory devices; Data with writing in the internal memory of described Nonvolatile memory devices are written to described non-volatile memory medium, comprising:
The controller of described Nonvolatile memory devices writes described data in the internal memory of described Nonvolatile memory devices; And according to the corresponding relation of the logical memory space address of described PCIE bus Memory window address and Nonvolatile memory devices, and the mapping corresponding relation of the logical memory space address of described Nonvolatile memory devices and amount of physical memory address, with the data that write in the internal memory of described Nonvolatile memory devices, correspondence is written to described non-volatile memory medium.
4. according to each described method of claim 1 to 3, it is characterized in that described method also comprises:
With the data read of storing in the described non-volatile memory medium in the internal memory of described Nonvolatile memory devices;
The data that read in the internal memory of described Nonvolatile memory devices are delivered to the user interface chip by the PCIE link; Perhaps, pass to CPU by the PCIE link and handle reading data in the internal memory of described Nonvolatile memory devices.
5. according to each described method of claim 1 to 3, it is characterized in that, described data write in the internal memory of described Nonvolatile memory devices, comprising:
Judge the second identical data of data that whether have been cached with in the internal memory of described Nonvolatile memory devices with the input of user interface chip, if do not have; Then the data of described user interface chip input are write the internal memory of described Nonvolatile memory devices; If have, then with the data of described second data as the described user interface chip input in the internal memory that is written to Nonvolatile memory devices.
6. a storage array is characterized in that, comprising:
Central processor CPU, user interface chip, the quick interconnected PCIE exchange chip of peripheral component and one or more Nonvolatile memory devices;
Wherein, the PCIE exchange chip is connected to the PCIE link with CPU, user interface chip and Nonvolatile memory devices; Described Nonvolatile memory devices comprises internal memory and non-volatile memory medium;
Described CPU is used to control and will be delivered to described Nonvolatile memory devices by the PCIE link from the data of described user interface chip input;
Described Nonvolatile memory devices is used for described data are write the internal memory of described Nonvolatile memory devices; Data with writing in the internal memory of described Nonvolatile memory devices write described non-volatile memory medium.
7. storage array according to claim 6 is characterized in that, described Nonvolatile memory devices is the memory device that has distributed PCIE bus Memory window address space;
Described CPU specifically is used for, and control will be written to the PCIE bus Memory window address of described Nonvolatile memory devices from the data of user interface chip input by the PCIE link.
8. storage array according to claim 7 is characterized in that,
Described CPU also is used for, and by the corresponding relation of control signaling with the logical memory space address of described PCIE bus Memory window address and Nonvolatile memory devices, notifies described Nonvolatile memory devices;
Described Nonvolatile memory devices also comprises controller, and described controller is used for described data are write the internal memory of described Nonvolatile memory devices; And according to the corresponding relation of the logical memory space address of described PCIE bus Memory window address and Nonvolatile memory devices, and the mapping corresponding relation of the logical memory space address of described Nonvolatile memory devices and amount of physical memory address, with the data that write in the internal memory of described Nonvolatile memory devices, correspondence is written to described non-volatile memory medium.
9. according to each described storage array of claim 6 to 8, it is characterized in that,
Described Nonvolatile memory devices also is used for, with the data read of storing in the described non-volatile memory medium in the internal memory of described Nonvolatile memory devices; The data that read in the internal memory of described Nonvolatile memory devices are delivered to the user interface chip by the PCIE link; Perhaps, pass to CPU by the PCIE link and handle reading data in the internal memory of described Nonvolatile memory devices.
10. a storage system is characterized in that, comprising:
As each described storage array of claim 6 to 9, and the ustomer premises access equipment that is connected with the user interface chip of described storage array; Wherein, described ustomer premises access equipment is used for visiting described storage array by described user interface chip.
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| CN 201010615960 CN102063274B (en) | 2010-12-30 | 2010-12-30 | Storage array, storage system and data access method |
| PCT/CN2011/084999 WO2012089154A1 (en) | 2010-12-30 | 2011-12-30 | Storage array, storage system, and data access method |
| EP20110852505 EP2565772A4 (en) | 2010-12-30 | 2011-12-30 | Storage array, storage system, and data access method |
| US13/715,409 US8719490B2 (en) | 2010-12-30 | 2012-12-14 | Storage array, storage system, and data access method |
| US14/140,867 US9098404B2 (en) | 2010-12-30 | 2013-12-26 | Storage array, storage system, and data access method |
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