CN116955258B - Flexibly-connectable trigger connector, signal acquisition control equipment and system - Google Patents
Flexibly-connectable trigger connector, signal acquisition control equipment and system Download PDFInfo
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- G—PHYSICS
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The application discloses a trigger connector capable of being flexibly connected, signal acquisition control equipment and a system, and relates to the technical field of signal triggering. The trigger connector comprises a trigger interface circuit and an uplink and downlink cascade trigger interface circuit, wherein the trigger interface circuit is used for connecting a first interface IP unit which is connected with an equipment FPGA module and provides a DIO channel and connecting external trigger signal distribution equipment, and the uplink/downlink cascade trigger interface circuit is used for connecting a second interface IP unit which is connected with the equipment FPGA module and also provides the DIO channel and connecting external equipment which is positioned on the uplink/downlink, so that the purposes of cascade uplink/downlink transmission of trigger signals and/or synchronous transmission of star trigger signals with higher synchronous precision can be realized, and the equipment simultaneously meets the characteristics of light and portable appearance, good equipment expansibility, strong timing trigger capability, high synchronous precision and the like.
Description
Technical Field
The application belongs to the technical field of signal triggering, and particularly relates to a flexibly-connectable triggering connector, signal acquisition control equipment and a system.
Background
With the rapid development of analog circuits, digital circuits, and signal processing technologies, large electronic equipment often has complex but tight operating mechanisms and timings. Taking a particle accelerator commonly adopted by basic physical research and a radioactive medical system as an example, a power supply control system of a magnet for accelerating and controlling the movement of particles and a signal acquisition device for measuring particle parameters are required to have synchronous precision accurate to microsecond, and meanwhile, a strictly defined sequential logic trigger signal is required to trigger work. In addition, some radar and communication systems having multiple antennas also include multiple receivers and multiple transmitters that require precise clock synchronization and operate with precise timing. At the same time, these devices and systems often require extensive deployment and testing in the field, so the consumer's need for their portability and low cost features is strong. Therefore, a signal acquisition control device with complex timing triggering capability, accurate clock synchronization capability, and portable structural form would be a great aid to such applications.
Currently, in the market, signal acquisition control devices with complex timing triggering capability and accurate clock synchronization capability are mainly bus instrument systems, and their main bus architectures are PXIE (Peripheral Component Interconnection extensions for Instrumentation Express, an optimized version of peripheral component interconnect extension for instrument systems), AXIE (Advanced eXtensible Interface Express, an optimized version of bus protocol), VPX (a new generation of high-speed serial bus standard proposed by VME international trade association organization VITA on the basis of its VME bus in 2007), and the like.
The three types of instrument bus architectures, namely PXIE, AXIE and VPX, are all based on PCIE (Peripheral Component Interconnect Express, which is a high-speed serial computer expansion bus standard, originally named as '3 GIO', which is proposed by Intel in 2001 and aims to replace the old PCI, PCI-X and AGP bus standards) buses to expand instrument functions, and a plurality of functional modules can be installed. These buses all have standard or customizable synchronous timing hardware functions, which can achieve accurate synchronous timing and complex timing triggers.
However, the PCIE bus-based instrument system requires a special system chassis and a system controller, where the system chassis provides functions such as bus back board, system power supply, system heat dissipation, and structure fixing; the system controller provides functions of system control, man-machine interaction, signal processing, data storage, peripheral connection and the like. Although these system chassis and controllers are based on PCIE bus and advanced computer technology, they provide excellent performance for the system, but are also designed specifically, so they have a large volume, a general weight of more than 10kg, and require external keyboards, mice, and displays, so portability is not good. Meanwhile, the cost is high because of small yield, and the cost of the system often accounts for more than half of the cost of the whole system under the condition of small number of system functional modules.
Meanwhile, the portable signal acquisition control equipment in the current market is mainly a light module based on a USB or lightning interface, has the characteristics of hot plug, plug and play and the like, can be used by being matched with a commercial notebook computer, and has high cost performance and good portability. However, such devices are often only suitable for single-device operation, and even if the devices have synchronous triggering capability, only have simple reference clocks and triggering interfaces, complex timing triggering of multiple devices cannot be completed, and the synchronous precision between the devices is difficult to reach the level below microseconds, so that the requirement of high-precision synchronous timing triggering of users cannot be met.
In summary, the existing signal acquisition control equipment constructed based on the bus instrument system generally has the problems of poor expansion flexibility, low synchronization precision between equipment, weak timing triggering capability and the like, so that the signal acquisition control equipment capable of simultaneously meeting the characteristics of light and portable appearance, good equipment expansibility, strong timing triggering capability, high synchronization precision and the like is lacking in the current market.
Disclosure of Invention
The invention aims to provide a flexibly-connectable trigger connector, signal acquisition control equipment and a signal acquisition control system, which are used for solving the problems of poor expansion flexibility, low equipment synchronization precision, weak timing triggering capability and the like commonly existing in the conventional signal acquisition control equipment constructed based on a bus instrument system, so as to provide a trigger connector which can enable the equipment to simultaneously meet the characteristics of light and portable appearance, good equipment expansibility, strong timing triggering capability, high synchronization precision and the like, and further realize the characteristics of portability, low cost, multiple functions, expandability, precise synchronization triggering and the like for the signal acquisition control equipment and the system with the trigger connector.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, a trigger connector capable of being flexibly connected is provided, which comprises a star trigger interface and a cascade trigger interface, wherein the star trigger interface comprises a trigger interface circuit, and the cascade trigger interface comprises an uplink cascade trigger interface circuit and a downlink cascade trigger interface circuit;
the trigger interface circuit is used for connecting a first interface IP unit of an identical device FPGA module and providing a DIO channel so as to be provided with M TRIG channels for carrying out trigger signal interaction with the identical device FPGA module, and is also used for connecting external devices so as to be convenient for the external devices to interact with the identical device FPGA module through any TRIG channel for a first trigger signal, wherein the identical device FPGA module refers to an FPGA module positioned in the device of the trigger connector, and M represents a positive integer;
the uplink cascade trigger interface circuit is used for connecting a second interface IP unit of the same-equipment FPGA module and also providing a DIO channel so as to be provided with N uplink TRIG channels for carrying out trigger signal interaction with the same-equipment FPGA module, and is also used for connecting uplink external equipment positioned in the cascade uplink direction so as to be convenient for the uplink external equipment to interact with the same-equipment FPGA module through any uplink TRIG channel for a second trigger signal, wherein N represents a positive integer;
The downlink cascade trigger interface circuit is used for connecting the second interface IP unit so as to be provided with N downlink TRIG channels for carrying out trigger signal interaction with the same-equipment FPGA module, and is also used for connecting downlink external equipment positioned in a cascade downlink direction so that the downlink external equipment can interact with the same-equipment FPGA module through any one downlink TRIG channel for a third trigger signal.
Based on the above summary of the invention, a multifunctional trigger interface scheme based on FPGA is provided, that is, the multifunctional trigger interface scheme includes a trigger interface circuit, an uplink cascade trigger interface circuit and a downlink cascade trigger interface circuit, where the trigger interface circuit is used for connecting a first interface IP unit of the same device FPGA module and providing a DIO channel and connecting an external trigger signal distribution device, and the uplink/downlink cascade trigger interface circuit is used for connecting a second interface IP unit of the same device FPGA module and also providing a DIO channel and connecting an uplink/downlink external device located in a cascade uplink/downlink direction, so that the device and other devices with trigger connectors and the external trigger signal distribution device can form any one of a daisy chain topology structure and a star topology structure or any combination thereof, thereby achieving the purpose of cascade uplink/downlink transmission of trigger signals and/or simultaneous transmission of star trigger signals with higher synchronization precision.
In one possible design, the N uplink TRIG channels are in one-to-one correspondence with and connected to the N downlink TRIG channels, so that after any one uplink/downlink TRIG channel receives a trigger signal from an uplink/downlink external device or the FPGA module of the same device, the trigger signal is further transmitted to another external device located in the cascade downlink/uplink direction through the corresponding downlink/uplink TRIG channel.
In one possible design, the star trigger interface further includes a clock signal interface circuit;
the clock signal interface circuit is used for respectively connecting an external clock signal distribution device and a clock signal generation module of the affiliated device and connected with the first interface IP unit, and is also used for transmitting the external clock signal to the clock signal generation module after receiving the external clock signal from the external clock signal distribution device, so that the clock signal generation module generates a required clock signal of the affiliated device based on a phase-locked loop and/or a direct digital synthesis mechanism and transmits the required clock signal to the FPGA module of the affiliated device.
In one possible design, the external clock signal includes a reference clock signal for causing the clock signal generation module to generate a normal clock signal required by the device and phase-locked to the reference clock signal and/or a GPS pulse-per-second signal for causing the clock signal generation module to generate an accurate clock signal required by the device and phase-locked to the GPS pulse-per-second signal.
In one possible design, the cascade trigger interface further includes an uplink data transmission interface circuit and a downlink data transmission interface circuit;
the uplink data transmission interface circuit is used for connecting a third interface IP unit of the same-equipment FPGA module and also providing DIO channels so as to be provided with K uplink DIO channels for carrying out digital signal interaction with the same-equipment FPGA module, and is also used for connecting the uplink external equipment so as to realize data communication interconnection between the same-equipment FPGA module and the uplink external equipment through the K uplink DIO channels, wherein K represents a positive integer;
the downlink data transmission interface circuit is used for connecting the third interface IP unit so as to have K downlink DIO channels for carrying out digital signal interaction with the same-equipment FPGA module, and is also used for connecting the downlink external equipment so as to realize the data communication interconnection between the same-equipment FPGA module and the downlink external equipment through the K downlink DIO channels.
In one possible design, the uplink cascade trigger interface circuit and the uplink data transmission interface circuit employ Nano-Pitch connectors, and the downlink cascade trigger interface circuit and the downlink data transmission interface circuit also employ Nano-Pitch connectors.
In a second aspect, a signal acquisition control device is provided, including a signal acquisition control function module, an FPGA module, and a trigger connector as described in the first aspect or any of the possible designs of the first aspect;
the signal acquisition control function module is connected with the FPGA module, a first interface IP unit of the FPGA module, which provides a DIO channel, is connected with the trigger interface circuit of the trigger connector, and a second interface IP unit of the FPGA module, which provides a DIO channel, is respectively connected with the uplink cascade trigger interface circuit and the downlink cascade trigger interface circuit of the trigger connector.
In a third aspect, a signal acquisition control system is provided, including a trigger signal generating device and X signal acquisition control devices as described in the second aspect, where X represents a positive integer greater than or equal to 2;
the trigger signal output port of the trigger signal generating device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of the X-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the X-th signal acquisition control device;
Or the trigger signal output port of the trigger signal generating device is respectively connected with the uplink/downlink cascade trigger interface circuit or the trigger interface circuit of the trigger connector of each signal acquisition control device through cables with equal lengths.
In a fourth aspect, another signal acquisition control system is provided, including a trigger signal generating device, a trigger signal distributing device, and X signal acquisition control devices as described in the second aspect, where X represents a positive integer greater than or equal to 2;
the trigger signal output port of the trigger signal generating device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of a Y-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the Y-1 signal acquisition control device, wherein Y represents a positive integer less than or equal to X;
The trigger signal output ports of the trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through cables with equal length, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X.
In a fifth aspect, there is also provided another signal acquisition control system, including a first trigger signal distribution device, a second trigger signal distribution device, and X signal acquisition control devices according to the second aspect, where X represents a positive integer greater than or equal to 1;
the trigger signal output port of the first trigger signal distribution device is respectively connected with the uplink/downlink cascade trigger interface circuits of the trigger connectors of all the Y signal acquisition control devices through first equal-length cables, wherein Y represents a positive integer less than or equal to X;
the trigger signal output ports of the second trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through second equal-length cables, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X.
The beneficial effect of above-mentioned scheme:
(1) The invention creatively provides a multifunctional trigger interface scheme based on an FPGA, namely, the multifunctional trigger interface scheme comprises a trigger interface circuit, an uplink cascade trigger interface circuit and a downlink cascade trigger interface circuit, wherein the trigger interface circuit is used for connecting a first interface IP unit which is connected with an FPGA module of the same equipment and provides a DIO channel and connecting external trigger signal distribution equipment, the uplink/downlink cascade trigger interface circuit is used for connecting a second interface IP unit which is connected with the FPGA module of the same equipment and also provides the DIO channel and connecting uplink/downlink external equipment which is positioned in the cascade uplink/downlink direction, so that the device and other equipment with the trigger connector and the external trigger signal distribution equipment can form any one of a daisy chain topological structure and a star-shaped topological structure or any combination of the two, and further the purposes of cascading uplink/downlink transmission of trigger signals and/or synchronous transmission of synchronous signals with higher precision are realized.
(2) In the aspect of light portability: the starting weight of a chassis and a controller of a traditional PXIe, AXIe, VPX bus system with various timing triggering functions is over 10kg, and peripheral equipment required by man-machine interaction such as a display and a keyboard and mouse is not included. Even an all-in-one machine comprising a display screen and a keyboard and mouse, which is specially designed for portability, has difficulty in reducing the weight of the system to below 10 kg. The volume of these systems is also relatively large, almost at least one desktop host. The invention realizes the synchronous bus function in the special PXIe, AXIe, VPX bus type instrument system back plate through a group of dual-port cascade trigger interfaces and one star trigger interface, replaces the traditional bus back plate with cascade and star connection cables, and helps an integrated system of a plurality of signal acquisition and control equipment to get rid of the dependence on a special case by simple cable connection, thereby greatly reducing the system volume and the system weight.
(3) In the aspect of multifunction: the invention connects a plurality of signal acquisition and control devices in cascade in a daisy chain topology mode through a group of dual-port cascade trigger interfaces, and receives and connects transmission synchronous trigger signals from external devices based on the cascade interfaces. The cascade trigger interface simultaneously comprises a DIO interface capable of transmitting digital signals, so that the cascade connection of a plurality of signal acquisition and control devices can simultaneously transmit digital information suitable for various application requirements, and the functionality of the trigger interface is enriched. The invention also comprises a star trigger interface, which meets the requirement of the application requiring high-precision synchronous triggering.
(4) In terms of low cost: the invention adopts commercial products and technologies which are already shipped on a large scale in the market, including standard Nano-Pitch interfaces, nano-Pitch cables, FPGA and the like, and the cost is greatly lower than that of a customized system chassis, a bus backboard and a chassis power supply. The equipment using the multifunctional synchronous triggering interface can adopt a portable design, has a simpler packaging structure and a heat dissipation design, greatly reduces the design, process and production requirements, and further reduces the construction cost of the equipment and the system. The design of the present invention can help reduce system construction costs by at most 50% especially with a small number of devices in the system.
(5) In terms of flexibility: the multifunctional synchronous triggering interface has two connection modes: a cascade connection mode and a star connection mode. The cascade connection mode has the characteristic of simple form, can be connected through the daisy chain type gradual expansion, so that all connected devices form a unified trigger signal transmission mechanism, only one cable is needed for the connection of external devices for sending and receiving the trigger signals, and the number of the devices can be conveniently expanded at the later stage. The star connection mode can utilize the equal-length cable to avoid different transmission delays from the trigger signal to different devices, and meets the requirement of high-precision synchronous trigger application.
(6) In terms of short development cycle: because of the multifunction and flexibility, the application can be used as a standardized timing trigger interface of different signal acquisition and control equipment, so that a developer can reuse software and hardware designs of timing synchronization functions for new module research and development, thereby mainly focusing on the software and hardware design development of signal acquisition and control functional circuits and finally helping to shorten the overall development period of the equipment.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a specific structure of a trigger connector capable of being flexibly connected and a signal acquisition control device with the trigger connector according to an embodiment of the present application.
Fig. 2 is a circuit diagram of a cascade trigger interface in a trigger connector according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a first signal acquisition control system according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a second signal acquisition control system according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a third signal acquisition control system according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the present application will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present application, but is not intended to limit the present application.
It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, a first object may be referred to as a second object, and similarly a second object may be referred to as a first object, without departing from the scope of example embodiments of the application.
It should be understood that for the term "and/or" that may appear herein, it is merely one association relationship that describes an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: three cases of A alone, B alone or both A and B exist; as another example, A, B and/or C, can represent the presence of any one of A, B and C or any combination thereof; for the term "/and" that may appear herein, which is descriptive of another associative object relationship, it means that there may be two relationships, e.g., a/and B, it may be expressed that: the two cases of A and B exist independently or simultaneously; in addition, for the character "/" that may appear herein, it is generally indicated that the context associated object is an "or" relationship.
Example 1
As shown in fig. 1, the flexibly connectable trigger connector provided in this embodiment includes, but is not limited to, a star trigger interface and a cascade trigger interface, where the star trigger interface includes, but is not limited to, a trigger interface circuit (i.e. the TRIG in fig. 1), and the cascade trigger interface includes, but is not limited to, an uplink cascade trigger interface circuit (i.e. the TRIG in fig. 1) and a downlink cascade trigger interface circuit (i.e. the TRIG in fig. 1).
The Trigger interface circuit is used for connecting a first interface IP unit (i.e., DIO1 in fig. 1) of a Field Programmable Gate Array (FPGA) module of the same device and providing DIO channels, so as to have M TRIG (Trigger) channels for performing Trigger signal interaction with the FPGA module of the same device, and is also used for connecting an external device so as to enable the external device to interact with the FPGA module of the same device through any one TRIG channel for a first Trigger signal, where the FPGA module of the same device refers to an FPGA module located in an affiliated device of the Trigger connector, and M represents a positive integer. As shown in fig. 1, the device is exemplified as a signal acquisition control device, and the FPGA module of the same device is the FPGA module in the signal acquisition control device. By the configuration of the trigger interface circuit, the affiliated device, other devices with the trigger connector and the external trigger signal distribution device (namely, the external device) can form a star topology structure, and the external trigger signal distribution device can be connected with the trigger interface circuits of the affiliated device and the other devices through cables with equal lengths respectively, so that the purpose of simultaneously transmitting a star trigger signal (namely, the first trigger signal) with higher synchronous precision is realized. In addition, the device may also provide a trigger signal as a trigger signal distribution device to the external device.
The FPGA module is used for specifically responsible for signal acquisition, control and data communication processing of the equipment; for example, in the signal acquisition control apparatus, the following specific functions of signal acquisition and control may be realized by connection with a signal acquisition control function module (the circuit structure of which varies from one specific task to another, which is not the innovative point of the present embodiment): providing the trigger signal and the clock signal required by the operation for the signal acquisition control function module based on the trigger signal and the clock signal from the external equipment so that a plurality of signal acquisition control equipment connected in cascade or star can synchronously work through a clock and a trigger mechanism, for example, synchronous receiving or transmitting of the coherent signal is realized; triggering internal processing sequential logic or specific sequential logic processing flow based on external event so as to control the signal acquisition control function module to work according to the set sequential logic, thereby achieving the purposes of signal acquisition and control; providing a digital signal mutual transmission function between the signal acquisition control function module and the cascaded signal acquisition control equipment for the signal acquisition control function module; etc. The FPGA module is specifically formed by conventionally constructing an FPGA chip and peripheral circuits thereof, and can be specifically connected with a specific interface circuit by adopting an IP core (namely an interface IP unit) of a PCIE bus protocol (a soft core and a hard core of the PCIE bus protocol are provided by mainstream FPGA manufacturers), wherein the PCIE bus protocol preferably adopts a PCIE Gen3 x1 standard bus protocol or a PCIE Gen3 x4 standard bus protocol. Because the FPGA device belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array and has high-speed data throughput capacity, high-speed logic and time sequence control capacity, the FPGA module can be suitable for realizing functions such as high-speed serial bus, real-time signal processing, time sequence logic, trigger timing and the like. Meanwhile, a large number of DIO channels are usually arranged on the current high-performance FPGA chip, and can be used for receiving and transmitting digital signals independently and achieving channel receiving and updating frequencies of hundreds of MHz, so that the channels can be used for receiving and transmitting digital communication signals and trigger signals. In addition, as shown in fig. 1, the FPGA module is further connected with an on-board FLASH module (i.e., FLASH in fig. 1), so as to be used for storing the FPGA firmware program, and when the device is powered on, the FPGA firmware program is loaded and then works according to a predetermined mode.
The uplink cascade trigger interface circuit is used for connecting a second interface IP unit (i.e. DIO2 in fig. 1) of the same-equipment FPGA module and also providing a DIO channel so as to have N uplink TRIG channels for performing trigger signal interaction with the same-equipment FPGA module, and is also used for connecting uplink external equipment positioned in the cascade uplink direction so as to enable the uplink external equipment to interact with the same-equipment FPGA module through any uplink TRIG channel for a second trigger signal, wherein N represents a positive integer; the downlink cascade trigger interface circuit is used for connecting the second interface IP unit so as to be provided with N downlink TRIG channels for carrying out trigger signal interaction with the same-equipment FPGA module, and is also used for connecting downlink external equipment positioned in a cascade downlink direction so that the downlink external equipment can interact with the same-equipment FPGA module through any one downlink TRIG channel for a third trigger signal.
For example, as shown in fig. 2, the uplink cascade trigger interface circuit has 6 uplink TRIG channels, which are respectively named as TRIG0, TRIG1, TRIG2, TRIG3, TRIG4 and TRIG5, and the downlink cascade trigger interface circuit has 6 downlink TRIG channels. The uplink/downlink external device may be the external trigger signal distribution device, or may be another device having the trigger connector. By the configuration of the uplink cascade trigger interface circuit and the downlink cascade trigger interface circuit, on one hand, the affiliated device, other devices with the trigger connector and the external trigger signal distribution device can form a daisy chain topology structure, and further, the purpose of uplink/downlink transmission of the trigger signal cascade can be achieved, on the other hand, the affiliated device, other devices with the trigger connector and the external trigger signal distribution device can form a star topology structure, and further, the external trigger signal distribution device can be connected with the uplink cascade trigger interface circuit of the affiliated device and the other devices through cables with equal lengths, and the purpose of simultaneously transmitting star trigger signals (namely the second trigger signals) with higher synchronous precision is achieved. Furthermore, the second trigger signal may be specifically derived from the same device FPGA module, so that the device can act as a trigger signal distribution device.
The trigger interface circuit is used for connecting a first interface IP unit which is connected with an equipment FPGA module and provides a DIO channel and connecting external trigger signal distribution equipment, the uplink/downlink cascade trigger interface circuit is used for connecting a second interface IP unit which is connected with the equipment FPGA module and also provides the DIO channel and connecting uplink/downlink external equipment which is positioned in the cascade uplink/downlink direction, so that the equipment and other equipment with the trigger connector and the external trigger signal distribution equipment can form any one of a daisy chain topological structure and a star topology structure or any combination of the two, and the purposes of transmitting the trigger signal in an uplink/downlink manner and/or simultaneously transmitting a trigger signal with higher synchronous precision are achieved.
Preferably, the N uplink TRIG channels are in one-to-one correspondence and connected with the N downlink TRIG channels, so that after any one uplink/downlink TRIG channel receives a trigger signal from an uplink/downlink external device or the FPGA module of the same device, the trigger signal is further transmitted to another external device located in the cascade downlink/uplink direction through the corresponding downlink/uplink TRIG channel. Also as shown in fig. 2, since the 6 downlink TRIG channels and the 6 uplink TRIG channels are in one-to-one correspondence and are connected, they may be respectively named as TRIG0, TRIG1, TRIG2, TRIG3, TRIG4 and TRIG5, so that the uplink TRIG channel TRIGx (x represents an integer and the value interval is [0,5 ]) and the downlink TRIG channel TRIGx may be directly transmitted to each other as a trigger signal, such as a rising edge trigger signal and a falling edge trigger signal, so that the trigger signal does not need to be transferred by the FPGA module of the same device, and delay jitter problem of the trigger signal in the cascade transmission process (that is, transmission delay of the trigger signal by the FPGA module has a maximum of 5ns, and the delay time is jittery, and if the trigger signal is directly connected one by one, the delay is very small and the delay time certainty is high).
Preferably, the star trigger interface further comprises a clock signal interface circuit (i.e. CLK in fig. 1); the clock signal interface circuit is used for respectively connecting an external clock signal distribution device and a clock signal generation module (namely a PLL in figure 1) of the affiliated device and connecting the first interface IP unit, and is also used for transmitting the external clock signal to the clock signal generation module after receiving the external clock signal from the external clock signal distribution device, so that the clock signal generation module generates a required clock signal of the affiliated device based on a phase-locked loop (Phase Locked Loop, abbreviated as a PLL, which is a negative feedback control mode using a voltage generated by phase synchronization, for detuning a voltage-controlled oscillator to generate a target frequency) and/or a direct digital synthesis (Direct Digital Synthesizer, abbreviated as a DDS, which is a digital electronic mode, which generates arbitrary waveforms and frequencies from a single or mixed frequency source) mechanism and transmits the required clock signal to the FPGA module of the same device. The external clock signal distribution device and the external trigger signal distribution device may or may not be the same device. By the configuration of the clock signal interface circuit, when the affiliated device and other devices with the trigger connector and the external clock signal distribution device form a star topology structure, the external clock signal distribution device can be respectively connected with the clock signal interface circuits of the affiliated device and the other devices through cables with equal lengths, so that the aim of simultaneously transmitting external clock signals with higher synchronous precision is fulfilled. In addition, the clock signal interface circuit may also be directly connected to the first interface IP unit, so that after receiving an external sampling clock signal from the external clock signal distribution device, the external sampling clock signal is transmitted to the FPGA module of the same device for timing of signal acquisition and processing.
Specifically, the external clock signals include, but are not limited to, a reference clock signal for causing the clock signal generating module to generate a normal clock signal required by the device and phase-locked with the reference clock signal, and/or a GPS (Global Positioning System ) second pulse signal for causing the clock signal generating module to generate an accurate clock signal required by the device and phase-locked with the GPS second pulse signal, and the like. In addition, the device can further comprise an on-board clock crystal oscillator module connected with the clock signal generating module, so that when no external clock signal is input, the on-board clock crystal oscillator module transmits a crystal oscillator signal to the clock signal generating module, the clock signal generating module can generate a required common clock signal of the device based on a phase-locked loop and/or a direct digital synthesis mechanism, and the required common clock signal is transmitted to the FPGA module of the same device.
Preferably, the cascade trigger interface further includes an uplink data transmission interface circuit (i.e. DIO uplink in fig. 1) and a downlink data transmission interface circuit (i.e. DIO downlink in fig. 1); the uplink data transmission interface circuit is used for connecting a third interface IP unit (i.e., DIO3 in fig. 1) of the same-device FPGA module and also providing DIO channels, so as to have K uplink DIO channels for performing digital signal interaction with the same-device FPGA module, and is also used for connecting the uplink external device, so as to implement data communication interconnection between the same-device FPGA module and the uplink external device through the K uplink DIO channels, where K represents a positive integer; the downlink data transmission interface circuit is used for connecting the third interface IP unit so as to have K downlink DIO channels for carrying out digital signal interaction with the same-equipment FPGA module, and is also used for connecting the downlink external equipment so as to realize the data communication interconnection between the same-equipment FPGA module and the downlink external equipment through the K downlink DIO channels. For example, as shown in fig. 2, the uplink data transmission interface circuit has 8 uplink DIO channels, named DIO01, DIO11, DIO21, DIO31, DIO41, DIO51, DIO61, and DIO71, respectively, and the downlink data transmission interface circuit has 8 downlink DIO channels, named DIO02, DIO12, DIO22, DIO32, DIO42, DIO52, DIO62, and DIO72, respectively. By the configuration of the uplink data transmission interface circuit and the downlink data transmission interface circuit, the affiliated device and other devices with the trigger connector and the external data processing device can form a daisy chain topology structure, so that the aim of uplink/downlink transmission of the digital signal cascade can be fulfilled, for example, additional information for timing synchronization trigger functions, such as additional information of enabling a switch, a target device address, a channel number and the like, is transmitted.
Specifically, the uplink cascade trigger interface circuit and the uplink data transmission interface circuit use Nano-Pitch connectors (for example, standard 42-pin connectors), and the downlink cascade trigger interface circuit and the downlink data transmission interface circuit also use Nano-Pitch connectors, so that the cascade trigger interface has compact and high-speed characteristics.
Preferably, the corresponding uplink TRIG channels and the corresponding downlink TRIG channels are connected by arranging a push-pull circuit, so that the driving property of the push-pull circuit is utilized to enhance the driving capability of the DIO channels of the FPGA to the TRIG channels, and the method is suitable for longer cascade cables and more cascade devices.
In summary, the trigger connector provided by the embodiment has the following technical effects:
(1) The embodiment provides a multifunctional trigger interface scheme based on an FPGA, namely, the multifunctional trigger interface scheme comprises a trigger interface circuit, an uplink cascade trigger interface circuit and a downlink cascade trigger interface circuit, wherein the trigger interface circuit is used for connecting a first interface IP unit which is connected with an equipment FPGA module and provides a DIO channel and connecting external trigger signal distribution equipment, the uplink/downlink cascade trigger interface circuit is used for connecting a second interface IP unit which is connected with the equipment FPGA module and also provides the DIO channel and connecting uplink/downlink external equipment which is positioned in the cascade uplink/downlink direction, so that the equipment and other equipment with the trigger connector and the external trigger signal distribution equipment can form any one or any combination of a daisy chain topological structure and a star-shaped topological structure, and further the purposes of enabling the equipment to be light and handy in appearance, good in equipment expansibility, strong in timing trigger capability, high in synchronous precision and the like, and the characteristics of the existing star-shaped trigger signal simultaneously transmitting synchronous precision, and the equipment based on the bus type trigger connector, low-expansion of the existing trigger signal acquisition equipment, low-expansion capability, low-expansion of the existing trigger system, low-precision trigger signal acquisition equipment, low-expansion and practical trigger system, and the like can be realized.
Example two
The embodiment provides a novel signal acquisition control device based on the trigger connector of the embodiment one, namely as shown in fig. 1, and the novel signal acquisition control device comprises a signal acquisition control function module, an FPGA module and the trigger connector of the embodiment one; the signal acquisition control function module is connected with the FPGA module, a first interface IP unit of the FPGA module, which provides a DIO channel, is connected with the trigger interface circuit of the trigger connector, and a second interface IP unit of the FPGA module, which provides a DIO channel, is respectively connected with the uplink cascade trigger interface circuit and the downlink cascade trigger interface circuit of the trigger connector.
The technical details and technical effects of the foregoing devices provided in this embodiment may be referred to the trigger connector described in the first embodiment, and will not be described herein.
Example III
The second embodiment provides a novel signal acquisition control system flexibly connected with the signal acquisition control device based on the second embodiment, that is, the novel signal acquisition control system comprises a trigger signal generating device and X signal acquisition control devices according to the second embodiment, wherein X represents a positive integer greater than or equal to 2; the trigger signal output port of the trigger signal generating device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of the X-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the X-th signal acquisition control device. As shown in fig. 3, X is exemplified by 3, and the purpose of triggering signal cascade up/down transfer can be achieved by forming a daisy chain topology. In addition, in order to achieve the purpose of simultaneously transmitting star trigger signals with higher synchronization precision by forming a star topology, the trigger signal output port of the trigger signal generating device may also be connected with an uplink/downlink cascade trigger interface circuit or a trigger interface circuit of the trigger connector of each signal acquisition control device through an equal-length cable.
The technical details and technical effects of the foregoing devices provided in this embodiment may be referred to the trigger connector described in the first embodiment, and will not be described herein.
Example IV
The second signal acquisition control system is flexibly connected based on the signal acquisition control device of the second embodiment and is novel, namely, the signal acquisition control system comprises a trigger signal generating device, a trigger signal distributing device and X signal acquisition control devices as described in the second embodiment, wherein X represents a positive integer greater than or equal to 2; the trigger signal output port of the trigger signal generating device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of a Y-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the Y-1 signal acquisition control device, wherein Y represents a positive integer less than or equal to X; the trigger signal output ports of the trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through cables with equal length, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X. As shown in fig. 4, X, Y and Z are respectively exemplified by 3, and the purposes of cascading up/down transmission of trigger signals and simultaneously transmitting star trigger signals with higher synchronization accuracy can be achieved by forming a daisy chain topology structure and a star topology structure.
The technical details and technical effects of the foregoing devices provided in this embodiment may be referred to the trigger connector described in the first embodiment, and will not be described herein.
Example five
The second embodiment provides a third signal acquisition control system flexibly connected based on the signal acquisition control device according to the second embodiment, that is, the signal acquisition control system comprises a first trigger signal distribution device, a second trigger signal distribution device and X signal acquisition control devices according to the second embodiment, wherein X represents a positive integer greater than or equal to 1; the trigger signal output port of the first trigger signal distribution device is respectively connected with the uplink/downlink cascade trigger interface circuits of the trigger connectors of all the Y signal acquisition control devices through first equal-length cables, wherein Y represents a positive integer less than or equal to X; the trigger signal output ports of the second trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through second equal-length cables, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X. As shown in fig. 5, X, Y and Z are respectively exemplified by 3, and the purpose of simultaneously transmitting different star trigger signals with higher synchronization accuracy can be achieved by forming two star topologies.
The technical details and technical effects of the foregoing devices provided in this embodiment may be referred to the trigger connector described in the first embodiment, and will not be described herein.
Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The trigger connector capable of being flexibly connected is characterized by comprising a star trigger interface and a cascade trigger interface, wherein the star trigger interface comprises a trigger interface circuit, and the cascade trigger interface comprises an uplink cascade trigger interface circuit and a downlink cascade trigger interface circuit;
the trigger interface circuit is used for connecting a first interface IP unit of an identical device FPGA module and providing a DIO channel so as to be provided with M TRIG channels for carrying out trigger signal interaction with the identical device FPGA module, and is also used for connecting external devices so as to be convenient for the external devices to interact with the identical device FPGA module through any TRIG channel for a first trigger signal, wherein the identical device FPGA module refers to an FPGA module positioned in the device of the trigger connector, and M represents a positive integer;
The uplink cascade trigger interface circuit is used for connecting a second interface IP unit of the same-equipment FPGA module and also providing a DIO channel so as to be provided with N uplink TRIG channels for carrying out trigger signal interaction with the same-equipment FPGA module, and is also used for connecting uplink external equipment positioned in the cascade uplink direction so as to be convenient for the uplink external equipment to interact with the same-equipment FPGA module through any uplink TRIG channel for a second trigger signal, wherein N represents a positive integer;
the downlink cascade trigger interface circuit is used for connecting the second interface IP unit so as to be provided with N downlink TRIG channels for carrying out trigger signal interaction with the same-equipment FPGA module, and is also used for connecting downlink external equipment positioned in a cascade downlink direction so that the downlink external equipment can interact with the same-equipment FPGA module through any one downlink TRIG channel for a third trigger signal.
2. The trigger connector of claim 1, wherein N upstream TRIG channels are in one-to-one correspondence with and connected to N downstream TRIG channels, so that after any one upstream/downstream TRIG channel receives a trigger signal from an upstream/downstream external device or the same-device FPGA module, the trigger signal is further transmitted to another external device located in a cascade downstream/upstream direction through a corresponding downstream/upstream TRIG channel.
3. The trigger connector of claim 1, wherein the star trigger interface further comprises a clock signal interface circuit;
the clock signal interface circuit is used for respectively connecting an external clock signal distribution device and a clock signal generation module of the affiliated device and connected with the first interface IP unit, and is also used for transmitting the external clock signal to the clock signal generation module after receiving the external clock signal from the external clock signal distribution device, so that the clock signal generation module generates a required clock signal of the affiliated device based on a phase-locked loop and/or a direct digital synthesis mechanism and transmits the required clock signal to the FPGA module of the affiliated device.
4. The trigger connector of claim 3, wherein the external clock signal comprises a reference clock signal for causing the clock signal generation module to generate a normal clock signal required by the device and phase-locked to the reference clock signal and/or a GPS pulse-per-second signal for causing the clock signal generation module to generate an accurate clock signal required by the device and phase-locked to the GPS pulse-per-second signal.
5. The trigger connector of claim 1, wherein the cascading trigger interface further comprises an upstream data transmission interface circuit and a downstream data transmission interface circuit;
the uplink data transmission interface circuit is used for connecting a third interface IP unit of the same-equipment FPGA module and also providing DIO channels so as to be provided with K uplink DIO channels for carrying out digital signal interaction with the same-equipment FPGA module, and is also used for connecting the uplink external equipment so as to realize data communication interconnection between the same-equipment FPGA module and the uplink external equipment through the K uplink DIO channels, wherein K represents a positive integer;
the downlink data transmission interface circuit is used for connecting the third interface IP unit so as to have K downlink DIO channels for carrying out digital signal interaction with the same-equipment FPGA module, and is also used for connecting the downlink external equipment so as to realize the data communication interconnection between the same-equipment FPGA module and the downlink external equipment through the K downlink DIO channels.
6. The trigger connector of claim 5, wherein the upstream cascade trigger interface circuit and the upstream data transmission interface circuit employ Nano-Pitch connectors, and the downstream cascade trigger interface circuit and the downstream data transmission interface circuit also employ Nano-Pitch connectors.
7. A signal acquisition control device comprising a signal acquisition control function module, an FPGA module, and a trigger connector according to any one of claims 1 to 6;
the signal acquisition control function module is connected with the FPGA module, a first interface IP unit of the FPGA module, which provides a DIO channel, is connected with the trigger interface circuit of the trigger connector, and a second interface IP unit of the FPGA module, which provides a DIO channel, is respectively connected with the uplink cascade trigger interface circuit and the downlink cascade trigger interface circuit of the trigger connector.
8. A signal acquisition control system comprising a trigger signal generating device and X signal acquisition control devices as claimed in claim 7, wherein X represents a positive integer greater than or equal to 2;
the trigger signal output port of the trigger signal generating device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of the X-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the X-th signal acquisition control device;
Or the trigger signal output port of the trigger signal generating device is respectively connected with the uplink/downlink cascade trigger interface circuit or the trigger interface circuit of the trigger connector of each signal acquisition control device through cables with equal lengths.
9. A signal acquisition control system, comprising a trigger signal generating device, a trigger signal distributing device, and X signal acquisition control devices according to claim 7, wherein X represents a positive integer greater than or equal to 2;
the trigger signal output port of the trigger signal generating device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a first signal acquisition control device, the downlink/uplink cascade trigger interface circuit of the trigger connector of the first signal acquisition control device is connected with an uplink/downlink cascade trigger interface circuit of a trigger connector of a second signal acquisition control device, and so on until the downlink/uplink cascade trigger interface circuit of the trigger connector of a Y-1 signal acquisition control device is connected with the uplink/downlink cascade trigger interface circuit of the trigger connector of the Y-1 signal acquisition control device, wherein Y represents a positive integer less than or equal to X;
the trigger signal output ports of the trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through cables with equal length, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X.
10. A signal acquisition control system comprising a first trigger signal distribution device, a second trigger signal distribution device, and X signal acquisition control devices according to claim 7, wherein X represents a positive integer greater than or equal to 1;
the trigger signal output port of the first trigger signal distribution device is respectively connected with the uplink/downlink cascade trigger interface circuits of the trigger connectors of all the Y signal acquisition control devices through first equal-length cables, wherein Y represents a positive integer less than or equal to X;
the trigger signal output ports of the second trigger signal distribution equipment are respectively connected with trigger interface circuits of trigger connectors of all signal acquisition control equipment in Z signal acquisition control equipment through second equal-length cables, wherein Z represents a positive integer less than or equal to X, and Y+Z is greater than or equal to X.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472782A (en) * | 2013-08-30 | 2013-12-25 | 华中科技大学 | Distributed time sequence trigger control system |
| CN111611114A (en) * | 2020-03-30 | 2020-09-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Integrated avionics PHM system |
| CN112305511A (en) * | 2020-09-27 | 2021-02-02 | 北京无线电测量研究所 | Radar receiver digital baseband signal recording and analyzing system and method |
| CN115509987A (en) * | 2022-09-16 | 2022-12-23 | 哈尔滨工业大学 | Interface module, trigger unit, high-precision trigger board card based on MiniVPX architecture and trigger method |
| CN115599010A (en) * | 2022-08-12 | 2023-01-13 | 北京中海技创科技发展有限公司（Cn） | Multi-channel embedded synchronous acquisition system and method thereof |
| CN116402148A (en) * | 2023-04-14 | 2023-07-07 | 山东云海国创云计算装备产业创新中心有限公司 | Quantum measurement and control fast feedback device, method, equipment and storage medium |
| CN116647247A (en) * | 2022-11-04 | 2023-08-25 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN116737624A (en) * | 2023-06-06 | 2023-09-12 | 成都立思方信息技术有限公司 | High-performance data access device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004057410B4 (en) * | 2004-11-26 | 2015-11-12 | Robert Bosch Gmbh | Arrangement with an interface module and interface module |
| FR2996084B1 (en) * | 2012-09-21 | 2014-09-26 | Eurocopter France | CHAIN INFORMATION EXCHANGE SYSTEM COMPRISING MULTIPLE EQUIPMENT CONNECTED BY DIGITAL DIGITAL BUSES |
-
2023
- 2023-09-19 CN CN202311205884.XA patent/CN116955258B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472782A (en) * | 2013-08-30 | 2013-12-25 | 华中科技大学 | Distributed time sequence trigger control system |
| CN111611114A (en) * | 2020-03-30 | 2020-09-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Integrated avionics PHM system |
| CN112305511A (en) * | 2020-09-27 | 2021-02-02 | 北京无线电测量研究所 | Radar receiver digital baseband signal recording and analyzing system and method |
| CN115599010A (en) * | 2022-08-12 | 2023-01-13 | 北京中海技创科技发展有限公司（Cn） | Multi-channel embedded synchronous acquisition system and method thereof |
| CN115509987A (en) * | 2022-09-16 | 2022-12-23 | 哈尔滨工业大学 | Interface module, trigger unit, high-precision trigger board card based on MiniVPX architecture and trigger method |
| CN116647247A (en) * | 2022-11-04 | 2023-08-25 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN116680220A (en) * | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system |
| CN116402148A (en) * | 2023-04-14 | 2023-07-07 | 山东云海国创云计算装备产业创新中心有限公司 | Quantum measurement and control fast feedback device, method, equipment and storage medium |
| CN116737624A (en) * | 2023-06-06 | 2023-09-12 | 成都立思方信息技术有限公司 | High-performance data access device |
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