CN115599010A

CN115599010A - Multi-channel embedded synchronous acquisition system and method thereof

Info

Publication number: CN115599010A
Application number: CN202210965484.8A
Authority: CN
Inventors: 史钊亮; 李远照; 沈继功
Original assignee: Beijing In Shanghai Technology Innovation Technology Development Co ltd
Current assignee: Beijing In Shanghai Technology Innovation Technology Development Co ltd
Priority date: 2022-08-12
Filing date: 2022-08-12
Publication date: 2023-01-13
Anticipated expiration: 2042-08-12
Also published as: CN115599010B

Abstract

The invention belongs to the technical field of data acquisition and processing, and discloses a multi-channel embedded synchronous acquisition system and a method thereof. The acquisition system consists of three parts, namely a data acquisition unit, a main control unit and a connecting back plate. The acquisition method comprises the following steps: an Ethernet communication step, which is used for realizing data interaction between the upper computer and the lower computer; user parameter input step, realizing A/D collection and communication mode parameter setting; a data graph drawing module step, which presents the A/D data to a user in a graph mode so as to be convenient for visually observing the collected data; a data calculation step, namely analyzing and calculating the A/D data; and the human-computer interface realizes the functions of parameter setting and data display. The invention has the advantages of light and convenient structure, expandable acquisition channel, grouping use by adopting the channel, realization of IEPE sensor interface, realization of distributed synchronous acquisition and convenience for networking cross-platform application by adopting the Ethernet interface.

Description

Multi-channel embedded synchronous acquisition system and method thereof

Technical Field

The invention relates to the technical field of data acquisition and processing, in particular to a multi-channel embedded synchronous acquisition system and a method thereof.

Background

With the development of modern underwater acoustic signal processing technology and the continuous improvement of sonar performance, the hydrophone scale of underwater signal processing is larger and larger, the number of array elements is more and more, and even thousands of array elements are required to be synchronously acquired. This requires the use of data acquisition equipment, primarily a data acquisition card.

The current data acquisition cards are mainly classified into a multiplexing scanning type acquisition card and a synchronous data acquisition card according to the working principle. The multiplexing scanning acquisition card realizes multi-channel data acquisition by switching channels through a multiplexer and multiplexing an A/D converter in a time-sharing manner, and has the defects of low sampling rate and incapability of realizing synchronous acquisition. The structure of the synchronous data acquisition card system is shown in fig. 1, each acquisition channel independently uses one A/D converter, and a plurality of A/D converters work simultaneously to realize data acquisition, so that higher sampling rate can be realized, and multi-channel synchronous acquisition can be realized through synchronous signals. The disadvantages are the small number of channels and the high power consumption. For example, PXI-6115 has 4 AI lanes (12 bits, 10 MS/s/ch), 2 AO lanes, and 8 DIO lanes. PXIe-6378 and PXIe-6124.PXIe-6378 has 16 paths of AI (16 bits, 3.57 MS/s), 4 paths of AO and 48 paths of DIO; PXIe-6124 has 4-channel AI (16 bits, 4 MS/s), 2-channel AO, 24-channel DIO.

In the recent years, various data acquisition cards specially used for sound and vibration measurement appear at home and abroad, for example, PXI-4472 of NI can realize synchronous acquisition of 8-channel sound and vibration signals. And system cascading is supported to achieve synchronous acquisition of more channels.

Therefore, the existing domestic and foreign synchronous data acquisition equipment has the defects of small number of acquisition channels, large volume and the like, and cannot meet the requirement of acquiring the underwater acoustic array data with more and more channels. Therefore, the development of the multi-channel embedded synchronous acquisition module is of great significance.

Disclosure of Invention

The present invention provides a multi-channel embedded synchronous acquisition system, which is used for solving the above technical problems in the prior art.

In order to achieve the purpose, the invention discloses a multi-channel embedded synchronous acquisition system, which consists of three parts, namely a data acquisition unit, a main control unit and a connecting back plate, wherein the data acquisition unit comprises an Ethernet communication module, an analog data acquisition module and an IEPE driving module; the main control unit comprises a switch module, 6 gigabit network interface modules, a power management module, a synchronous signal module and a reference clock module; the connection back plate is mainly used for physical connection of the data acquisition unit and the main control unit;

the multi-channel embedded synchronous acquisition system is connected with an upper computer through a network switch of a main control unit to realize the communication connection between the upper computer and each data acquisition unit; the analog signals of the underwater acoustic array are sequentially connected to the analog data acquisition interfaces of the data acquisition units; the PPS synchronous signal of the external GNSS is connected to a trigger/synchronous input interface of the main control unit; the host computer writes in parameters of the sampling rate, the sampling channel and the reference voltage, and starts the A/D acquisition module, and the data acquisition unit sends acquired data to the host computer through the switch of the main control unit.

Further, the data acquisition unit realizes 32-path differential signal parallel acquisition, and adopts an ADC + FPGA architecture and utilizes a module design idea to design the data acquisition unit, wherein channels 0-31 are mutually independent; the data acquisition unit comprises 32 IEPE constant current source modules, 32 signal conditioning modules, a reference voltage module, a clock module, a DDR memory module, a gigabit Ethernet module and a synchronization and PPS signal module.

Further, the IEPE constant current source module provides a 4mA current source for the IEPE sensor, and when the external sensor is the IEPE, the IEPE constant current source module can be directly used simply and reliably;

the signal conditioning module conditions the input analog signal to a proper range and inputs the analog signal to the A/D converter for sampling, and simultaneously improves the input impedance of the interface;

the reference voltage module provides voltage reference for the A/D converter and signal conditioning, and switches the signal input range by switching different reference voltages;

the clock module provides a basic clock for system operation;

the DDR storage module is used as a data cache of the A/D acquisition module;

the Ethernet module is used as a data acquisition unit and an upper computer communication interface, realizes communication with the upper computer through Ethernet, acquires control commands such as sampling rate setting, buffer area emptying, PPS signal validity, acquisition start, acquisition end and the like in a channel grouping mode, and sends acquired data in real time;

the synchronous signal and PPS signal module is used for receiving an external trigger/synchronous signal, conditioning the external trigger/synchronous signal, and then connecting the conditioned external trigger/synchronous signal to a trigger/synchronous signal interface of a data acquisition unit, so that a synchronous data acquisition function based on the external trigger/synchronous signal is realized, and the connection and system cascade of the data acquisition unit and the external synchronous/trigger signal are realized.

Furthermore, the multi-channel embedded synchronous acquisition system is cascaded with 4 data acquisition units in total to realize the synchronous acquisition of 128-channel differential analog signals; the multi-channel embedded synchronous acquisition system can also expand synchronous acquisition of more channels.

Furthermore, the switch module in the main control unit, as a core of the main control unit, is used for realizing ethernet connection and data communication between 4 data acquisition units and external computing; the 6 kilomega network interfaces are respectively connected with the data acquisition module and an external computer;

the power supply management module is used for managing an external power supply to provide a safe, stable and reliable power supply for the system;

the synchronous signal module realizes PPS signal input and conditioning of an external GNSS and synchronously outputs conditioned signals to each data acquisition unit to realize synchronous acquisition;

the reference clock module generates a reference clock, and each data acquisition unit takes the reference clock as a reference to improve the synchronous acquisition performance of the system.

The invention also discloses a method for adopting the multi-channel embedded synchronous acquisition system, and the multi-channel embedded synchronous acquisition system realizes the following steps through an upper computer:

data storage management step, realizing management functions of A/D such as storage, export, deletion and the like;

an Ethernet communication step, which is used for realizing data interaction between the upper computer and the lower computer;

user parameter input step, realizing A/D collection and communication mode parameter setting;

a data graph drawing module step, which presents the A/D data to a user in a graph mode, so that the acquired data can be observed visually;

a data calculation step, namely analyzing and calculating the A/D data;

and the human-computer interface realizes the functions of parameter setting and data display.

Further, the following steps are realized through a data acquisition unit:

a parameter setting step, namely acquiring user parameters through Ethernet, and setting parameters such as sampling rate, acquisition channel, triggering, start/stop signal parameters of the data acquisition step and reporting address and quantity parameters of the data reporting step;

a data acquisition step, namely controlling an ADC (analog to digital converter) to acquire analog data according to parameters such as a sampling rate, an acquisition channel, a trigger signal and a start/stop signal set by a user, and putting the acquired data into a DDR (double data rate);

and a data reporting step, namely acquiring ADC data from the DDR according to the parameter setting and sending the ADC data to the underwater sound special intelligent calculation through the Ethernet.

Further, the parameter setting step further includes: after the equipment is powered on, the Ethernet data is waited, after command data is received, protocol analysis is carried out according to a protocol, parameters set by a user are written into a corresponding register for other related programs to use, and then a reply message is sent to inform the user that the parameter setting is successful.

Further, the data acquisition step further comprises: and after receiving an acquisition starting command, reading parameters and initializing, waiting for a PPS signal if the PPS signal is effective, starting acquisition after receiving the PPS signal, writing data into the DDR, judging whether the acquisition is stopped if the stop signal is effective, and otherwise, continuing acquisition. And if the PPS signal is invalid, directly starting acquisition.

Further, the data reporting module further comprises: and according to the set parameters, reading the AD data from the DDR, and sending the AD data to the computer through the network.

The multi-channel embedded synchronous acquisition system and the method thereof have the following advantages:

1. the structure is light and convenient, and the external dimension of 100mm 200mm realizes the collection channel as much as 128.

2. The acquisition channel is expandable, and synchronous acquisition of more channels can be realized by adding a data acquisition unit;

3. the channels can be used in groups, so that one acquisition system is realized, and various acquisition tasks are completed;

4. an IEPE sensor interface can be realized, an IEPE sensing network is directly connected externally, vibration signal acquisition is realized, a conversion board card is omitted, and connection complexity is reduced;

5. distributed synchronous acquisition can be realized, and distributed synchronous acquisition is realized with the satellite second pulse signal;

6. and an Ethernet interface is adopted, so that the use is convenient, the networking is convenient, and the cross-platform application is convenient.

Drawings

FIG. 1 shows a system block diagram of a synchronous data acquisition card;

FIG. 2 is a general schematic diagram of a multi-channel embedded synchronous acquisition module;

FIG. 3 is a schematic diagram of the hardware components of the multi-channel embedded synchronous acquisition module;

FIG. 4 is a schematic diagram of the software components of the multi-channel embedded synchronous acquisition module;

FIG. 5 is a general block diagram of the multi-channel embedded synchronous acquisition module;

FIG. 6 is a schematic diagram of a system connection of a multi-channel embedded synchronous acquisition module;

FIG. 7 is a diagram of a multi-channel embedded synchronous acquisition module;

FIG. 8 illustrates a multi-channel embedded synchronous acquisition module assembly form;

FIG. 9 is a schematic diagram of the internal connection of the multi-channel embedded synchronous acquisition module;

FIG. 10 is a schematic diagram of an interface of a multi-channel embedded synchronous acquisition module;

FIG. 11 is a structural effect diagram of the packing box;

FIG. 12 is a view showing an overall configuration of a data acquisition unit;

FIG. 13 is a circuit diagram of signal conditioning;

FIG. 14 is a circuit diagram of a signal interface;

FIG. 15 is a schematic diagram of a gigabit Ethernet interface design;

FIG. 16 is a circuit diagram of a voltage reference source;

FIG. 17 is a diagram of a DDR memory circuit design;

FIG. 18 is a schematic diagram of a clock circuit design;

fig. 19 is an overall configuration diagram of the main control unit;

FIG. 20 is a schematic diagram of a switch design;

FIG. 21 is a schematic view of a back plate design;

FIG. 22 is a schematic diagram of the upper computer software;

FIG. 23 is a schematic view of an operation panel of the upper computer;

FIG. 24 is a parameter setting module workflow diagram;

FIG. 25 is a data acquisition module workflow diagram;

FIG. 26 is a flowchart of the data reporting module;

FIG. 27 is a diagram of an AD7768 synchronous connection;

FIG. 28 is a schematic diagram of reference clock and PPS connections;

fig. 29 is a timing chart of input and output of the schmitt trigger.

Detailed Description

The technical invention will be clearly and completely described below in conjunction with specific embodiments of the invention, but it should be understood by those skilled in the art that the embodiments described below are only for illustrating the invention and should not be construed as limiting the scope of the invention. All other embodiments of the invention can be obtained by those skilled in the art without any inventive work based on the embodiments of the invention, and the invention is within the protection scope of the invention.

The preferred embodiments of the present invention will be described in detail with reference to the following examples. It is to be understood that the following examples are given for illustrative purposes only and are not intended to limit the scope of the present invention. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of the present invention and all such modifications and alternatives fall within the scope of the appended claims.

The experimental procedures used in the following examples are all conventional procedures unless otherwise specified. Materials, reagents and the like used in the following examples are commercially available unless otherwise specified.

The multi-channel embedded synchronous acquisition system mainly realizes synchronous acquisition of underwater acoustic array signals of no less than 128 channels and transmits acquired data to an underwater acoustic special intelligent computer through Ethernet. The functional requirements are as follows:

a PPS signal synchronous input interface with an external GNSS;

the capability of synchronously acquiring data based on external PPS signals is provided;

the system is provided with an Ethernet data transmission interface;

the system has real-time data acquisition and transmission capability;

the capability of data grouping collection is provided;

the system has the capability of receiving and executing the control command of the upper computer, wherein the command comprises sampling rate setting, buffer area emptying, PPS signal validity, acquisition starting, acquisition ending and the like;

the multi-channel embedded synchronous acquisition system can be divided into: a hardware portion and a software portion. As shown in fig. 2, the hardware part conditions the input differential analog signal and converts the conditioned signal into a digital signal, and then transmits the digital signal to the upper computer through the ethernet; the upper computer software completes the input and output of man-machine data through an interactive interface of an application program, and the application program controls the hardware by sending a control command based on an Ethernet communication protocol or an interface library.

Hardware part

The hardware of the multi-channel embedded synchronous acquisition system is generally divided into a data acquisition unit and a main control unit, which are shown in fig. 3. The main control unit is provided with a power supply interface, a network port and a PPS signal interface which are respectively connected with a power supply, a computer and a GNSS PPS signal. The data acquisition unit is provided with a multi-channel differential analog signal interface connected with the underwater acoustic array sensor.

The data acquisition unit comprises an A/D acquisition module, an Ethernet communication module and a synchronous signal module:

(1) And the A/D acquisition module. The A/D acquisition module conditions the input underwater sound differential analog signal and realizes the parallel acquisition of the 32-channel differential analog signal under the control of a synchronous signal or an Ethernet control command.

(2) And an Ethernet communication module. The Ethernet communication module is used as a communication interface between the data acquisition unit and the upper computer, realizes communication with the upper computer through Ethernet, acquires control commands such as sampling rate setting, buffer zone emptying, PPS signal validity, acquisition start and acquisition end and channel grouping setting, and transmits acquired data in real time.

(3) And a synchronous signal module. The synchronous signal module has two functions, namely controlling an A/D acquisition channel in the data acquisition unit to perform synchronous acquisition. And the second is that an external synchronization and trigger interface is provided, and cascade synchronization of a plurality of data acquisition units is realized through the interface, so that synchronous acquisition of more analog input channels is realized. In the invention, 4 data acquisition units are cascaded in total, and 128-channel differential analog signal synchronous acquisition is realized. The invention can also expand synchronous acquisition of more channels.

The main control unit consists of a network exchange module, a synchronous signal module and a power management module:

(1) And a network switching module. The network switching module is essentially a network switch and realizes network data switching. And network connection and data exchange between the data acquisition units and an external computer are realized.

(2) And a synchronization signal module. The synchronous signal module is mainly used for receiving an external trigger/synchronous signal, conditioning the signal and then connecting the signal to a trigger/synchronous signal interface of the data acquisition unit to realize the function of synchronous data acquisition based on the external trigger/synchronous signal.

(3) And a power management module. The power management module is used for conditioning and filtering an external 12V power supply to provide a stable and reliable power supply for the power management module and the data acquisition unit.

Software component

The overall design of the multichannel embedded synchronous acquisition module software is divided into an upper computer software and a lower computer software, which are shown in fig. 4.

The upper computer software mainly comprises an interface library, a communication protocol, ethernet communication, data acquisition, data caching, data display, a human-computer interface, parameter setting, a control command and other modules.

The interface library, the communication protocol and the Ethernet communication module realize the data communication of the Ethernet and establish the connection with the multi-channel embedded synchronous acquisition module. Meanwhile, the interface library and the communication protocol are independent modules and can provide interfaces for secondary development and use for users.

And the data acquisition module receives the A/D acquisition data in real time through the Ethernet.

The data caching module caches the acquired A/D data for the data display module to use. The data display module displays real-time A/D acquisition data in the form of drawing graphs and the like.

The system comprises a human-computer interface module, a parameter setting and control command module, wherein the human-computer interface module provides a system and a user interaction interface, and a user sets parameters through the human-computer interface module and sends a control command.

System components

The multi-channel embedded synchronous acquisition module mainly comprises a data acquisition unit, a main control unit and a connecting back plate, wherein the data acquisition unit comprises modules of Ethernet communication, analog data acquisition, IEPE drive and the like. The main control unit includes modules such as network switch, power supply, reference clock, PPS synchronization, etc., as shown in fig. 5.

The working principle of the multi-channel embedded synchronous acquisition module is shown in fig. 6, and the communication connection between an upper computer and each data acquisition unit is realized by connecting a network switch of a main control unit and the upper computer; the analog signals of the underwater acoustic array are sequentially connected to the analog data acquisition interfaces of the data acquisition units; the PPS synchronous signal of the external GNSS is connected to a trigger/synchronous input interface of the main control unit; the host computer writes in parameters such as sampling rate, sampling channel, reference voltage to start AD collection, the data acquisition unit sends the data of gathering to the host computer through the switch of main control unit.

Structural design

Housing design

The multichannel embedded type synchronous acquisition module shell is made of an integrated aluminum alloy material, has the functions of high temperature resistance, corrosion resistance, easy heat dissipation and the like as shown in figure 7, and has the external dimension of less than or equal to 200mm in length, less than or equal to 100mm in width and less than or equal to 100mm in height.

Calculating the size of a multi-channel embedded synchronous acquisition module: length = length of housing 190mm + max (length of data acquisition unit connector 5mm, length of main control unit connector 5 mm) =195mm. Meets the requirements. Width = shell width 100mm, meets the requirements. Height = 100mm of the shell height, and meets the requirement.

Internal structure

The inside data acquisition unit 4 that has of module, 1 main control unit connects 1 of backplate. The connecting back plate is arranged at the bottom of the shell by an aluminum alloy supporting frame, as shown in figure 8. The side wall of the device housing has 5 slide rails for fixing 4 data acquisition units and 1 main control unit, as shown in fig. 9. The data acquisition unit and the main control unit backplane connector are connected with the connector of the backplane.

Interface design

The side panel of the module extends out of connectors and indicator lamps such as a power supply interface, a PPS synchronous interface, a synchronous output interface Ethernet interface and the like of the main control unit; the analog acquisition interface and the indicator light of the data acquisition unit are shown in fig. 10.

Packing case design

The packing box adopts the aluminum alloy packing box, and other annexes such as collection module, supporting cable and specification certificate are placed in a packing box, as shown in fig. 11. The incasement is equipped with and is used for cushioning absorbing interior trim material, carries out the profile modeling according to collection module's overall dimension to the packing box inside lining and tailors, makes the box have the characteristic of shocking resistance, and the cable is put in the box bottom, and equipment is put in the box upper strata.

Data acquisition unit

Integral structure

The data acquisition unit mainly has the function of realizing 32-path differential signal parallel acquisition, the invention adopts an ADC + FPGA framework and utilizes a module design idea to design the data acquisition unit, and the structure is shown in figure 12, wherein channels 0-31 are mutually independent. The data acquisition unit comprises 32 IEPE constant current source modules, 32 signal conditioning modules, a reference voltage module, a clock module, a DDR storage module, a gigabit Ethernet module and a synchronization and PPS signal module.

The IEPE constant current source module can provide a 4mA current source for the IEPE sensor, and when the external sensor is the IEPE, the IEPE constant current source module can be directly used simply and reliably.

And the signal conditioning module conditions the input analog signal to a proper range and inputs the signal to the A/D converter for sampling. And simultaneously, the input impedance of the interface is improved.

And the reference voltage module provides a voltage reference for the A/D converter and the signal conditioning, and switches the signal input range by switching different reference voltages.

And the clock module is used for providing a basic clock for the system operation.

And the DDR memory module is used as an A/D acquisition data cache.

And the Ethernet module is used as a data acquisition unit and an upper computer communication interface.

And the synchronous signal and the PPS signal realize the connection and system cascade of the data acquisition unit and an external synchronous/trigger signal.

Selection of main chip

The chip type selection is used as the important work of system design, and the main chips of the data acquisition unit comprise an FPGA chip, an analog-to-digital conversion chip, an operational amplifier, a voltage reference source and the like.

FPGAs integrate millions of logic gates internally, allowing repeated programming and erasing, and have become widely used in recent years. The FPGA is used in the design, so that the space volume of the controller can be reduced in a large scale, the power consumption is reduced, the reliability of the system is improved, and the design is flexible. At present, FPGA manufacturers in the market mainly comprise ALTERA and XILINX, a series of chips with extremely high cost performance are stable in performance, reliable in reliability and low in price, and are widely applied to the field of industrial control, the type of the FPGA is XC7A100T-2FGG484I, and the FPGA belongs to the invention of the Artix-7 series of Xilinx company, specific parameters are shown in Table 1, and the performance of the FPGA can meet working requirements.

TABLE 1 FPGA chip Primary parameters

The analog-to-digital conversion chips are various in types, and an analog-to-digital conversion chip AD7768 of an AD company is selected according to the requirements of the invention. The main parameters are shown in Table 2.

Table 2 major parameters of the AD7768 chip

The performance of the operational amplifier directly influences the performance of the circuit, and the invention selects AD company ADA4610, the main parameters of which are shown in Table 3

TABLE 3 ADA4610 chip Main parameters

The voltage reference source chips ADR441B and ADR445B are respectively used as 2.5V and 5V voltage reference bases, and the main parameters thereof are shown in Table 4

TABLE 4 ADR441B and ADR445B chip key parameters

Circuit design

(1) IEPE constant current source

IEPE sensors, unlike charged piezo sensors, require a power source to operate. When the external sensor is an IEPE, the IEPE constant current source is replaced by parameter configuration, so that the sensor can normally work.

(2) Signal conditioning circuit

The measured differential analog signal enters the data acquisition unit, the signal range is-2.5V, or-5V, in order to meet the requirement of measurement accuracy, a voltage follower made of an operational amplifier is used for realizing impedance matching so as to increase the input impedance, and the measured signal range is kept unchanged after the voltage follower passes through. The analog-to-digital conversion chip selected by the invention has the reference voltage VREF range of 1-5V and the differential input voltage range of-VREF to + VREF. Therefore, the selection of two ranges of ± 5V and ± 2.5V is realized by switching the reference voltage of the analog-to-digital conversion chip in the present invention, as shown in fig. 13.

As shown in fig. 14, the signal access interface is compatible with two forms of differential and single-ended, and can adopt two modes of floating input and common ground input.

Gigabit Ethernet circuit

A1-channel gigabit Ethernet communication interface is designed by using an FPGA external RealtekRTL8211EG Ethernet PHY chip, so that data transmission is realized. The RTL8211EG chip supports 10/100/1000Mbps network transmission rate and carries out data communication with the FPGA through a GMII interface. RTL8211EG supports MDI/MDX self-adaptation, various speed self-adaptation and Master/Slave self-adaptation, and supports MDIO bus to carry out PHY register management. A schematic diagram of a gigabit ethernet design is shown in fig. 15. When the network is connected to a gigabit Ethernet, the data transmission of the FPGA and the PHY chip RTL8211EG is communicated through a GMII bus, and the transmission clock is 125Mhz. The receiving clock E _ RXC is provided by the PHY chip, the transmitting clock E _ GTXC is provided by the FPGA, and data is sampled at the rising edge of the clock. When the network is connected to a hundred-mega Ethernet, the FPGA and the PHY chip RTL8211EG communicate through an MII bus during data transmission, and the transmission clock is 25Mhz. Both the receive clock E _ RXC and the transmit clock E _ TXC are provided by the PHY chip, with data sampled on the rising edge of the clock.

Voltage reference source circuit

The voltage reference source provides a reference voltage for the analog-to-digital converter, and the performance of the voltage reference source directly influences the precision of the analog-to-digital conversion. The invention designs two reference voltages of 2.5V and 5V to realize the range selection of two input signals of 2.5V and 5V. The circuit is shown in fig. 16.

DDR memory circuit

The data acquisition unit is designed with two 4Gbit (512 MB) DDR3 chips (8 Gbit (1 GB) in total) of Micron (Meiguang) and a model number of MT41J256M16HA-125 (compatible with MT41K256M16 HA-125) as system data cache. The bus width of the DDR is 32 bits in total. The maximum operational clock speed of DDR3SDRAM can reach 400MHz (data rate 800 Mbps). The circuit design schematic is shown in fig. 17.

Clock circuit

The clock circuit is designed as shown in fig. 18, an external reference clock and a crystal oscillator are connected into the FPGA, an a/D clock source is selected through parameters, and an a/D converter is driven through a clock distributor.

Master control unit design

Integral structure

The overall design of the main control unit is shown in fig. 19, and the main control unit mainly comprises a switch module, 6 gigabit network interface modules, a power management module, a synchronous signal module and a reference clock module.

The switch module is used as the core of the main control unit and is used for realizing Ethernet connection and data communication between the 4 data acquisition units and external computing. The 6 gigabit network interfaces are respectively connected with the data acquisition module and an external computer.

The power management module realizes the management of an external power supply to provide a safe, stable and reliable power supply for the system.

The synchronous signal module realizes the PPS signal input and conditioning of an external GNSS, and synchronously outputs conditioned signals to each data acquisition unit to realize synchronous acquisition.

Selection of main chip

The invention selects REALTEKRTL8370N-VB as the main chip of the main control unit, and conforms to the standards of IEEE802.3, IEEE802.3u, IEEE802.3x, IEEE802.3az and IEEE802.3 ab; the system is provided with 8 10/100/1000Mbps self-adaptive RJ45 ports, and the ports are supported to be automatically turned over; the UTP port supports an automatic negotiation function, an automatic frame skipping transmission mode and a transmission rate; and MAC address self-learning is supported.

Circuit design

Circuit of switch

The gigabit Ethernet switch chip selected by the invention is provided with 8 interfaces, and 4 interfaces are designed to be respectively connected with 4 data acquisition units. And 2, leading out a port 2 to be used as a connection of a multi-channel embedded synchronous acquisition module and a computer. In addition, 2 ports are used as standby interfaces to facilitate system expansion and upgrading. The design schematic diagram of the PPS signal processing circuit is shown in FIG. 20

PPS signal is generally TTL level, and the invention uses Schmitt inverter to shape PPS signal, and 74LV2G14SH is selected.

Reference clock

The invention uses CDV304 as 1. Firstly, the clock source of each channel is ensured to have good synchronization performance. Meanwhile, when the signal is wired, the lengths of the signal source to each data acquisition unit are consistent as much as possible. Therefore, the driving capability and the signal quality of the clock are ensured, and the time difference caused by different paths passed by the clock signal is avoided.

Ethernet data transmission

The invention requires real-time data acquisition and transmission capability. The number of the acquisition paths is 128, the AD conversion bit number is 24bit, and the single-channel sampling rate is more than or equal to 200kSPS.

The data amount per second is 128 × 24 × 200=614400kbit =614.4mbit.

The maximum theoretical transmission rate for a gigabit ethernet network is 1000Mbit/s. In consideration of actual loss and system redundancy, the invention designs two gigabit network ports, designs the transmission data volume of 2000Mbit > >614.4Mbit, and can meet the requirement.

Connecting back plate

The connection back plate is mainly used for physical connection of the data acquisition unit and the main control unit. As shown in fig. 21, there are 5 connection slots in total from 0 to 4, the slot 0 is connected to the main control unit, the slots 1 to 4 are connected to the data acquisition unit, and the connection relationship is that the ethernet interfaces of the slots 1 to 4 are respectively connected to the ethernet interfaces 1 to 4 of the slot 0. The slot 0 power output interface, the reference clock interface and the synchronous signal interface are respectively connected to the power input interfaces, the reference clock interfaces and the synchronous signal interfaces of the slots 1-4.

Software design

Software composition

The multichannel embedded synchronous acquisition module software mainly comprises upper computer software, a lower computer program, a development interface and a communication protocol.

Software of upper computer

The software of the upper computer of the multi-channel embedded synchronous acquisition module consists of a data storage management module, an Ethernet communication module, a user parameter input module, a data graphic drawing module, a data calculation module and a human-computer interface, as shown in FIG. 22.

The data storage management module realizes the management functions of A/D, such as storage, export, deletion and the like;

the Ethernet communication module realizes data interaction between the upper computer and the lower computer;

the user parameter input module realizes the setting of the parameters of the A/D acquisition and communication modes;

the data graph drawing module presents the A/D data to a user in a graph mode, so that the collected data can be observed visually;

the data statistics calculation module analyzes and calculates the A/D data;

the human-computer interface mainly realizes the functions of parameter setting, data display and the like as shown in fig. 24.

Development interface and communication protocol

The development interface and the communication protocol are provided for users, and secondary development and use of the users are facilitated.

Lower computer software

The multi-channel embedded synchronous acquisition module consists of a data acquisition unit and a main control unit. The main control unit mainly has the function of a gigabit Ethernet interactive machine and does not need to write programs. The software of the data acquisition unit is divided into three modules of parameter setting, data acquisition and data reporting according to functions.

The parameter setting module mainly obtains user parameters through Ethernet, and sets parameters such as sampling rate, acquisition channel, trigger, start/stop signal and the like of the data acquisition module and parameters such as reporting address, quantity and the like of the data reporting module.

The data acquisition module is mainly used for controlling the ADC to acquire analog data according to parameters such as a sampling rate, an acquisition channel, a trigger signal and a start/stop signal set by a user, and putting the acquired data into the DDR.

The data reporting module is mainly used for acquiring ADC data from the DDR according to parameter setting and sending the data to the underwater sound special intelligent calculation through the Ethernet.

Parameter setting module

As shown in fig. 24, the parameter setting module has a work flow chart, after the device is powered on, the device waits for ethernet data, and when command data is received, performs protocol analysis according to a protocol, writes parameters set by a user into a corresponding register for use by other related programs, and then sends a reply message to notify the user that the parameter setting is successful.

Data acquisition module

And the data acquisition module reads parameters and initializes after receiving the acquisition starting command, waits for PPS signals if the PPS signals are effective, starts to acquire after receiving the PPS signals, writes data into the DDR, then judges whether the stop signals are effective or not, and stops acquiring. If the PPS signal is invalid, the acquisition is directly started, and the work flow is shown in figure 25.

Data reporting module

And the data reporting module reads the AD data from the DDR according to the set parameters and sends the AD data to the underwater sound special intelligent computer through the network, and the working flow of the data reporting module is shown in fig. 26.

Design calculation

Number of signal input channels

The invention uses 4 data acquisition units, each data acquisition unit has 32 channels, and the total number of the channels is 128 channels, thereby meeting the requirement that the system is more than or equal to 128 channels.

Synchronous acquisition accuracy

Synchronization between AD multipaths

The analog-to-digital conversion chip AD7768 used in the present invention has three ways to ensure system synchronization, as shown in FIG. 27.

(1) A START pulse signal is applied to the first AD7768 device, and the first AD7768 samples this asynchronous START pulse, producing a pulse associated with the basic MCLK signal on the SYNC _ OUT pin of the first device, connecting the SYNC _ OUT pin of the first device to all of the SYNC _ IN pins of the AD7768, as shown.

(2) Using SPI synchronization, a synchronization command is written to the first AD7768 device. Similar to (1), SPI synchronization produces a pulse on the first device SYNC _ OUT that is related to the basic MCLK signal.

(3) A signal synchronized to basic MCLK is applied to the SYNC _ IN pin. This signal is connected from a star point and directly to the SYNC _ IN pin of each AD7768.

The invention selects the first method to realize 128-channel synchronous acquisition, and uses a clock distribution chip to enable all data acquisition units to share the same reference clock, as shown in fig. 28:

(1) Sharing the same reference clock, and arranging wires with equal length;

(2) And the circuit is connected with PPS signals in a star connection mode and is wired with equal length.

The measures can ensure that the time error among AD multiple channels in the system is less than 1ns.

PPS Signal synchronization

Calculating the synchronization precision of the PPS signals, mainly calculating the signal delay from the PSS signals to the AD acquisition end, wherein the delay mainly comprises: PSS signal interface circuit delay, signal interface to FPGA end PCB line delay, FPGA logic delay, trigger signal from FPGA output to AD chip line delay, trigger signal and AD sampling clock phase difference delay. The delay time of each part is calculated respectively

(1) The PSS signal interface circuit samples the schmitt trigger for shaping, looking at the chip manual, maxtph = MAXtPLH =4.7ns, as shown in fig. 29.

(2) The PCB routing delay is realized, and the propagation speed of a signal in vacuum is 11.85inch/ns. The propagation rate of the signal on the PCB board = the propagation rate of the signal in vacuum/PCB dielectric constant. Typical data is 5555mil/ns equal to about 141mm/ns. When the PCB is wired, the length of the wire is controlled within 282mm, and the maximum delay time is ensured to be 2ns.

(3) The maximum delay time can be determined by setting FPGA constraint to ensure that the maximum delay time is 5ns.

(4) And (2) the PCB routing is positioned on the same board and can be controlled within 140mm, and the maximum delay time of the PCB routing is ensured to be 1ns.

(5) The phase difference between the trigger signal and the AD sampling clock is maximally one clock, so the maximum delay is =1/MCLK, and MCLK =32.768MHz in the system, and one clock period is about 30.5ns.

To sum up: the total delay of the system =4.7+, 2+, 5+, 1+30.5=43.2ns. The requirement that the system is less than or equal to 50ns is met.

Signal to noise ratio

The signal-to-noise ratio of the analog-to-digital conversion system is calculated by firstly calculating the total noise of the system. The ADC system typically includes amplifiers, analog-to-digital converters, reference source noise, and other noise caused by circuit resistor-capacitor, etc.

The system signal-to-noise ratio can be formulated

In the formula: SNR _total For the system signal-to-noise ratio, V _{FSR_rms} Is the effective value of the signal, V _nt Is the total noise;

and (6) calculating.

Total noise of system

In the formula V _nADC Is analog-to-digital converter noise, V _nAmp Is amplifier noise, V _nARef Is the reference source noise. V _RC Other noise caused by capacitive resistance on the circuit, etc.

The chip manual is searched, the signal-to-noise ratio of AD7768 is 107.8dB, the total harmonic distortion plus noise of ADA4610 is 0.00025%, and the noise of reference sources ADR445 and ADR441 is 1.2uV.

Ignoring other noise, i.e. V, caused by capacitive resistance, etc. in the circuit _RC When = 0:

when the system selects the range of +/-5V, V _{FSR_rms} V when =1.767V _nADC ≈7.2uV，V _nAmp ≈4.4uV， V _nARef ＝1.2uV，V _RC The equation is substituted for 0uV, and the snr is found to be about 106.33dB.

When the system selects the range of +/-2.5V, V _{FSR_rms} When =0.8835V, V _nADC ≈3.6V _nAmp ≈2.2V _nARef ＝1.2uV， V _RC And the signal to noise ratio is about 106.08dB by substituting the equation into the equation of 0 uV.

In ignoring other noise, i.e. V, due to circuit capacitance resistance or the like _RC When =15 uV:

when the system selects the range of +/-5V, V _{FSR_rms} When =1.767V, V _nADC ≈7.2uV，V _nAmp ≈4.4uV， V _nARef ＝1.2uV，V _RC And the equation is substituted by =15uV, and the signal-to-noise ratio is about 100dB.

When the system selects the range of +/-2.5V, V _{FSR_rms} V is 0.8835V _nADC ≈3.6，V _nAmp ≈2.2V _nARef ＝1.2uV， V _RC And (5) =15uV, and substituting the formula to obtain the signal-to-noise ratio of about 95dB.

Therefore, the noise such as PCB circuit resistance and capacitance is controlled within 15uV through PCB design, and the 95dB signal-to-noise ratio of the system can be realized.

In summary, the system can achieve a signal-to-noise ratio of 93dB.

Number of AD conversion bits

The number of AD conversion bits is determined by an A/D conversion chip, and the AD7768 is selected as the system A/D converter, and the number of the conversion bits is 24 bits.

Single channel sampling rate

The single-channel sampling rate is determined by an A/D conversion chip, and the AD7768 is selected to be used as the A/D converter of the system, and the single-channel sampling rate of the A/D converter is up to 256kSPS.

Dynamic range

The AD dynamic range is determined by an A/D conversion chip, and the AD7768 is selected to be used as a system A/D converter, and the dynamic range of the AD7768 is 108DB.

Input bandwidth

The input bandwidth of the system is determined by an operational amplifier and an A/D conversion chip, the input bandwidth of the A/D conversion chip AD7768 is 110.8kHz, and the input bandwidth of the operational amplifier ADA4610 is 10.6MHz. The minimum value of the two determines the input bandwidth of the system to be 110.8kHz.

Input impedance

The invention uses an operation method amplifier to design an input interface circuit, and the input impedance is 1M omega according to the circuit design.

Data caching

The data acquisition unit comprises 2 pieces of 512MBDDR memory particles, and the total number is 2 × 512 × 4=4GB.

Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims

1. A multi-channel embedded synchronous acquisition system comprises three major parts, namely a data acquisition unit, a main control unit and a connecting back plate, wherein the data acquisition unit comprises an Ethernet communication module, an analog data acquisition module and an IEPE driving module; the main control unit comprises a switch module, 6 gigabit network interface modules, a power management module, a synchronous signal module and a reference clock module; the connection back plate is used for physically connecting the data acquisition unit and the main control unit;

2. The multi-channel embedded synchronous acquisition system according to claim 1, wherein the data acquisition unit realizes 32-channel differential signal parallel acquisition, adopts an ADC + FPGA architecture and utilizes a module design idea to design the data acquisition unit, wherein channels 0-31 are independent; the data acquisition unit comprises 32 IEPE constant current source modules, 32 signal conditioning modules, a reference voltage module, a clock module, a DDR memory module, a gigabit Ethernet module and a synchronization and PPS signal module.

3. The multi-channel embedded synchronous acquisition system according to claim 2, wherein the IEPE constant current source module provides a 4mA current source for the IEPE sensor, which is directly simple and reliable to use when the external sensor is the IEPE;

the signal conditioning module conditions an input analog signal and inputs the conditioned signal into the A/D converter for sampling, and meanwhile, the input impedance of the interface is improved;

the clock module provides a basic clock for system work;

the DDR storage module is used as a data cache of the A/D acquisition module;

the synchronous signal and PPS signal module is used for receiving an external trigger/synchronous signal, conditioning the external trigger/synchronous signal, then connecting the conditioned external trigger/synchronous signal to a trigger/synchronous signal interface of a data acquisition unit, realizing the function of synchronous data acquisition based on the external trigger/synchronous signal, and realizing the connection and system cascade of the data acquisition unit and the external synchronous/trigger signal.

4. The multi-channel embedded synchronous acquisition system according to any one of claims 1 to 3, wherein the multi-channel embedded synchronous acquisition system is cascaded with 4 data acquisition units in total to realize synchronous acquisition of 128-channel differential analog signals; the multi-channel embedded synchronous acquisition system can also expand synchronous acquisition of more channels.

5. The multi-channel embedded synchronous acquisition system according to claim 1, wherein the switch module in the main control unit, as a core of the main control unit, is used for realizing ethernet connection and data communication between 4 data acquisition units and external computing; the 6 kilomega network interfaces are respectively connected with the data acquisition module and an external computer;

the synchronous signal module realizes the PPS signal input and conditioning of an external GNSS and synchronously outputs conditioned signals to each data acquisition unit to realize synchronous acquisition;

6. A method for adopting the multi-channel embedded synchronous acquisition system of any one of claims 1 to 5, wherein the multi-channel embedded synchronous acquisition system realizes the following steps through an upper computer:

a data graph drawing module step, which presents the A/D data to a user in a graph mode so as to be convenient for visually observing the collected data;

a data calculation step, namely analyzing and calculating the A/D data;

7. The method according to claim 6, wherein the multi-channel embedded synchronous acquisition system implements the following steps by a data acquisition unit:

a data acquisition step, namely controlling the ADC to acquire analog data according to parameters such as a sampling rate, an acquisition channel, a trigger signal, a start/stop signal and the like set by a user, and putting the acquired data into the DDR;

8. The method of claim 7, wherein the parameter setting step further comprises: the equipment waits for Ethernet data after being electrified, after receiving command data, carries out protocol analysis according to a protocol, writes parameters set by a user into a corresponding register for other related programs to use, and then sends a reply message to inform the user of successful parameter setting.

9. The method of claim 7, wherein the data acquisition step further comprises: and after receiving an acquisition starting command, reading parameters and initializing, waiting for a PPS signal if the PPS signal is effective, starting acquisition after receiving the PPS signal, writing data into the DDR, then judging whether the acquisition is stopped if the stop signal is effective, and otherwise, continuing acquisition. Acquisition is started directly if the PPS signal is invalid.

10. The method of claim 7, wherein the data reporting module step further comprises: and according to the set parameters, reading the AD data from the DDR and sending the AD data to the computer through the network.