CN111131267A - Ethernet self-adaption method, device and system based on FPGA - Google Patents
Ethernet self-adaption method, device and system based on FPGA Download PDFInfo
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- CN111131267A CN111131267A CN201911371227.6A CN201911371227A CN111131267A CN 111131267 A CN111131267 A CN 111131267A CN 201911371227 A CN201911371227 A CN 201911371227A CN 111131267 A CN111131267 A CN 111131267A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Abstract
The invention relates to the technical field of Ethernet self-adaptation, and discloses an Ethernet self-adaptation method, a device and a system based on an FPGA (field programmable gate array), wherein the method comprises the following steps: receiving a first network transmission packet sent by the PHY chip through a first mii interface; determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface; according to the first transmission rate mode, carrying out Ethernet protocol analysis on the first network transmission packet to obtain a first network data packet; converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order; and executing corresponding system data processing according to the content of the first network data stream. The Ethernet self-adaption method, the device and the system based on the FPGA enhance the stability of the Ethernet self-adaption by a hardware architecture, and the interface can be flexibly selected by the programmable configuration interface, thereby improving the application adaptability of the Ethernet self-adaption method.
Description
Technical Field
The invention relates to the technical field of Ethernet self-adaptation, in particular to an Ethernet self-adaptation method, device and system based on an FPGA.
Background
At present, the transmission bandwidth of optical fiber communication can reach 100Gbps, while products at 40Gbps are gradually commercialized, and products at 10Gbps are widely applied to practical networks. Since low-bandwidth ethernet has been commercially available for a long time in the network, the access layer devices in the metro network are also 10M ethernet, 100M ethernet and 1000M ethernet which are widely used. However, due to the development of internet of things technology and cloud computing, the requirement of end users for broadband should be higher and higher, and then the previously operated 10M ethernet and 100M ethernet are inevitably replaced by 1000M ethernet. Because the rates of two interfaces of different broadband Ethernet networks are different, the code patterns sent by opposite terminals can not be mutually identified, and the problem that the interfaces of different broadband Ethernet networks can not be butted in the network upgrading process exists. In practical situations, an engineer is required to manually configure to achieve the pairing of the speed and the operation mode of the interfaces of the two devices.
In the prior art, the function of ethernet adaptation can be added to the PHY chip, but the existing ethernet adaptation technology is mostly implemented by using software and a dedicated interface, which brings the problems of weak stability, inflexible use of a dedicated interface, and poor adaptability of the three-speed ethernet adaptation technology.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an Ethernet self-adapting method, device and system based on FPGA, to enhance the stability of Ethernet self-adapting by hardware architecture, and to enable an interface to be flexibly selected by a programmable configuration interface, thereby improving the application adaptability of the interface.
In order to solve the above technical problem, in a first aspect, the present invention provides an ethernet adaptive method based on an FPGA, including:
receiving a first network transmission packet sent by the PHY chip through a first mii interface;
determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface;
according to the first transmission rate mode, carrying out Ethernet protocol analysis on the first network transmission packet to obtain a first network data packet;
converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
and executing corresponding system data processing according to the content of the first network data stream.
Wherein the determining, according to the clock frequency of the first mii interface, a first transmission rate mode corresponding to the first network transmission packet specifically includes:
and intercepting the clock frequency of the first mii interface through a counter, and determining a first transmission rate mode corresponding to the first network transmission packet according to the intercepted clock frequency.
Further, the executing the corresponding system data processing comprises: and generating a second network data stream to be sent to the PHY chip.
Further, after the generating the second network data stream to be sent to the PHY chip, the method further includes:
recombining the second network data stream according to the host byte order and the network byte order to obtain a second network data packet;
according to the first transmission rate mode, packaging the second network data packet through an Ethernet protocol to obtain a second network transmission packet;
transmitting the second network transport packet to the PHY chip through a second mii interface according to a second mii interface transmission timing; the clock frequency of the second mii interface is obtained by phase-shifting and looping the clock frequency of the first mii interface.
In order to solve the same technical problem, in a second aspect, the present invention further provides an FPGA-based ethernet adaptive device, including: the device comprises a first mii interface, a rate interception module, an Ethernet protocol analysis module, a data conversion module and a data processing module;
the first mii interface is used for receiving a first network transmission packet sent by the PHY chip;
the rate listening module is configured to determine a first transmission rate mode corresponding to the first network transmission packet according to a clock frequency of the first mii interface;
the Ethernet protocol analysis module is used for carrying out Ethernet protocol analysis on the first network transmission packet according to the first transmission rate mode to obtain a first network data packet;
the data conversion module is used for converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
and the data processing module is used for executing corresponding system data processing according to the content of the first network data stream.
The rate listening module is configured to determine, according to the clock frequency of the first mii interface, a first transmission rate mode corresponding to the first network transmission packet, specifically:
the rate listening module listens to the clock frequency of the first mii interface through a counter, and determines a first transmission rate mode corresponding to the first network transmission packet according to the heard clock frequency.
Further, the executing the corresponding system data processing comprises: and generating a second network data stream to be sent to the PHY chip.
Furthermore, the ethernet adaptive device based on the FPGA further comprises a data reassembly module, an ethernet protocol encapsulation module, and a second mii interface;
the data recombination module is used for recombining the second network data stream according to a preset host byte sequence and a preset network byte sequence to obtain a second network data packet;
the Ethernet protocol encapsulation module is used for encapsulating the second network data packet into a second network transmission packet according to an Ethernet protocol;
the second mii interface is configured to send the second network transport packet to the PHY chip according to a second mii interface transmission timing sequence, where a clock frequency of the second mii interface is obtained by shifting and looping back a clock frequency of the first mii interface.
Further, the first mii interface is any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface or an sgmii interface;
the second mii interface is any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface, or an sgmii interface.
In order to solve the same technical problem, in a third aspect, the present invention further provides an ethernet adaptive system based on FPGA, which includes: PHY chip and the Ethernet self-adapting device based on FPGA; the PHY chip is configured to send the first network transport packet to the ethernet adaptive device, and receive the second network transport packet sent by the ethernet adaptive device.
The invention has the beneficial effects that: the invention provides an Ethernet self-adapting method, a device and a system based on FPGA, the method communicates with a PHY chip through an mii interface, receives or sends a network transmission packet, determines the transmission rate mode of the transmission through the clock frequency of a mii interface when receiving the network transmission packet, and analyzes and converts the network transmission packet according to different transmission rate modes to obtain a network data stream so as to execute corresponding system data processing according to the obtained network data stream. Compared with the prior art that different broadband Ethernet networks cannot mutually identify the code patterns sent by opposite terminals due to different interface rates, the mii interface of the invention can be flexibly selected, the transmission rate can be automatically identified, and the application applicability is improved. In addition, the invention does not need to use a chip with inherent function, does not need to increase extra cost, has strong portability and is more easily suitable for various application scenes.
Drawings
In order to more clearly illustrate the technical features of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic flowchart of an ethernet adaptive method based on FPGA according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of an ethernet adaptive device based on an FPGA according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an ethernet adaptive device based on an FPGA according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an ethernet adaptive system based on FPGA according to a fourth embodiment of the present invention.
Detailed Description
In order to clearly understand the technical features, objects and effects of the present invention, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention. Other embodiments, which can be derived by those skilled in the art from the embodiments of the present invention without inventive step, shall fall within the scope of the present invention.
Example one
Fig. 1 is a schematic flowchart of an ethernet adaptive method based on an FPGA according to an embodiment of the present invention.
As shown in fig. 1, the method comprises the steps of:
s10: receiving a first network transmission packet sent by the PHY chip through a first mii interface;
s20: determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface;
specifically, the clock of the 10M broadband ethernet transmission mii interface is 2.5M, each clock transmits 4-bit data, and two clocks transmit 8-bit data, i.e., 1byte data; an mii interface clock of 100M broadband Ethernet transmission is 25M, each clock transmits 4-bit data, and two clocks transmit 8-bit data, namely 1byte data; the 1000M broadband Ethernet transmission mii interface clock is 125M, each clock transmits 8bit data, and the rising edge and the falling edge of the clock respectively transmit 4 bit.
Further, determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface, specifically: the clock frequency of the first mii interface is sensed through a counter, the current Ethernet transmission rate is judged to be 10M, 100M or 1000M according to the sensed clock frequency, and a first transmission rate mode corresponding to the first network transmission packet is determined.
It should be understood that the counter is used to listen to the clock frequency of the first mii interface because the FPGA chip has its own clock counter, but the invention is not limited thereto. For example, a computer program that can perform rate sensing can also be written to implement rate sensing.
S30: according to the first transmission rate mode, carrying out Ethernet protocol analysis on the first network transmission packet to obtain a first network data packet;
specifically, according to the first transmission rate mode, the first network transmission packet is analyzed according to the ethernet protocol, the ethernet protocol component in the first network transmission packet is removed, and the application data obtained by removing the protocol component is extracted to obtain the first network data packet.
S40: converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
it should be understood that different cpus run different operating systems, and the host endianness and the network endianness may also be different, including the little-end endianness and the big-end endianness.
S50: according to the content of the first network data stream, executing corresponding system data processing;
it should be understood that the first network data stream may have different application requirements in practical applications, and corresponding data processing needs to be performed on the first network data stream. For example, when the first network data stream is applied to the image field, corresponding image data processing is performed, but the invention is not limited thereto. It should also be understood that executing the corresponding system data processing procedure further includes generating a second network data stream to be sent to the PHY chip after performing corresponding data processing on the first network data stream according to different application requirements.
Further, the ethernet adaptive method based on FPGA of the first embodiment further includes, after generating the second network data stream to be sent to the PHY chip, the following steps:
recombining the second network data flow according to the byte order of the host and the byte order of the network to obtain a second network data packet;
according to the first transmission rate mode, packaging the second network data packet through an Ethernet protocol to obtain a second network transmission packet;
specifically, according to the first transmission rate mode, the second network data packet is encapsulated according to the ethernet protocol, ethernet protocol components are added on the basis of the second network data packet, and the second network transmission packet is obtained after encapsulation.
Transmitting a second network transmission packet to the PHY chip through a second mii interface according to the transmission timing sequence of a second mii interface; the clock frequency of the second mii interface is obtained by phase-shifting and looping the clock frequency of the first mii interface.
The ethernet adaptive method based on FPGA according to the first embodiment of the present invention receives a first network transmission packet sent by a PHY chip through a first mii interface, determines a first network transmission rate corresponding to the first network transmission packet according to a clock frequency of a first mii interface, performs a series of subsequent processing to obtain a second network transmission packet that needs to be sent to the PHY chip, and sends the second network transmission packet to the PHY chip according to a time sequence sent by a second mii interface through a second mii interface. The clock frequency of the second mii interface is obtained by phase shifting and loopback of the clock frequency of the first mii interface, so that the Ethernet self-adaptation is realized, and the stability of the Ethernet self-adaptation is improved by a hardware architecture; compared with the chip with the inherent function, the FPGA has more flexible design and stronger portability, and is more easily suitable for various application scenes.
Example two
Fig. 2 is a schematic structural diagram of an ethernet adaptive device based on an FPGA according to a second embodiment of the present invention.
As shown in fig. 2, the apparatus includes: a first mii interface, a rate listening module, an Ethernet protocol parsing module, a data conversion module and a data processing module, wherein,
the first mii interface is used for receiving a first network transmission packet sent by the PHY chip;
the first mii interface may be any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface, or an sgmii interface, and the data transmission interface of the second embodiment of the present invention is more flexible to select compared with the prior art in which the data transmission interface is a dedicated interface defined by an inherent function chip.
The rate interception module is used for determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface;
specifically, the clock of the 10M broadband ethernet transmission mii interface is 2.5M, each clock transmits 4-bit data, and two clocks transmit 8-bit data, i.e., 1byte data; an mii interface clock of 100M broadband Ethernet transmission is 25M, each clock transmits 4-bit data, and two clocks transmit 8-bit data, namely 1byte data; the 1000M broadband Ethernet transmission mii interface clock is 125M, each clock transmits 8bit data, and the rising edge and the falling edge of the clock respectively transmit 4 bit.
Further, the rate listening module is configured to determine, according to the clock frequency of the first mii interface, a first transmission rate mode corresponding to the first network transmission packet, specifically: the rate interception module intercepts the clock frequency of the first mii interface through a counter, judges whether the current ethernet transmission rate is 10M, 100M or 1000M according to the intercepted clock frequency, and determines a first transmission rate mode corresponding to the first network transmission packet.
It should be understood that the counter is used to listen to the clock frequency of the first mii interface because the FPGA chip has its own clock counter, but the invention is not limited thereto.
The Ethernet protocol analysis module is used for carrying out Ethernet protocol analysis on the first network transmission packet according to the first transmission rate mode to obtain a first network data packet;
specifically, the ethernet protocol analysis module analyzes the first network transmission packet according to the ethernet protocol according to the first transmission rate mode, removes the ethernet protocol component in the first network transmission packet, and extracts the application data obtained by removing the protocol component to obtain the first network data packet.
The data conversion module is used for converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
it should be understood that different cpus run different operating systems, and the host endianness and the network endianness may also be different, including the little-end endianness and the big-end endianness.
And the data processing module is used for executing corresponding system data processing according to the content of the first network data stream.
It should be understood that the first network data stream may have different application requirements in practical applications, and the data processing module needs to perform corresponding data processing on the first network data stream. For example, when the first network data stream is applied to the image domain, the data processing module performs corresponding image data processing, but the invention is not limited thereto. It should be further understood that, after performing corresponding data processing on the first network data stream according to different application requirements after the data processing module performs corresponding system data processing, the data processing module further generates a second network data stream that needs to be sent to the PHY chip.
Further, the ethernet adaptive device based on FPGA of the second embodiment further includes a data reassembly module, an ethernet protocol encapsulation module, and a second mii interface;
the data recombination module is used for recombining the second network data stream according to the preset host byte sequence and the preset network byte sequence to obtain a second network data packet;
the Ethernet protocol encapsulation module is used for encapsulating the second network data packet into a second network transmission packet according to the Ethernet protocol;
specifically, the ethernet protocol parsing module encapsulates the second network data packet according to the ethernet protocol according to the first transmission rate mode, adds an ethernet protocol component to the basis of the second network data packet, and obtains the second network transmission packet after encapsulation.
The second mii interface is used to send a second network transport packet to the PHY chip according to the second mii interface transmission timing, where the clock frequency of the second mii interface is obtained by shifting and looping back the clock frequency of the first mii interface.
The second mii interface may be any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface, or an sgmii interface, and the data transmission interface of the second embodiment of the present invention is more flexible to select compared with the prior art in which the data transmission interface is a dedicated interface defined by an inherent function chip.
EXAMPLE III
Fig. 3 is a schematic structural diagram of an ethernet adaptive device based on an FPGA according to a third embodiment of the present invention.
Preferably, the ethernet adaptive device based on FPGA of the third embodiment further includes a rate configuration module based on the second embodiment, and a schematic structural diagram of the rate configuration module is shown in fig. 3;
the working process is basically the same as that of the second embodiment, and is not described herein again specifically, but the difference is as follows: after the rate snooping module determines a first transmission rate mode corresponding to the first network transmission packet, the rate configuration module configures the first transmission rate mode to the first mii interface, the ethernet protocol parsing module, the ethernet protocol encapsulation module and the second mii interface, and the first mii interface, the ethernet protocol parsing module, the ethernet protocol encapsulation module and the second mii interface perform corresponding processing according to the received first transmission rate.
The ethernet adaptive device based on FPGA according to the second embodiment and the third embodiment of the present invention receives a first network transmission packet sent by a PHY chip through a first mii interface, determines a first network transmission rate corresponding to the first network transmission packet according to a clock frequency of a first mii interface, performs a series of subsequent processing to obtain a second network transmission packet that needs to be sent to the PHY chip, and sends the second network transmission packet to the PHY chip through a second mii interface according to a time sequence sent by a second mii interface. The clock frequency of the second mii interface is obtained by phase shifting and loopback of the clock frequency of the first mii interface, so that the Ethernet self-adaptation is realized, the stability of the Ethernet self-adaptation is improved by a hardware architecture, and meanwhile, the interface can be flexibly selected and the application adaptability of the interface can be improved by a programmable configuration interface; compared with the chip with the inherent function, the FPGA has more flexible design and stronger portability, and is more easily suitable for various application scenes.
Example four
Fig. 4 is a schematic structural diagram of an ethernet adaptive system based on an FPGA according to a fourth embodiment of the present invention.
As shown in fig. 4, the system includes a PHY chip and the FPGA-based ethernet adaptation apparatus of the second embodiment or the third embodiment, wherein,
the data transmitting end of the PHY chip transmits a first network transport packet to the ethernet adaptation device through the first mii interface, and the data receiving end of the PHY chip receives a second network transport packet transmitted by the ethernet adaptation device through the second mii interface.
The ethernet adaptive system based on the FPGA of the fourth embodiment of the present invention enhances the stability of ethernet adaptation by using a hardware architecture, and the programmable configuration interface enables flexible selection of an interface, thereby improving the application adaptability thereof.
It should be understood that the several embodiments provided by the present invention are merely illustrative and that the disclosed method, apparatus and system may be implemented in other ways. For example, one or more of the modules may be combined or integrated into another system.
While the foregoing is directed to the preferred embodiment of the present invention, the scope of the present invention should not be limited thereto, and it will be understood by those skilled in the art that various equivalent changes and modifications may be made without departing from the spirit and scope of the present invention.
Claims (10)
1. An Ethernet self-adapting method based on FPGA is characterized by comprising the following steps:
receiving a first network transmission packet sent by the PHY chip through a first mii interface;
determining a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface;
according to the first transmission rate mode, carrying out Ethernet protocol analysis on the first network transmission packet to obtain a first network data packet;
converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
and executing corresponding system data processing according to the content of the first network data stream.
2. The FPGA-based ethernet adaptation method according to claim 1, wherein the determining the first transmission rate mode corresponding to the first network transport packet according to the clock frequency of the first mii interface specifically comprises:
and intercepting the clock frequency of the first mii interface through a counter, and determining a first transmission rate mode corresponding to the first network transmission packet according to the intercepted clock frequency.
3. The FPGA-based ethernet adaptation method of claim 1, said performing corresponding system data processing comprising: and generating a second network data stream to be sent to the PHY chip.
4. The FPGA-based Ethernet adaptation method of claim 3, further comprising, after the generating a second network data stream to be sent to the PHY chip:
recombining the second network data stream according to the host byte order and the network byte order to obtain a second network data packet;
according to the first transmission rate mode, packaging the second network data packet through an Ethernet protocol to obtain a second network transmission packet;
transmitting the second network transport packet to the PHY chip through a second mii interface according to a second mii interface transmission timing; the clock frequency of the second mii interface is obtained by phase-shifting and looping the clock frequency of the first mii interface.
5. An ethernet adaptive apparatus based on FPGA, comprising: the device comprises a first mii interface, a rate interception module, an Ethernet protocol analysis module, a data conversion module and a data processing module;
the first mii interface is used for receiving a first network transmission packet sent by the PHY chip;
the rate listening module is configured to determine a first transmission rate mode corresponding to the first network transmission packet according to a clock frequency of the first mii interface;
the Ethernet protocol analysis module is used for carrying out Ethernet protocol analysis on the first network transmission packet according to the first transmission rate mode to obtain a first network data packet;
the data conversion module is used for converting the first network data packet into a first network data stream according to a preset host byte order and a preset network byte order;
and the data processing module is used for executing corresponding system data processing according to the content of the first network data stream.
6. The FPGA-based ethernet adaptation device of claim 5, wherein the rate listening module is configured to determine a first transmission rate mode corresponding to the first network transmission packet according to the clock frequency of the first mii interface, specifically:
the rate listening module listens to the clock frequency of the first mii interface through a counter, and determines a first transmission rate mode corresponding to the first network transmission packet according to the heard clock frequency.
7. The FPGA-based Ethernet adaptive device of claim 5, wherein the performing the corresponding system data processing comprises: and generating a second network data stream to be sent to the PHY chip.
8. The FPGA-based Ethernet adaptive device of claim 7, further comprising a data reassembly module, an Ethernet protocol encapsulation module, and a second mii interface;
the data recombination module is used for recombining the second network data stream according to a preset host byte sequence and a preset network byte sequence to obtain a second network data packet;
the Ethernet protocol encapsulation module is used for encapsulating the second network data packet into a second network transmission packet according to an Ethernet protocol;
the second mii interface is configured to send the second network transport packet to the PHY chip according to a second mii interface transmission timing sequence, where a clock frequency of the second mii interface is obtained by shifting and looping back a clock frequency of the first mii interface.
9. The FPGA-based Ethernet adaptive device of claim 8, wherein the first mii interface is any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface, or an sgmii interface;
the second mii interface is any one of an rgmii interface, an rmii interface, an smii interface, an ssmii interface, a gmii interface, or an sgmii interface.
10. An ethernet adaptive system based on an FPGA, comprising: a PHY chip and an ethernet adaptation device according to any of claims 5 to 9;
the PHY chip is used for sending a network transmission packet to the Ethernet self-adaptive device and receiving the network transmission packet sent by the Ethernet self-adaptive device.
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| CN114301856A (en) * | 2021-12-29 | 2022-04-08 | 上海赫千电子科技有限公司 | Gigabit GMII data transmission method and device based on FPGA |
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| CN112398713A (en) * | 2020-10-22 | 2021-02-23 | 北京和利时系统工程有限公司 | Backboard bus data sending method and device |
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