CN206684543U - A kind of automatic identification based on FPGA and the circuit and system for switching network interface - Google Patents
A kind of automatic identification based on FPGA and the circuit and system for switching network interface Download PDFInfo
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- CN206684543U CN206684543U CN201720480677.9U CN201720480677U CN206684543U CN 206684543 U CN206684543 U CN 206684543U CN 201720480677 U CN201720480677 U CN 201720480677U CN 206684543 U CN206684543 U CN 206684543U
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Abstract
The utility model discloses a kind of automatic identification based on FPGA and switch the circuit and system of network interface, belong to switching control field, how simply technical problems to be solved intelligence for realize the more handover operations between master control and individual equipment；Its circuit includes fpga chip, ethernet PHY interface and network interface, fpga chip includes MUX modules, frame parsing module, Tri Mode Ethernet MAC IP kernels and SGMII IP kernels, network interface, ethernet PHY interface, SGMII IP kernels, Tri Mode Ethernet MAC IP kernels and frame parsing module are sequentially connected one master control parsing loop of composition, and above-mentioned master control parsing loop is a plurality of altogether.The system includes foregoing circuit, equipment and multiple master controls.The utility model can be simply intelligent realize the more handover operations between master control and individual equipment.
Description
Technical field
Switching control field is the utility model is related to, specifically a kind of automatic identification based on FPGA simultaneously switches network interface
Circuit and system.
Background technology
Generally when multiple master controls and individual equipment interact, only a master control is allowed to go control device, only this master control
Release control, other master controls are only possible to operate equipment.Any generally, can be gone that platform master control control selected with hardware switch
Control equipment, this artificial mode is not intelligent enough, troublesome in poeration.
How simple intelligence realizes the more handover operations between master control and individual equipment, is the technology for needing to solve is asked
Topic.
The content of the invention
Technical assignment of the present utility model is the deficiency for more than, there is provided a kind of automatic identification based on FPGA simultaneously switches net
Mouthful circuit and system, to solve, how simple intelligence realizes asking for more handover operations between master control and individual equipment
Topic.
Technical assignment of the present utility model is realized in the following manner：
A kind of automatic identification based on FPGA simultaneously switches the circuit of network interface, including FPGA（Field Programmable
Gate Array, field programmable gate array）Chip, ethernet PHY（English full name is Physical Layer, translator of Chinese
For physical layer）Interface and network interface, fpga chip include MUX modules, frame parsing module, Tri-Mode Ethernet MAC
（For three fast ethernet macs）IP kernel and SGMII（English full name is Serial Gigabit Media Independent
Interface, translator of Chinese are serial media independent interface）IP kernel, network interface, ethernet PHY interface, SGMII IP kernels,
Tri-Mode Ethernet MAC IP kernels and frame parsing module are sequentially connected composition one and can transmit master control order and parse
The master control parsing loop of master control order, above-mentioned master control parsing loop are a plurality of altogether；Frame parsing module in every master control parsing loop
It is connected with MUX modules, corresponding two frames parsing in any two master controls parsing loop in above-mentioned a plurality of master control parsing loop
Module is connected.
In the Reusable Design Methodology of integrated circuit, IP kernel（English full name is Intellectual Property
Core）It is logic unit, the reusable module of chip design to refer to one party provides, form.IP kernel generally has already been through
Design verification, designer are designed based on IP kernel, can shorten the cycle of design.IP kernel can pass through agreement
The opposing party is supplied to by a side, or occupied alone by a side.The concept of IP kernel comes from the patent certificate and source code of product design
Copyright etc., designer can carry out the logic of application specific integrated circuit or field programmable gate array based on IP kernel
Design, to reduce the design cycle.IP kernel is divided into soft core, stone and solid core.Soft core is typically unrelated with technique, there is register to pass
The design code of defeated level hardware description language description, can carry out subsequent design；Stone be the former by logic synthesis, layout,
Series of process file after wiring, there is specific process form, Physical realization；Gu core is then generally between above two
Between person, it can be obtained by the processes such as functional verification, Time-Series analysis, designer in the form of logic gate level netlist
Take.Using IP core design electronic system, it is convenient to quote, and the function of changing primary element is easy.
Wherein, the circuit can connect more master controls, the master control order that every master control is sent by above-mentioned multiple network interfaces
Can be through corresponding network interface, ethernet PHY interface, SGMII IP kernels, Tri-Mode Ethernet MAC IP
Core is sent to frame parsing module and parsed, when the master control order that one of master control is sent for enabled order when, then other frames
Parsing module is placed in reset state, and the master control order parsed exports the resolve command of corresponding frame parsing module via MUX modules,
And then the operation to equipment is realized, after the completion of equipment operation, above-mentioned all frame parsing modules are in running order, are ready to
Receive the enabled order from master control.
Further, totally two, loop of master control parsing, the frame parsing module in every master control parsing loop is and MUX
Module connects, and two frame parsing modules corresponding in two master control parsing loops are connected.
Further, the network interface is RJ45 interfaces.
Further, the Tri-Mode Ethernet MAC IP kernels and SGMII IP kernels are to support
The IP kernel of 10Mbps/100Mbps/1000Mbps network speeds.
A kind of automatic identification based on FPGA simultaneously switches the system of network interface, including one kind described in any one is based on as described above
FPGA automatic identification and circuit, equipment and the multiple master controls for switching network interface, the corresponding master control parsing loop of each master control, often
The network interface of individual master control connects with the network interface in corresponding master control parsing loop, and MUX modules connect with equipment.
A kind of automatic identification based on FPGA of the present utility model simultaneously switches the circuit of network interface and system and has advantages below：
1st, the circuit can connect more master controls by multiple network interfaces, and a master control solution is corresponding with for every master control
Loop is analysed, when the master control order that wherein a master control is sent is enables order, frame parsing module corresponding with other master controls is put
In reset state, after the completion of the operation of equipment, all frame parsing modules are in running order, prepare to receive enabled order, from
And realize automatic identification and switch the function of network interface, without artificially configuring which master control to remove control device using；
2nd, Tri-Mode Ethernet MAC IP kernels and SGMII IP kernels support 10Mbps/ in fpga chip
The network speed supported in 100Mbps/1000Mbps network speeds, the i.e. fpga chip is not limited to one kind, it would be preferable to support a variety of master controls.
Brief description of the drawings
The utility model is further illustrated below in conjunction with the accompanying drawings.
Accompanying drawing 1 is the structured flowchart of a kind of automatic identification based on FPGA of embodiment 1 and the circuit for switching network interface；
Accompanying drawing 2 is the structured flowchart of a kind of automatic identification based on FPGA of embodiment 2 and the system for switching network interface.
Embodiment
With reference to Figure of description and specific embodiment to a kind of automatic identification based on FPGA of the present utility model and switching
The circuit and system of network interface are described in detail below.
Embodiment 1：
As shown in Figure 1, a kind of automatic identification based on FPGA of the present utility model and the circuit of network interface is switched, including
Fpga chip, ethernet PHY interface and network interface, fpga chip include MUX modules, frame parsing module, Tri-Mode
Ethernet MAC IP kernels and SGMII IP kernels, network interface, ethernet PHY interface, SGMII IP kernels, Tri-Mode
Ethernet MAC IP kernels and frame parsing module are sequentially connected composition one and can transmit master control order and parse master control order
Master control parses loop, and above-mentioned master control parses totally two, loop, the frame parsing module in every master control parsing loop with MUX modules
Connection, two master controls parse two frame parsing modules corresponding in loops and are connected.
Wherein, network interface is RJ45 interfaces, and for being connected with the RJ45 interfaces in corresponding master control, reception comes from
The master control order of master control.
Ethernet PHY interface, for receiving the master control order from network interface, and master control order is converted to and is suitable to
The signal of SGMII IP kernels transmission.
SGMII IP kernels can support 10Mbps/100Mbps/1000Mbps network speeds, be connect for receiving from ethernet PHY
The master control order of mouth interface, and master control order is converted into the signal suitable for the transmission of Tri-Mode Ethernet MAC IP kernels.
Tri-Mode Ethernet MAC IP kernels can support 10Mbps/100Mbps/1000Mbps network speeds, receive and
Parallel signal is converted to by serial signal from the master control order of SGMII IP kernels, and by master control order, and by the master control after conversion
Order is sent to frame parsing module.
Frame parsing module receives the parallel master control order from Tri-Mode Ethernet MAC IP kernels, and to master control
Order is parsed, if the master control order is enabled order, parses resolve command.In two frame parsing modules, when it
In the master control order that parses in a frame parsing module for enabled order when, send EN to another parsing module and instruct and cause it
Reset state is placed in, and resolve command is sent to MUX modules, resolve command is sent to equipment, realization pair through MUX modules and set
Standby operation, after master control is complete to equipment operation, two frame parsing modules are placed in working condition.
MUX modules are connected, reception comes from frame parsing module as MUX with the frame parsing module in fpga chip
Resolve command, and resolve command is sent to equipment, to be operated to equipment.
In actual applications, master control can be parsed into the network interface in loop and replace with optical-fiber network according to the demand of master control
Interface, meanwhile, the Tri-Mode Ethernet MAC IP kernels in fpga chip and multiple SGMII IP kernels are replaced with can
Support the IP kernel of gigabit Ethernet.
In the present embodiment, two master control parsing loops are provided with, in actual applications, certain amount can be set according to demand
Network interface, ethernet PHY interface, SGMII IP kernels, Ethernet MAC IP kernels and frame parsing module, above-mentioned is every
Individual network interface, ethernet PHY interface, SGMII IP kernels, Ethernet MAC IP kernels and frame parsing module correspond
And one master control parsing loop of composition is sequentially connected, so as to form a plurality of master control parsing loop, appoint in all frame parsing modules
One frame parsing module of meaning connects with other frame parsing modules, every corresponding master control in master control parsing loop.
A kind of automatic identification based on the FPGA of the present utility model and working method for the circuit for switching network interface is：
A kind of automatic identification based on FPGA simultaneously switches being electrically connected between equipment and Duo Tai master controls of network interface, the electricity
Each network interface connects with the network interface of a corresponding master control in road, and the MUX modules and equipment in the circuit connect
Connect；The master control order that every master control is sent passes sequentially through corresponding network interface, ethernet PHY interface, SGMII IP kernels
It is sent in frame parsing module and is parsed with Tri-Mode Ethernet MAC IP kernels；
When the master control order that wherein master control is sent is enabled order, the master control command analysis is obtained into resolve command,
And EN instructions are sent to another frame parsing module, another frame parsing module is placed in reset state；
Resolve command is sent to MUX modules, and is sent by MUX modules to equipment, and equipment is operated；
After the completion of equipment operation, two frame parsing modules are placed in working condition in the circuit, to be ready to receive
Enabled order.
Embodiment 2：
As shown in Figure 2, a kind of automatic identification based on FPGA and the system of network interface is switched, including two master controls, equipment
And a kind of automatic identification based on FPGA disclosed in two embodiments 1 and switch the circuit of network interface.
Each corresponding master control parsing loop of master control, the network interface of each master control parse with corresponding master control
Network interface connection in loop, MUX modules connect with equipment.
The working method of a kind of automatic identification based on FPGA of the present utility model and the system for switching network interface is：
The master control order that every master control is sent passes sequentially through corresponding network interface, ethernet PHY interface, SGMII
IP kernel and Tri-Mode Ethernet MAC IP kernels are sent in frame parsing module and parsed；
When the master control order that wherein master control is sent is enabled order, the master control command analysis is obtained into resolve command,
And EN instructions are sent to another frame parsing module, another frame parsing module is placed in reset state；
Resolve command is sent to MUX modules, and is sent by MUX modules to equipment, and equipment is operated；
After the completion of equipment operation, two frame parsing modules are placed in working condition in the circuit, to be ready to receive
Enabled order.
By embodiment above, the those skilled in the art can readily realize the utility model.But
It is it should be appreciated that the utility model is not limited to embodiment disclosed above.On the basis of disclosed embodiment,
The those skilled in the art can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (5)
1. a kind of automatic identification based on FPGA simultaneously switches the circuit of network interface, it is characterised in that including fpga chip, ethernet PHY
Interface and network interface, fpga chip include MUX modules, frame parsing module, Tri-Mode Ethernet MAC IP kernels and
SGMII IP kernels, network interface, ethernet PHY interface, SGMII IP kernels, Tri-Mode Ethernet MAC IP kernels and frame solution
Analysis module is sequentially connected composition one and can transmit master control order and parse the master control parsing loop of master control order, above-mentioned master control solution
It is a plurality of altogether to analyse loop；Frame parsing module in every master control parsing loop is connected with MUX modules, and above-mentioned a plurality of master control parses back
Corresponding two frame parsing modules are connected in any two master controls parsing loop in road.
2. a kind of automatic identification based on FPGA according to claim 1 simultaneously switches the circuit of network interface, it is characterised in that institute
Totally two, loop of master control parsing is stated, the frame parsing module that every master control is parsed in loop is connected with MUX modules, two master control solutions
Two frame parsing modules corresponding in analysis loop are connected.
3. a kind of automatic identification based on FPGA according to claim 1 or 2 simultaneously switches the circuit of network interface, it is characterised in that
The network interface is RJ45 interfaces.
4. a kind of automatic identification based on FPGA according to claim 1 or 2 simultaneously switches the circuit of network interface, it is characterised in that
The Tri-Mode Ethernet MAC IP kernels and SGMII IP kernels are that can support 10Mbps/100MBPS/1000MBPS
The IP kernel of network speed.
5. a kind of automatic identification based on FPGA simultaneously switches the system of network interface, it is characterised in that any including such as claim 1-4
A kind of automatic identification based on FPGA described in simultaneously switches circuit, equipment and the multiple master controls of network interface, each master control corresponding one
Bar master control parses loop, and the network interface of each master control connects with the network interface in corresponding master control parsing loop,
MUX modules connect with equipment.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108650100A (en) * | 2018-04-26 | 2018-10-12 | 济南浪潮高新科技投资发展有限公司 | A kind of converter design method of SRIO and network interface |
| CN108737188A (en) * | 2018-05-24 | 2018-11-02 | 郑州云海信息技术有限公司 | A kind of net card failure switching system |
| CN109683550A (en) * | 2018-12-21 | 2019-04-26 | 济南浪潮高新科技投资发展有限公司 | A kind of power on/off system and method |
| CN111131267A (en) * | 2019-12-25 | 2020-05-08 | 博依特(广州)工业互联网有限公司 | Ethernet self-adaption method, device and system based on FPGA |
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2017
- 2017-05-03 CN CN201720480677.9U patent/CN206684543U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108650100A (en) * | 2018-04-26 | 2018-10-12 | 济南浪潮高新科技投资发展有限公司 | A kind of converter design method of SRIO and network interface |
| CN108650100B (en) * | 2018-04-26 | 2020-12-11 | 浪潮集团有限公司 | Method for designing converter of SRIO and network interface |
| CN108737188A (en) * | 2018-05-24 | 2018-11-02 | 郑州云海信息技术有限公司 | A kind of net card failure switching system |
| CN108737188B (en) * | 2018-05-24 | 2021-08-31 | 郑州云海信息技术有限公司 | Network card fault switching system |
| CN109683550A (en) * | 2018-12-21 | 2019-04-26 | 济南浪潮高新科技投资发展有限公司 | A kind of power on/off system and method |
| CN109683550B (en) * | 2018-12-21 | 2021-11-16 | 山东浪潮科学研究院有限公司 | Control method of startup and shutdown system |
| CN111131267A (en) * | 2019-12-25 | 2020-05-08 | 博依特(广州)工业互联网有限公司 | Ethernet self-adaption method, device and system based on FPGA |
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Effective date of registration: 20211103 Address after: 250100 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province Patentee after: Shandong Inspur Scientific Research Institute Co.,Ltd. Address before: 250100 First Floor of R&D Building 2877 Kehang Road, Sun Village Town, Jinan High-tech Zone, Shandong Province Patentee before: JINAN INSPUR HIGH-TECH TECHNOLOGY DEVELOPMENT Co.,Ltd. |
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