CN104536923B - A kind of interference signal collection of multichannel and processing checking system - Google Patents
A kind of interference signal collection of multichannel and processing checking system Download PDFInfo
- Publication number
- CN104536923B CN104536923B CN201410695549.7A CN201410695549A CN104536923B CN 104536923 B CN104536923 B CN 104536923B CN 201410695549 A CN201410695549 A CN 201410695549A CN 104536923 B CN104536923 B CN 104536923B
- Authority
- CN
- China
- Prior art keywords
- chip
- fpga chip
- optical
- extension set
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 title claims abstract description 33
- 239000013307 optical fiber Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000003287 optical effect Effects 0.000 claims description 34
- 239000000835 fiber Substances 0.000 claims description 25
- 238000003491 array Methods 0.000 claims description 18
- 238000004891 communication Methods 0.000 claims description 6
- 238000012937 correction Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 230000006870 function Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000007726 management method Methods 0.000 description 3
- 102100029368 Cytochrome P450 2C18 Human genes 0.000 description 2
- 101000919360 Homo sapiens Cytochrome P450 2C18 Proteins 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Optical Communication System (AREA)
Abstract
The invention discloses a kind of collection of the interference signal of multichannel and processing checking system, it includes collection storage extension set and data dump extension set two parts, described collection storage extension set includes main control computer module, high speed memory modules, AD acquisition modules, optical-fibre channel unit and PMU, and data dump extension set includes dump server and disk array.The invention provides a kind of collection of the interference signal of multichannel and processing checking system, while there is complete collection, real-time storage, playback process and dump processing function, also with the advantages of easy to use, accuracy is strong, reliability is high.
Description
Technical field
The present invention relates to a kind of Signal acquiring and processing to verify system, particularly a kind of multichannel interference signal collection and place
Manage checking system.
Background technology
Data collecting system is the bridge that computer intelligence instrument contacts with extraneous physical world, is the important of acquisition information
Approach.Data acquisition technology refers mainly to the ultra-weak electronic signal from sensor output, through signal condition, analog-to-digital conversion to storage, note
Record the technology involved by this process.With the rapid development of computer and information technology, signal transmit production in people with
Increasingly consequence is occupied in life, but has a factor for influenceing laser propagation effect in the transmitting procedure of signal, that is,
Interference signal.Therefore, interference signal is acquired just extremely important with processing.
Occur various types of signal collection and processing checking system currently on the market, these systems are to usual signal acquisition
Very big convenience is brought, but these systems also have certain limitation.
The interference signal acquisition module of multichannel is most important to be sought to accomplish synchronous acquisition, so how to reduce multichannel
The lock in time of collection, this was also the difficult point and deficiency that present multichannel collecting technology faces with regard to critically important.
Memory module, which improves storage speed and reduces the bit error rate, very big influence to the quality of memory module, to whole
Individual system also plays the role of great, and this is also a major issue in the collection and processing of interference signal.
Signal acquiring and processing checking system is intended to that accuracy height can be accomplished, highly reliable, easy to use, but at present also
While almost neither one has complete collection, real-time storage, playback process and dump processing function, moreover it is possible to which it is accurate to accomplish
Property strong, a kind of multichannel that reliability is high interference signal collection and processing checking system.
The content of the invention
Present invention aims to overcome that the deficiencies in the prior art, there is provided a kind of interference signal collection of multichannel is tested with processing
Card system, while there is complete collection, real-time storage, playback process and dump processing function, also with easy to use, accurate
The advantages of really property is strong, reliability is high.
The technical proposal of the invention is realized in this way：A kind of interference signal collection of multichannel and processing checking system,
It includes collection storage extension set and data dump extension set；The communication ends of described collection storage extension set pass through gigabit Ethernet and number
It is bi-directionally connected according to the communication ends of dump extension set, the data sending terminal of collection storage extension set passes through optical fiber and the number of data dump extension set
Connected according to receiving terminal；
Described collection storage extension set includes main control computer module, multiple high speed memory modules, AD acquisition modules and light
Fine channel unit, the input of described AD acquisition modules receive input signal, high speed memory modules, AD acquisition modules and optical fiber
Channel unit is connected by plate high-speed bus, and high speed memory modules, AD acquisition modules and optical-fibre channel unit also pass through simultaneously
CAN is connected, and described optical-fibre channel unit is connected by PCIe with main control computer module, and optical-fibre channel unit is additionally provided with
To the delivery outlet of data dump extension set output data；
Described data dump extension set includes data dump server and disk array, described data dump server bag
HBA cards and Fiber Interface Card are included, the input of described Fiber Interface Card receives the input signal from collection storage extension set, light
The output of fine interface card is connected by PCIe and HBA cards, and the output of HBA cards is connected by optical fiber interface with disk array.
A kind of interference signal collection of described multichannel and processing checking system, in addition to multiple array antennas and one
Multichannel receiver, the radiofrequency signal of described array antenna received interference signal, output and the multichannel of array antenna receive
Machine is connected, and the output of multichannel receiver is connected with AD acquisition modules.
The number of described high speed memory modules is 4.
Described high speed memory modules are used for storage file system including FLASH arrays, fpga chip, DSP Processor, one
System is used to receive from fpga chip data and is transferred to the optical module of optical port with the NOR FLASH of parameter and one, described
FLASH arrays are connected with fpga chip, and fpga chip is connected by GTX interfaces with external bus, and fpga chip is connect by EMIF
Mouthful be connected with DSP Processor, DSP Processor is connected with pci interface, DSP Processor also by with Ethernet PHY chip and gigabit
Network interface connection；Described NOR FLASH are connected with fpga chip, described optical module one end by GTX interfaces and with FPGA cores
Piece is connected, and the other end is connected with optical port；Described FLASH arrays are the FLASH arrays for employing BCH error correction codings,
FLASH arrays include multigroup FLASH chip, and described multigroup FLASH chip is the chip of pipeline processing architecture, described
FLASH chip is the chip using pair of pages programming technique and the core utilized including multiple timesharing.
Described AD acquisition modules include multi-channel A/D collector, fpga chip, DSP Processor, Ethernet PHY chip, when
Clock manager and crystal oscillator, described multi-channel A/D collector receive the input signal from outside, the output of AD collectors and FPGA
Chip is connected, and fpga chip is connected by GTX interfaces with external bus, and fpga chip also passes through DSP data/address bus and DSP processing
Device is connected, and DSP Processor one end is connected with default pci interface, and the other end is connected by Ethernet PHY chip and gigabit Ethernet
Connect；Input receives the reference signal from crystal oscillator, the output end and multichannel of timer manager to described timer manager all the way
AD collectors connect, and every PCB trace length all the way of timer manager to multi-channel A/D collector is isometric.
Described optical-fibre channel unit includes fpga chip, fiber optical transceiver and Ethernet PHY chip, described FPGA cores
Piece is connected by GTX with plate high-speed bus, and fpga chip is also connected by GTX with fiber optical transceiver, and fiber optical transceiver passes through
Optical port output data, fpga chip are also connected by Ethernet PHY chip with gigabit Ethernet, fpga chip also respectively with PCIe
Bus connects with CAN.
Described Fiber Interface Card includes fiber optical transceiver, fpga chip and PCIe golden fingers, described fpga chip
It is connected with PCIe golden fingers, fpga chip is also connected by fiber optical transceiver with optical port.
High performance industrial computer card of the described main control computer module from the standard CPCI of AD-link companies
CPCI-6210。
Described collection storage extension set also includes a PMU, is responsible for providing the power supply that complete machine needs, uses
AC or D/C power administrative unit receive the dc source that outside 220V AC powers are converted to complete machine other modules needs.
The S30 series of described dump server from association for company, using Intel to strong E5-1600 processors,
And possess PCIe3.0 and PCIe2.0 slots, user can be met to the data transportation requirements between optical channel card and HBA cards.
Disk array selects the SureSAS112 modularization disk storage systems of Legend Company, and main frame connected mode supports FC
With iCISI agreements.
The present invention gain effect be：（1）AD acquisition modules are arrived using same clock source and same trigger source, clock signal
The PCB trace length of each AD devices is strictly isometric, and has also given synchronous triggering signal and synchronizing clock signals to FPGA cores
Piece, synchronization of the fpga chip to multi-channel A/D gathered data receive, and ensure the lock in time that can make multi-channel sampling<0.1ns, carry
The high accuracy of collection；（2）Using multinomial high speed storing technology, storage speed is substantially increased, using BCH error correcting techniques,
Reduce the bit error rate, the bit error rate<10-12, improve the accuracy and reliability of data storage；（3）The present invention, which has, completely to adopt
Collection, real-time storage, playback process or dump processing function, it can complete to use interference signal from each step of processing is collected
It is very convenient.
Brief description of the drawings
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the theory diagram of high speed memory modules；
Fig. 3 is the theory diagram of AD acquisition modules；
Fig. 4 is the theory diagram of optical-fibre channel unit；
Fig. 5 is the theory diagram of Fiber Interface Card；
Fig. 6 is the method flow diagram of the interference signal collection and processing checking of a kind of multichannel.
Embodiment
Technical scheme is further described below in conjunction with the accompanying drawings：A kind of as shown in figure 1, interference signal of multichannel
Collection and processing checking system, it includes collection storage extension set and data dump extension set；The communication of described collection storage extension set
End is bi-directionally connected by the communication ends of gigabit Ethernet and data dump extension set, and the data sending terminal of collection storage extension set passes through light
Fibre is connected with the data receiver of data dump extension set；
Described collection storage extension set includes main control computer module, multiple high speed memory modules, AD acquisition modules and light
Fine channel unit, the input of described AD acquisition modules receive input signal, high speed memory modules, AD acquisition modules and optical fiber
Channel unit is connected by plate high-speed bus, and high speed memory modules, AD acquisition modules and optical-fibre channel unit also pass through simultaneously
CAN is connected, and described optical-fibre channel unit is connected by PCIe with main control computer module, and optical-fibre channel unit is additionally provided with
To the delivery outlet of data dump extension set output data；
Described data dump extension set includes data dump server and disk array, described data dump server bag
HBA cards and Fiber Interface Card are included, the input of described Fiber Interface Card receives the input signal from collection storage extension set, light
The output of fine interface card is connected by PCIe and HBA cards, and the output of HBA cards is connected by optical fiber interface with disk array.
A kind of interference signal collection of described multichannel and processing checking system, in addition to multiple array antennas and one
Multichannel receiver, the radiofrequency signal of described array antenna received interference signal, output and the multichannel of array antenna receive
Machine is connected, and the output of multichannel receiver is connected with AD acquisition modules.
The number of described high speed memory modules is 4.
As shown in Fig. 2 described high speed memory modules are used for including FLASH arrays, fpga chip, DSP Processor, one
Storage file system and the NOR FLASH of parameter and one are used to receiving from fpga chip data and being transferred to the optical mode of optical port
Block, described FLASH arrays are connected with fpga chip, and fpga chip is connected by GTX interfaces with external bus, and fpga chip leads to
EMIF interfaces are crossed to be connected with DSP Processor, DSP Processor is connected with pci interface, DSP Processor also by with ethernet PHY core
Piece and gigabit network interface connection；Described NOR FLASH are connected with fpga chip, described optical module one end by GTX interfaces and
It is connected with fpga chip, the other end is connected with optical port；Described FLASH arrays are the FLASH for employing BCH error correction codings
Array, FLASH arrays include multigroup FLASH chip, and described multigroup FLASH chip is the chip of pipeline processing architecture, institute
The FLASH chip stated is the chip using pair of pages programming technique and the core utilized including multiple timesharing.
Sample frequency more and more higher, this handles and brings larger pressure in real time to rear end；This just locates to data transfer and in real time
Reason proposes higher requirement, such as multistage present invention employs multinomial high speed storing technology in order to meet the needs of real-time storage
Pipelining, pair of pages programming technique and Interleaved programming techniques etc., multi-stage pipeline technology are to use to utilize FLASH cores
The programming time interval of piece, pipeline processing architecture is built using multigroup FLASH chip；Pair of pages programming technique is using single
The pair of pages independence feature of FLASH chip, realizes pair of pages in the unit interval while programs, and program speed can be improved one by this technology
Times；The characteristics of Interleaved programming techniques are then core multiple using one single chip, timesharing utilizes these cores, is deposited so as to realize
The lifting of speed is stored up, highest can meet 1GB/s storage speeds.
Characteristics of the FLASH due to production technology and medium in itself, the BIT mistakes of randomness occur in programming process,
Therefore in order to ensure the use demand of user, the present invention uses real-time error coding techniques, ensures the correctness of data, according to
FLASH user's manual knows, 24 BIT mistakes at most occur in 1080 Byte, the BCH error correction codings that the present invention uses,
1080 Byte can be realized with up to 32 BIT correction process, can farthest meet user's request, make the bit error rate<10-12。
As shown in figure 3, described AD acquisition modules include multi-channel A/D collector, fpga chip, DSP Processor, Ethernet
PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receive the input signal from outside, AD collectors
Output is connected with fpga chip, and fpga chip is connected by GTX interfaces with external bus, and fpga chip is also total by DSP data
Line is connected with DSP Processor, and DSP Processor one end is connected with default pci interface, the other end by Ethernet PHY chip with
Gigabit Ethernet connects；Input receives the reference signal from crystal oscillator to described timer manager all the way, timer manager
Output end is connected with multi-channel A/D collector, and every PCB trace length all the way of timer manager to multi-channel A/D collector is isometric.
As shown in figure 4, described optical-fibre channel unit includes fpga chip, fiber optical transceiver and Ethernet PHY chip, institute
The fpga chip stated is connected by GTX with plate high-speed bus, and fpga chip is also connected by GTX with fiber optical transceiver, optical fiber
Transceiver is also connected by optical port output data, fpga chip by Ethernet PHY chip with gigabit Ethernet, and fpga chip is also
It is connected respectively with PCIe buses and CAN.
As shown in figure 5, described Fiber Interface Card includes fiber optical transceiver, fpga chip and PCIe golden fingers, it is described
Fpga chip is connected with PCIe golden fingers, and fpga chip is also connected by fiber optical transceiver with optical port.
High performance industrial computer card of the described main control computer module from the standard CPCI of AD-link companies
CPCI-6210。
Described collection storage extension set also includes a PMU, is responsible for providing the power supply that complete machine needs, uses
AC or D/C power administrative unit receive the dc source that outside 220V AC powers are converted to complete machine other modules needs.
The S30 series of described dump server from association for company, using Intel to strong E5-1600 processors,
And possess PCIe3.0 and PCIe2.0 slots, user can be met to the data transportation requirements between optical channel card and HBA cards.
Disk array selects the SureSAS112 modularization disk storage systems of Legend Company, and main frame connected mode supports FC
With iCISI agreements.
As shown in fig. 6, the method for the interference signal collection and processing checking of a kind of multichannel corresponding to the present invention, it includes
Following steps：
S1. collection storage：Interference signal is acquired, is converted into data signal, and carry out real-time storage；
S2. data processing：Obtained data signal is handled, including playback process sub-step, data dump sub-step
Rapid and file management sub-step.
Described step S1 includes following sub-step：
S11. signal acquisition：Array antenna takes the radiofrequency signal of interference signal；
S12. signal transmits：The signal of acquisition is transferred to AD acquisition modules, described AD collection moulds by multichannel receiver
The collection of block is multi pass acquisition；
S13. signal is changed：AD acquisition module synchronous acquisitions, and ensure that the sampling clock that every collections of AD all the way use is homologous
Same phase, using synchronous triggering input signal in fpga chip, realize that the synchronization to multi-channel A/D gathered data receives, signal is changed
For data signal, and channel uncertainty calibration is carried out in acquisition module；
S14. signal stores：Digital letter will be collected by plate high-speed bus and be transferred to high speed memory modules, deposited at a high speed
Store up real-time storage of the module to the high-speed data from AD acquisition modules.
Playback process sub-step in described step S2 includes following sub-step：
S211. after receiving data readback order, optical-fibre channel unit reads number by GTX interfaces from high speed memory modules
According to storing data into main control computer module local hard disk by PCIe interface；
S212. the processing software of main control computer module completes the post-processing to playback of data.
Data dump sub-step in described step S2 includes following sub-step：
S221. after receiving data dump order, optical-fibre channel unit reads data from high speed memory modules, turns in data
Under the control for storing up extension set, by data dump to disk array；
S222. dump server is handled data and proof of algorithm.
File management sub-step in described step S2 uses to be stored in customized file system management memory module
Data, In the view of user terminal memory module storage be it is a series of can be deleted as needed, read and format manipulation
File.
The PCB per AD devices all the way of multi-channel A/D collector is to clock track lengths etc. in described AD acquisition modules
It is long.
Described high speed memory modules include FLASH arrays, and described FLASH arrays are to employ BCH Error Correction of Coding skills
The FLASH arrays of art, FLASH arrays include multigroup FLASH chip, and described multigroup FLASH chip is pipeline processing architecture
Chip, described FLASH chip be using pair of pages programming technique and the core utilized including multiple timesharing chip.
Claims (1)
1. a kind of interference signal collection of multichannel and processing checking system, it includes collection storage extension set and data dump point
Machine；The communication ends of described collection storage extension set are bi-directionally connected by the communication ends of gigabit Ethernet and data dump extension set, are adopted
The data sending terminal of collection storage extension set is connected by optical fiber with the data receiver of data dump extension set；
Described collection storage extension set leads to including main control computer module, multiple high speed memory modules, AD acquisition modules and optical fiber
Road unit, the input of described AD acquisition modules receive input signal, high speed memory modules, AD acquisition modules and optical-fibre channel
Unit is connected by plate high-speed bus, and high speed memory modules, AD acquisition modules and optical-fibre channel unit are also simultaneously total by CAN
Line is connected, and described optical-fibre channel unit is connected by PCIe with main control computer module, and optical-fibre channel unit is additionally provided with to number
According to the delivery outlet of dump extension set output data；
Described data dump extension set includes data dump server and disk array, and described data dump server includes
HBA cards and Fiber Interface Card, the input of described Fiber Interface Card receive the input signal from collection storage extension set, optical fiber
The output of interface card is connected by PCIe and HBA cards, and the output of HBA cards is connected by optical fiber interface with disk array；Its feature
It is：The interference signal collection of the multichannel also includes multiple array antennas with processing checking system and a multichannel receives
Machine, the radiofrequency signal of described array antenna received interference signal, the output of array antenna are connected with multichannel receiver, more logical
The output of road receiver is connected with AD acquisition modules；The number of described high speed memory modules is 4；Described high speed storing mould
Block is used for storage file system and the NOR FLASH of parameter and one including FLASH arrays, fpga chip, DSP Processor, one
Individual to be used to receive from fpga chip data and be transferred to the optical module of optical port, described FLASH arrays are connected with fpga chip,
Fpga chip is connected by GTX interfaces with external bus, and fpga chip is connected by EMIF interfaces with DSP Processor, DSP processing
Device is connected with pci interface, DSP Processor also by with Ethernet PHY chip and gigabit network interface connection；Described NOR FLASH
It is connected with fpga chip, described optical module one end is connected by GTX interfaces and with fpga chip, and the other end is connected with optical port；
Described FLASH arrays are the FLASH arrays for employing BCH error correction codings, and FLASH arrays include multigroup FLASH chip,
Described multigroup FLASH chip be pipeline processing architecture chip, described FLASH chip be using pair of pages programming technique simultaneously
The chip of the core utilized including multiple timesharing；Described AD acquisition modules include multi-channel A/D collector, fpga chip, DSP processing
Device, Ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receive the input signal from outside, AD
The output of collector is connected with fpga chip, and fpga chip is connected by GTX interfaces with external bus, and fpga chip also passes through
DSP data/address bus is connected with DSP Processor, and DSP Processor one end is connected with default pci interface, and the other end passes through Ethernet
PHY chip is connected with gigabit Ethernet；Input receives the reference signal from crystal oscillator, clock to described timer manager all the way
The output end of manager is connected with multi-channel A/D collector, and timer manager to multi-channel A/D collector is grown per PCB trace all the way
Spend isometric；Described optical-fibre channel unit includes fpga chip, fiber optical transceiver and Ethernet PHY chip, described FPGA cores
Piece is connected by GTX with plate high-speed bus, and fpga chip is also connected by GTX with fiber optical transceiver, and fiber optical transceiver passes through
Optical port output data, fpga chip are also connected by Ethernet PHY chip with gigabit Ethernet, fpga chip also respectively with PCIe
Bus connects with CAN；Described Fiber Interface Card includes fiber optical transceiver, fpga chip and PCIe golden fingers, described
Fpga chip is connected with PCIe golden fingers, and fpga chip is also connected by fiber optical transceiver with optical port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410695549.7A CN104536923B (en) | 2014-11-27 | 2014-11-27 | A kind of interference signal collection of multichannel and processing checking system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410695549.7A CN104536923B (en) | 2014-11-27 | 2014-11-27 | A kind of interference signal collection of multichannel and processing checking system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104536923A CN104536923A (en) | 2015-04-22 |
| CN104536923B true CN104536923B (en) | 2018-03-23 |
Family
ID=52852453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410695549.7A Active CN104536923B (en) | 2014-11-27 | 2014-11-27 | A kind of interference signal collection of multichannel and processing checking system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104536923B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104363075A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | Digital beam forming technical verification system |
| CN104331637A (en) * | 2014-11-28 | 2015-02-04 | 成都龙腾中远信息技术有限公司 | Digital beam forming technique verification system and data processing method |
| CN104333438B (en) * | 2014-11-28 | 2019-01-04 | 成都龙腾中远信息技术有限公司 | A kind of digital bea mforming technique verification platform data processing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2775683Y (en) * | 2005-03-21 | 2006-04-26 | 中国海洋石油总公司 | Optical fiber interface plate for earth quake exploration data collecting system |
| CN1848064A (en) * | 2005-04-13 | 2006-10-18 | 株式会社日立制作所 | Disk array device and control method therefor |
| CN204203961U (en) * | 2014-11-27 | 2015-03-11 | 成都龙腾中远信息技术有限公司 | A kind of multichannel undesired signal Acquire and process verification system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8878860B2 (en) * | 2006-12-28 | 2014-11-04 | Intel Corporation | Accessing memory using multi-tiling |
| CN102053240B (en) * | 2010-10-26 | 2012-11-07 | 北京理工大学 | Reconnaissance receiving processor for synthetic aperture radar signal |
| CN202563080U (en) * | 2012-05-07 | 2012-11-28 | 中国人民解放军海军702厂 | High-speed data acquisition device based on FPGA and DSP |
-
2014
- 2014-11-27 CN CN201410695549.7A patent/CN104536923B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2775683Y (en) * | 2005-03-21 | 2006-04-26 | 中国海洋石油总公司 | Optical fiber interface plate for earth quake exploration data collecting system |
| CN1848064A (en) * | 2005-04-13 | 2006-10-18 | 株式会社日立制作所 | Disk array device and control method therefor |
| CN204203961U (en) * | 2014-11-27 | 2015-03-11 | 成都龙腾中远信息技术有限公司 | A kind of multichannel undesired signal Acquire and process verification system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104536923A (en) | 2015-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104408009A (en) | System and method for acquiring, processing and verifying method multi-channel interference signal | |
| CN104408008A (en) | Multi-channel interference signal acquiring, processing and verifying method | |
| CN104361374A (en) | Collecting and processing system and method of radio-frequency signals | |
| CN206541145U (en) | A kind of multi channel signals synchronous | |
| CN104536923B (en) | A kind of interference signal collection of multichannel and processing checking system | |
| CN106209693B (en) | High Speed Data Collection Method based on network-on-chip | |
| CN109104260B (en) | The synchronous method of plate card type multichannel data acquisition system | |
| CN104639410A (en) | Design method of field bus optical fiber communication interface | |
| CN104991880B (en) | A kind of FC AE ASM Communication Cards based on PCI E interfaces | |
| CN109075742A (en) | Baud rate calibrates circuit and serial port chip | |
| CN104361143B (en) | A kind of portable data acquisition card and its method | |
| CN107908587A (en) | Real-time data acquisition transmitting device based on USB3.0 | |
| CN104361373A (en) | Collecting and processing method of radio-frequency signals | |
| CN104331637A (en) | Digital beam forming technique verification system and data processing method | |
| CN205750776U (en) | 64 multi-channel high frequency ultrasound data receive-transmit systems based on PCI-E interface | |
| CN202676907U (en) | Multichannel weather radar data collecting device | |
| JP2023553613A (en) | Systems and techniques for line diagnostics | |
| CN204242207U (en) | A kind of Acquire and process system of radiofrequency signal | |
| CN204203961U (en) | A kind of multichannel undesired signal Acquire and process verification system | |
| CN107844447A (en) | Multi-channel serial bus high speed data sampling and processing system and method | |
| CN104361375B (en) | A kind of collection of radiofrequency signal and processing system | |
| CN104954113A (en) | Multichannel data transmission method and system | |
| CN207718361U (en) | PCM signal harvester and system | |
| CN106802781B (en) | Multichannel sound signal collection system based on ARM | |
| CN103064810B (en) | A kind of method that realizes satellite serial communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information |
Inventor after: Xiong Xingzhong Inventor after: Li Mingyu Inventor after: Jiang Weiheng Inventor after: Xu Weiyang Inventor after: Long Ning Inventor before: Long Ning Inventor before: Zhang Xingxing |
|
| CB03 | Change of inventor or designer information | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180212 Address after: 610000 Chengdu high tech Zone (West), West core road, No. 5, No. Applicant after: Chengdu Longteng Zhongyuan Information Technology Co., Ltd. Applicant after: Sichuan University of Science & Engineering Address before: High tech Zone Tianchen road Chengdu City, Sichuan province 610000 No. 88 Applicant before: Chengdu Longteng Zhongyuan Information Technology Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200701 Address after: 570228 No. 58 Renmin Avenue, Hainan, Haikou Co-patentee after: Shen Zhong Patentee after: Zhang Kun Co-patentee after: Wang Xianpeng Address before: 610000 No. 5 West core road, hi tech Zone, Chengdu, Sichuan Co-patentee before: SICHUAN University OF SCIENCE & ENGINEERING Patentee before: CHENGDU LONGTENG ZHONGYUAN INFORMATION TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200709 Address after: 12 / F, building 4, No. 18, Jialing Jiangdong Street, Jianye District, Nanjing City, Jiangsu Province, 210019 Patentee after: Nanjing Xinyan collaborative positioning and Navigation Research Institute Co., Ltd Address before: 570228 No. 58 Renmin Avenue, Hainan, Haikou Co-patentee before: Shen Zhong Patentee before: Zhang Kun Co-patentee before: Wang Xianpeng |
|
| TR01 | Transfer of patent right |