CN204203961U - A kind of multichannel undesired signal Acquire and process verification system - Google Patents
A kind of multichannel undesired signal Acquire and process verification system Download PDFInfo
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- CN204203961U CN204203961U CN201420723565.8U CN201420723565U CN204203961U CN 204203961 U CN204203961 U CN 204203961U CN 201420723565 U CN201420723565 U CN 201420723565U CN 204203961 U CN204203961 U CN 204203961U
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Abstract
The utility model discloses a kind of multichannel undesired signal Acquire and process verification system, it comprises collection and stores extension set and data dump extension set two parts, described collection stores extension set and comprises main control computer module, high speed memory modules, AD acquisition module, optical-fibre channel unit and Power Management Unit, and data dump extension set comprises dump server and disk array.The utility model provides a kind of multichannel undesired signal Acquire and process verification system, while having complete collection, real-time storage, playback process and dump processing capacity, also has easy to use, that accuracy is strong, reliability is high advantage.
Description
Technical field
The utility model relates to a kind of Signal acquiring and processing verification system, particularly a kind of hyperchannel undesired signal Acquire and process verification system.
Background technology
Data acquisition system (DAS) is the bridge that computer intelligence instrument and extraneous physical world contact, and is the important channel of obtaining information.Data acquisition technology mainly refers to the ultra-weak electronic signal exported from sensor, through signal condition, analog to digital conversion to the technology storing, record involved by this process.Along with the develop rapidly of computing machine and infotech, Signal transmissions occupies more and more consequence in production and the life of people, but has a factor affecting laser propagation effect in the transmitting procedure of signal, and that is exactly undesired signal.Therefore, Acquire and process carries out to undesired signal just extremely important.
Now commercially occurred various types of signal Acquire and process verification system, these systems bring very large convenience to usual signals collecting, but these systems also have certain limitation.
Multichannel undesired signal acquisition module is most important will accomplish synchronous acquisition exactly, so the lock in time how reducing multichannel collecting is just very important, this is also that a difficult point facing of present multichannel collecting technology is with not enough.
Memory module improves storage speed and reduces the quality of the bit error rate on memory module very large impact, and also have great effect to whole system, this is also a major issue in the Acquire and process of undesired signal.
Signal acquiring and processing verification system all wishes to accomplish that accuracy is high, reliability is strong, easy to use, but while also almost neither one has complete collection, real-time storage, playback process and dump processing capacity at present, the one multichannel undesired signal Acquire and process verification system that accuracy is strong, reliability is high can also be accomplished.
Utility model content
The utility model object is to overcome the deficiencies in the prior art, a kind of multichannel undesired signal Acquire and process verification system is provided, while there is complete collection, real-time storage, playback process and dump processing capacity, also there is easy to use, that accuracy is strong, reliability is high advantage.
The technical solution of the utility model is achieved in that a kind of multichannel undesired signal Acquire and process verification system, and it comprises collection and stores extension set and data dump extension set; The communication ends that described collection stores extension set is bi-directionally connected by the communication ends of gigabit Ethernet and data dump extension set, gathers the data sending terminal storing extension set and is connected by the data receiver of optical fiber with data dump extension set;
Described collection stores extension set and comprises main control computer module, multiple high speed memory modules, AD acquisition module and optical-fibre channel unit, the input end of described AD acquisition module receives input signal, high speed memory modules, AD acquisition module are connected by high-speed bus between plate with optical-fibre channel unit, high speed memory modules, AD acquisition module are also connected by CAN with optical-fibre channel unit simultaneously, described optical-fibre channel unit is by PCIe and main control computer model calling, and optical-fibre channel unit is also provided with the delivery outlet exporting data to data dump extension set;
Described data dump extension set comprises data dump server and disk array, described data dump server comprises HBA card and Fiber Interface Card, the input end of described Fiber Interface Card receives from gathering the input signal storing extension set, the output of Fiber Interface Card is linked by PCIe and HBA and connects, and the output of HBA card is connected with disk array by optical fiber interface.
Described one multichannel undesired signal Acquire and process verification system, also comprise multiple array antenna and a multichannel receiver, the radiofrequency signal of described array antenna received undesired signal, the output of array antenna is connected with multichannel receiver, and the output of multichannel receiver is connected with AD acquisition module.
The number of described high speed memory modules is 4.
Described high speed memory modules comprise FLASH array, fpga chip, dsp processor, one for memory file system and parameter NOR FLASH and for receiving from fpga chip data and being transferred to the optical module of light mouth, described FLASH array is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is connected with dsp processor by EMIF interface, dsp processor is connected with pci interface, and dsp processor is also by being connected with gigabit network interface with ethernet PHY chip; Described NOR FLASH is connected with fpga chip, and described optical module one end is by GTX interface and be connected with fpga chip, and the other end is connected with light mouth; Described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
Described AD acquisition module comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the input signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, and the other end is connected with gigabit Ethernet by ethernet PHY chip; Described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, and timer manager is isometric to the PCB track lengths on each road of multi-channel A/D collector.
Described optical-fibre channel unit comprises fpga chip, fiber optical transceiver and ethernet PHY chip, described fpga chip is connected by high-speed bus between GTX with plate, fpga chip is also connected with fiber optical transceiver by GTX, fiber optical transceiver exports data by light mouth, fpga chip is also connected with gigabit Ethernet by ethernet PHY chip, and fpga chip is also connected with PCIe bus and CAN respectively.
Described Fiber Interface Card comprises fiber optical transceiver, fpga chip and PCIe golden finger, being connected with PCIe golden finger of described fpga chip, being also connected with light mouth by fiber optical transceiver of fpga chip.
Described main control computer module selects the High performance industrial computer card CPCI-6210 of the standard C PCI of AD-link company.
Described collection stores extension set and also comprises a Power Management Unit, is responsible for the power supply providing complete machine to need, and the 220V AC power using AC or DC Power Management Unit to receive outside is converted to the direct supply that other modules of complete machine need.
Described dump server selects association for the S30 series of company, adopts Intel to strong E5-1600 processor, and possesses PCIe3.0 and PCIe2.0 slot, can meet user to the data transportation requirements between optical channel card and HBA card.
Disk array selects the SureSAS112 modularization disk storage system of Legend Company, and main frame connected mode supports FC and iCISI agreement.
Gain effect of the present utility model is: (1) AD acquisition module adopts same clock source and same trigger source, clock signal is strictly isometric to the PCB track lengths of each AD device, and also given fpga chip by synchronous triggering signal and synchronizing clock signals, fpga chip is to the synchronous reception of multi-channel A/D image data, guarantee can make <0.1ns lock in time of multi-channel sampling, improves the accuracy of collection; (2) adopt multinomial high speed storing technology, substantially increase storage speed, adopt BCH error correcting technique, reduce the bit error rate, bit error rate <10
-12, improve the accuracy and reliability that store data; (3) the utility model has complete collection, real-time storage, playback process or dump processing capacity, can complete to undesired signal from collecting each step of process, very easy to use.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model;
Fig. 2 is the theory diagram of high speed memory modules;
Fig. 3 is the theory diagram of AD acquisition module;
Fig. 4 is the theory diagram of optical-fibre channel unit;
Fig. 5 is the theory diagram of Fiber Interface Card;
Fig. 6 is a kind of method flow diagram of multichannel undesired signal Acquire and process checking.
Embodiment
Further describe the technical solution of the utility model below in conjunction with accompanying drawing: as shown in Figure 1, a kind of multichannel undesired signal Acquire and process verification system, it comprises collection and stores extension set and data dump extension set; The communication ends that described collection stores extension set is bi-directionally connected by the communication ends of gigabit Ethernet and data dump extension set, gathers the data sending terminal storing extension set and is connected by the data receiver of optical fiber with data dump extension set;
Described collection stores extension set and comprises main control computer module, multiple high speed memory modules, AD acquisition module and optical-fibre channel unit, the input end of described AD acquisition module receives input signal, high speed memory modules, AD acquisition module are connected by high-speed bus between plate with optical-fibre channel unit, high speed memory modules, AD acquisition module are also connected by CAN with optical-fibre channel unit simultaneously, described optical-fibre channel unit is by PCIe and main control computer model calling, and optical-fibre channel unit is also provided with the delivery outlet exporting data to data dump extension set;
Described data dump extension set comprises data dump server and disk array, described data dump server comprises HBA card and Fiber Interface Card, the input end of described Fiber Interface Card receives from gathering the input signal storing extension set, the output of Fiber Interface Card is linked by PCIe and HBA and connects, and the output of HBA card is connected with disk array by optical fiber interface.
Described one multichannel undesired signal Acquire and process verification system, also comprise multiple array antenna and a multichannel receiver, the radiofrequency signal of described array antenna received undesired signal, the output of array antenna is connected with multichannel receiver, and the output of multichannel receiver is connected with AD acquisition module.
The number of described high speed memory modules is 4.
As shown in Figure 2, described high speed memory modules comprise FLASH array, fpga chip, dsp processor, one for memory file system and parameter NOR FLASH and for receiving from fpga chip data and being transferred to the optical module of light mouth, described FLASH array is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is connected with dsp processor by EMIF interface, dsp processor is connected with pci interface, and dsp processor is also by being connected with gigabit network interface with ethernet PHY chip; Described NOR FLASH is connected with fpga chip, and described optical module one end is by GTX interface and be connected with fpga chip, and the other end is connected with light mouth; Described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
Sample frequency is more and more higher, and this processes to rear end in real time and brings larger pressure; This just has higher requirement to data transmission and process in real time, in order to meet the demand of real-time storage, the utility model have employed multinomial high speed storing technology, as multi-stage pipeline technology, pair of pages programming technique and Interleaved programming technique etc., multi-stage pipeline technology is the programming time interval with utilizing FLASH chip, adopts many group FLASH chip to build pipeline processing architecture; Pair of pages programming technique is the pair of pages independence feature utilizing single FLASH chip, and realize pair of pages in the unit interval and programme simultaneously, program speed can double by this technology; Interleaved programming technique is then the feature utilizing the multiple core of one single chip, and timesharing utilizes these core, thus realizes the lifting of storage speed, the highlyest can meet 1GB/s storage speed.
FLASH is due to the characteristic of production technology and medium itself, the BIT mistake of randomness is there will be in programming process, therefore in order to ensure the user demand of user, the utility model adopts real-time error coding techniques, ensure the correctness of data, user manual according to FLASH is known, there are at most 24 BIT mistakes in 1080 Byte, the BCH error correction coding that the utility model adopts, the correction process of nearly 32 BIT can be realized to 1080 Byte, farthest can meet consumers' demand, make bit error rate <10
-12.
As shown in Figure 3, described AD acquisition module comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the input signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, and the other end is connected with gigabit Ethernet by ethernet PHY chip; Described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, and timer manager is isometric to the PCB track lengths on each road of multi-channel A/D collector.
As shown in Figure 4, described optical-fibre channel unit comprises fpga chip, fiber optical transceiver and ethernet PHY chip, described fpga chip is connected by high-speed bus between GTX with plate, fpga chip is also connected with fiber optical transceiver by GTX, fiber optical transceiver exports data by light mouth, fpga chip is also connected with gigabit Ethernet by ethernet PHY chip, and fpga chip is also connected with PCIe bus and CAN respectively.
As shown in Figure 5, described Fiber Interface Card comprises fiber optical transceiver, fpga chip and PCIe golden finger, being connected with PCIe golden finger of described fpga chip, being also connected with light mouth by fiber optical transceiver of fpga chip.
Described main control computer module selects the High performance industrial computer card CPCI-6210 of the standard C PCI of AD-link company.
Described collection stores extension set and also comprises a Power Management Unit, is responsible for the power supply providing complete machine to need, and the 220V AC power using AC or DC Power Management Unit to receive outside is converted to the direct supply that other modules of complete machine need.
Described dump server selects association for the S30 series of company, adopts Intel to strong E5-1600 processor, and possesses PCIe3.0 and PCIe2.0 slot, can meet user to the data transportation requirements between optical channel card and HBA card.
Disk array selects the SureSAS112 modularization disk storage system of Legend Company, and main frame connected mode supports FC and iCISI agreement.
As shown in Figure 6, the method for a kind of multichannel undesired signal Acquire and process checking that the utility model is corresponding, it comprises the following steps:
S1. gather storage: undesired signal is gathered, be converted into digital signal, and carry out real-time storage;
S2. data processing: process the digital signal obtained, comprises playback process sub-step, data dump sub-step and file management sub-step.
Described step S1 comprises following sub-step:
S11. signal acquisition: the radiofrequency signal of undesired signal got by array antenna;
S12. Signal transmissions: multichannel receiver is by the Signal transmissions of acquisition to AD acquisition module, and the collection of described AD acquisition module is multi pass acquisition;
S13. signal conversion: AD acquisition module synchronous acquisition, and ensure that each road AD gathers the sampling clock homology homophase used, synchronous trigger input signal is utilized in fpga chip, realize the synchronous reception to multi-channel A/D image data, signal is converted to digital signal, and carries out channel uncertainty calibration in acquisition module;
S14. signal storage: will collect numeral letter by high-speed bus between plate and be transferred to high speed memory modules, high speed memory modules is to the real-time storage of the high-speed data from AD acquisition module.
Playback process sub-step in described step S2 comprises following sub-step:
S211. after receiving data readback order, optical-fibre channel unit reads data by GTX interface from high speed memory modules, by PCIe interface, data is stored into main control computer module local hard disk;
S212. the process software of main control computer module completes the process afterwards to playback of data.
Data dump sub-step in described step S2 comprises following sub-step:
S221. after receiving data dump order, optical-fibre channel unit reads data from high speed memory modules, under the control of data dump extension set, by data dump to disk array;
S222. dump server processes and proof of algorithm data.
File management sub-step in described step S2 adopts the data stored in self-defining file system management memory module, is a series of can deletion as required in the storage of user side memory module, the file of reading and format manipulation.
In described AD acquisition module, the PCB of the AD device on each road of multi-channel A/D collector is isometric to clock track lengths.
Described high speed memory modules includes FLASH array, described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
Claims (7)
1. a multichannel undesired signal Acquire and process verification system, is characterized in that: it comprises collection and stores extension set and data dump extension set; The communication ends that described collection stores extension set is bi-directionally connected by the communication ends of gigabit Ethernet and data dump extension set, gathers the data sending terminal storing extension set and is connected by the data receiver of optical fiber with data dump extension set;
Described collection stores extension set and comprises main control computer module, multiple high speed memory modules, AD acquisition module and optical-fibre channel unit, the input end of described AD acquisition module receives input signal, high speed memory modules, AD acquisition module are connected by high-speed bus between plate with optical-fibre channel unit, high speed memory modules, AD acquisition module are also connected by CAN with optical-fibre channel unit simultaneously, described optical-fibre channel unit is by PCIe and main control computer model calling, and optical-fibre channel unit is also provided with the delivery outlet exporting data to data dump extension set;
Described data dump extension set comprises data dump server and disk array, described data dump server comprises HBA card and Fiber Interface Card, the input end of described Fiber Interface Card receives from gathering the input signal storing extension set, the output of Fiber Interface Card is linked by PCIe and HBA and connects, and the output of HBA card is connected with disk array by optical fiber interface.
2. one according to claim 1 multichannel undesired signal Acquire and process verification system, it is characterized in that: it also comprises multiple array antenna and a multichannel receiver, the radiofrequency signal of described array antenna received undesired signal, the output of array antenna is connected with multichannel receiver, and the output of multichannel receiver is connected with AD acquisition module.
3. one according to claim 1 multichannel undesired signal Acquire and process verification system, is characterized in that: the number of described high speed memory modules is 4.
4. one according to claim 1 multichannel undesired signal Acquire and process verification system, it is characterized in that: described high speed memory modules comprises FLASH array, fpga chip, dsp processor, one for memory file system and parameter NOR FLASH and for receiving from fpga chip data and being transferred to the optical module of light mouth, described FLASH array is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is connected with dsp processor by EMIF interface, dsp processor is connected with pci interface, dsp processor is also by being connected with gigabit network interface with ethernet PHY chip, described NOR FLASH is connected with fpga chip, and described optical module one end is by GTX interface and be connected with fpga chip, and the other end is connected with light mouth, described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
5. one according to claim 1 multichannel undesired signal Acquire and process verification system, it is characterized in that: described AD acquisition module comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the input signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, the other end is connected with gigabit Ethernet by ethernet PHY chip, described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, and timer manager is isometric to the PCB track lengths on each road of multi-channel A/D collector.
6. one according to claim 1 multichannel undesired signal Acquire and process verification system, it is characterized in that: described optical-fibre channel unit comprises fpga chip, fiber optical transceiver and ethernet PHY chip, described fpga chip is connected by high-speed bus between GTX with plate, fpga chip is also connected with fiber optical transceiver by GTX, fiber optical transceiver exports data by light mouth, fpga chip is also connected with gigabit Ethernet by ethernet PHY chip, and fpga chip is also connected with PCIe bus and CAN respectively.
7. one according to claim 1 multichannel undesired signal Acquire and process verification system, it is characterized in that: described Fiber Interface Card comprises fiber optical transceiver, fpga chip and PCIe golden finger, being connected with PCIe golden finger of described fpga chip, being also connected with light mouth by fiber optical transceiver of fpga chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420723565.8U CN204203961U (en) | 2014-11-27 | 2014-11-27 | A kind of multichannel undesired signal Acquire and process verification system |
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| CN201420723565.8U CN204203961U (en) | 2014-11-27 | 2014-11-27 | A kind of multichannel undesired signal Acquire and process verification system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536923A (en) * | 2014-11-27 | 2015-04-22 | 成都龙腾中远信息技术有限公司 | Multichannel interference signal acquisition and processing verification system |
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2014
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536923A (en) * | 2014-11-27 | 2015-04-22 | 成都龙腾中远信息技术有限公司 | Multichannel interference signal acquisition and processing verification system |
| CN104536923B (en) * | 2014-11-27 | 2018-03-23 | 成都龙腾中远信息技术有限公司 | A kind of interference signal collection of multichannel and processing checking system |
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Granted publication date: 20150311 Termination date: 20151127 |