CN202433889U

CN202433889U - Device for serial communication data parity check

Info

Publication number: CN202433889U
Application number: CN 201120532693
Authority: CN
Inventors: 刘中海
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2011-12-19
Filing date: 2011-12-19
Publication date: 2012-09-12
Anticipated expiration: 2021-12-19

Abstract

The utility model relates to a device for serial communication data parity check. The device for serial communication data parity check is realized through a programmable logic device. The programmable logic device uses a D trigger and an exclusive or logic to realize the serial communication data parity check. In the check process, the rising edge of a clock is used for immigrating serial data and exclusive or values output by the front end of the D trigger into the D trigger. The device for serial communication data parity check can realize the parity check of serial communication data in the receiving process and can also add a proper parity check bit to a position at the rear of a data bit. The device has the advantages that the occupied resources are extremely few, the miniaturization design of the product is facilitated and the system integration level is improved.

Description

A kind of device of serial communication data parity check

Technical field

The utility model belongs to the channel coding technology field in the communication system, specially refers to a kind of device of serial communication data parity check.

Background technology

Serial data communication is widely used in the various computer communication system, and for example RS232 standard for serial communication, ethernet communication etc. all relate to serial data communication.In serial communication, usually use parity checking to find the mistake of information transmission.

At present, common serial communication parity checking is mainly through in the system of being integrated in or adopt in the special chip and realize that this mode is easy to use, but is to use the restriction that receives system resource, is unfavorable for system's miniaturization Design, and level of integrated system is not high.

The utility model content

The purpose of the utility model provide a kind of simple, reliable, use the serial communication data parity check device that resource is few, can in PLD, realize, to realize system's miniaturization Design, improve level of integrated system.

For realizing above-mentioned purpose; The device of the serial communication data parity check of the utility model is realized with PLD; This device is to realize with PLD; Comprise a d type flip flop and an XOR in this PLD, two input ends of XOR link to each other with the positive output end of serial data and d type flip flop respectively, and the output terminal of XOR links to each other with the data terminal of d type flip flop.

Said PLD is CPLD or FPGA.

The checking procedure of the serial communication data parity check device of the utility model is following:

(1) clear terminal that uses d type flip flop is with the d type flip flop zero clearing;

(2) the XOR value of at the rising edge of sampling clock the anode of serial data and d type flip flop being exported moves into d type flip flop;

(3) anode of d type flip flop be output as ' 0 ' expression the current serial data of receiving comprise even number ' 1 '; The negative terminal of d type flip flop is output as the current serial data of receiving of ' 0 ' expression and comprises odd number ' 1 '.

The serial communication data parity check device of the utility model uses a d type flip flop and an XOR to realize the serial communication data parity check; Also can be when sending after data bit the suitable PB of affix, can be efficiently, convenient, realize the parity of serial data is checked accurately.Circuit is simple, uses resource few, helps being integrated in the system of various serial communications.

Description of drawings

Fig. 1 is the serial communication parity checking unit principle schematic of the utility model;

Fig. 2 is that serial data receives oscillogram among the utility model embodiment.

Embodiment

Further specify below in conjunction with the embodiment of accompanying drawing the utility model.

The serial communication parity checking unit of the utility model is as shown in Figure 1; Comprise FPGA; Only comprise d type flip flop 1 and an XOR among the FPGA; Two input ends of XOR link to each other with the positive output end of serial data and d type flip flop respectively, and the output terminal of XOR links to each other with the data terminal of d type flip flop, is used to detect and write down the parity of current data.Its checking procedure is following: before transceive data, need user mode removing 4 that d type flip flop 1 state is ' 0 ' clearly, i.e. d type flip flop positive output end even parity check 5 is ' 0 '; D type flip flop carries out XOR at the rising edge of each data sampling clock 3 with serial data 2 and even parity check 5, and its XOR is the result be input in the d type flip flop, as check results.Wherein, the even parity check 5 of carrying out XOR with serial data 2 is even parity checks 5 of the last clock signal of data sampling clock 3.If current serial data 2 is identical with even parity check 5 data, then even parity check 5 is ' 0 ' otherwise is ' 1 '.Its result does, comprises even number ' 1 ' in the data of even parity check 5 for ' 0 ' expression transmitting-receiving, and odd 6 comprises odd number ' 1 ' for the data of ' 0 ' expression transmitting-receiving.

The reception waveform is as shown in Figure 2,21 expression data sampling clock signals among the figure, 22 expression serial datas, the current serial data that receives of 23 expressions, the even parity check of 24 expression current datas.If the data of sending are 10011010; Comprise 7 bit data and 1 digit pair verification, its checking procedure is following: the clear terminal of at first using d type flip flop is with the d type flip flop zero clearing, and the original state that makes d type flip flop is ' 0 '; When first rising edge of 21; 23 data received are ' 1 ', and then the even parity check of current data is exactly data ' 1 ' and the XOR result of d type flip flop original state ' 0 ', and promptly 24 is ' 1 '; And preserve next state to this result as d type flip flop, be used to calculate receive second order digit according to the time even parity check.By that analogy when the 7th rising edge of 21; 23 data received are ' 1 ', and this moment d type flip flop state be exactly d type flip flop data that rising edge is preserved ' 1 ' on 21, then the even parity check of current data is exactly the XOR result of data ' 1 ' and d type flip flop positive output end ' 1 '; Be ' 0 ' this moment 24; That is to say that preceding 7 bit data of receiving have even number ' 1 ', this last digit pair check bit with receiving data is consistent for ' 0 ', representes that this transmission is correct.

The utility model can be realized the parity inspection to serial data efficiently, conveniently, accurately.Circuit is simple, uses resource few, helps being integrated in the system of various serial communications.

Claims

1. serial communication data parity check device; It is characterized in that; This device is to realize with PLD; Comprise a d type flip flop and an XOR in this PLD, two input ends of XOR link to each other with the positive output end of serial data and d type flip flop respectively, and the output terminal of XOR links to each other with the data terminal of d type flip flop.

2. according to the described serial communication data parity check of claim 1 device, it is characterized in that: said PLD is CPLD or FPGA.