CN104361373A - Collecting and processing method of radio-frequency signals - Google Patents
Collecting and processing method of radio-frequency signals Download PDFInfo
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- CN104361373A CN104361373A CN201410695342.XA CN201410695342A CN104361373A CN 104361373 A CN104361373 A CN 104361373A CN 201410695342 A CN201410695342 A CN 201410695342A CN 104361373 A CN104361373 A CN 104361373A
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Abstract
The invention discloses a collecting and processing method of radio-frequency signals. The collecting and processing method of the radio-frequency signals comprises the step of collection and storage and the step of data processing. According to the step of collection and storage, the signals are collected and converted into digital signals, and the digital signals are stored in real time; the step of collection and storage comprises the sub-steps of signal collection, signal transmission, signal conversion and signal storage. According to the step of data processing, the obtained digital signals are processed, and step of data processing comprises the sub-step of playback processing and the sub-step of file management. By means of the collecting and processing method of the radio-frequency signals, the storage speed is greatly improved by adopting a plurality of high-speed storage technologies, the error rate is lowered by adopting the BCH error correction technology, AD modules adopt a same clock source and a same trigger source, the wiring lengths from clock signals to PCBs of AD devices are strictly identical, synchronous collecting time is shortened, and therefore the collecting and processing method of the radio-frequency signals is high in accuracy and high in reliability.
Description
Technical field
The present invention relates to a kind of Acquire and process method of radiofrequency signal.
Background technology
Data acquisition technology is the bridge that computer intelligence instrument and extraneous physical world contact, and is the important channel of obtaining information.Data acquisition technology mainly refers to the ultra-weak electronic signal exported from sensor, through signal condition, analog to digital conversion to the technology storing, record involved by this process.Along with the develop rapidly of computing machine and infotech, Signal transmissions occupies more and more consequence in production and the life of people.
And the Acquire and process method of radiofrequency signal is many times multichannel, RF signal collection and disposal route all wish to accomplish that accuracy is high, and reliability is strong, easy to use.
Multichannel acquisition module is most important will accomplish synchronous acquisition exactly, so the lock in time how reducing multichannel collecting is just very important, this is also that a difficult point facing of present multichannel collecting technology is with not enough.
High speed memory modules improves storage speed and reduces the quality of the bit error rate on memory module very large impact, and also have great effect to whole system, this is also a major issue in the Acquire and process of radiofrequency signal.
RF signal collection and disposal route need to have complete collection and store, data processing step, and are difficult to while intactly having these functions, ensure that the accuracy of data and reliability are the deficiencies in the prior art parts.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of accuracy high, the Acquire and process method of the radiofrequency signal that reliability is strong.
The object of the invention is to be achieved through the following technical solutions: a kind of Acquire and process method of radiofrequency signal, it comprises the following steps:
S1. gather storage: radio frequency signal gathers, and is converted into digital signal, and carry out real-time storage;
S2. data processing: process the digital signal obtained, comprises playback process sub-step and file management sub-step.
Described step S1 comprises following sub-step:
S11. signal acquisition: array antenna obtains radiofrequency signal;
S12. Signal transmissions: multichannel receiver is by the Signal transmissions of acquisition to AD acquisition module, and the collection of described AD acquisition module is multi pass acquisition;
S13. signal conversion: AD acquisition module synchronous acquisition, and ensure that each road AD gathers the sampling clock homology homophase used, synchronous trigger input signal is utilized in fpga chip, realize the synchronous reception to multi-channel A/D image data, signal is converted to digital signal, and carries out channel uncertainty calibration in acquisition module;
S14. signal storage: between plate, high-speed bus will collect numeral letter and be transferred to high speed memory modules, and high speed memory modules is to the real-time storage of the high-speed data from AD acquisition module.
Playback process sub-step in described step S2 comprises following sub-step:
S211. after optical-fibre channel unit receives the data readback order from main control computer module, optical-fibre channel unit reads data by GTX interface from high speed memory modules, by PCIe interface, data is stored into main control computer module local hard disk;
S212. the process software of main control computer module completes the process afterwards to playback of data.
File management sub-step in described step S2 comprises file erase, file reads and document formatting.
In described AD acquisition module, clock signal is isometric to the PCB track lengths of each road AD device of multi-channel A/D collector.
Described high speed memory modules includes FLASH array, described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
The invention has the beneficial effects as follows: (1) AD acquisition module adopts same clock source and same trigger source, clock signal is strictly isometric to the PCB track lengths of each AD device, and also given fpga chip by synchronous triggering signal and synchronizing clock signals, fpga chip is to the synchronous reception of multi-channel A/D image data, guarantee can make <0.1ns lock in time of multi-channel sampling, improves the accuracy of collection; (2) adopt multinomial high speed storing technology, substantially increase storage speed, adopt BCH error correcting technique, reduce the bit error rate, bit error rate <10
-12, improve the accuracy and reliability that store data; (3) the invention provides a kind of complete accuracy high, the Acquire and process method of the radiofrequency signal that reliability is strong.
Accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is a kind of Acquire and process system principle diagram of radiofrequency signal;
Fig. 3 is the theory diagram of high speed memory modules;
Fig. 4 is the theory diagram of AD acquisition module;
Fig. 5 is the theory diagram of optical-fibre channel unit.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 1, a kind of Acquire and process method of radiofrequency signal, it comprises the following steps:
S1. gather storage: radio frequency signal gathers, and is converted into digital signal, and carry out real-time storage;
S2. data processing: process the digital signal obtained, comprises playback process sub-step and file management sub-step.
Described step S1 comprises following sub-step:
S11. signal acquisition: array antenna obtains radiofrequency signal;
S12. Signal transmissions: multichannel receiver is by the Signal transmissions of acquisition to AD acquisition module, and the collection of described AD acquisition module is multi pass acquisition;
S13. signal conversion: AD acquisition module synchronous acquisition, and ensure that each road AD gathers the sampling clock homology homophase used, synchronous trigger input signal is utilized in fpga chip, realize the synchronous reception to multi-channel A/D image data, signal is converted to digital signal, and carries out channel uncertainty calibration in acquisition module;
S14. signal storage: between plate, high-speed bus will collect numeral letter and be transferred to high speed memory modules, and high speed memory modules is to the real-time storage of the high-speed data from AD acquisition module.
Playback process sub-step in described step S2 comprises following sub-step:
S211. after optical-fibre channel unit receives the data readback order from main control computer module, optical-fibre channel unit reads data by GTX interface from high speed memory modules, by PCIe interface, data is stored into main control computer module local hard disk;
S212. the process software of main control computer module completes the process afterwards to playback of data.
File management sub-step in described step S2 comprises file erase, file reads and document formatting.
In described AD acquisition module, clock signal is isometric to the PCB track lengths of each road AD device of multi-channel A/D collector.
Described high speed memory modules includes FLASH array, described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
As shown in Figure 2, use the Acquire and process system of a kind of radiofrequency signal of this method, it comprises main control computer module, multiple high speed memory modules, AD acquisition module and optical-fibre channel unit, the input end of described AD acquisition module receives input signal, high speed memory modules, AD acquisition module is connected by high-speed bus between plate with optical-fibre channel unit, high speed memory modules, AD acquisition module is also connected by CAN with optical-fibre channel unit simultaneously, described optical-fibre channel unit is by PCIe and main control computer model calling, optical-fibre channel unit is also provided with data output.
The Acquire and process system of described a kind of radiofrequency signal also comprises multiple array antenna and a multichannel receiver, described array antenna received radiofrequency signal, the output of array antenna is connected with multichannel receiver, and the output of multichannel receiver is connected with AD acquisition module.
The number of described high speed memory modules is 4.
As shown in Figure 3, described high speed memory modules comprise FLASH array, fpga chip, dsp processor, one for memory file system and parameter NOR FLASH and for receiving from fpga chip data and being transferred to the optical module of light mouth, described FLASH array is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is connected with dsp processor by EMIF interface, dsp processor is connected with pci interface, and dsp processor is also by being connected with gigabit network interface with ethernet PHY chip; Described NOR FLASH is connected with fpga chip, and described optical module one end is by GTX interface and be connected with fpga chip, and the other end is connected with light mouth; Described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
Sample frequency is more and more higher, and this processes to rear end in real time and brings larger pressure; This just has higher requirement to data transmission and process in real time, in order to meet the demand of real-time storage, present invention employs multinomial high speed storing technology, as multi-stage pipeline technology, pair of pages programming technique and Interleaved programming technique etc., multi-stage pipeline technology is the programming time interval with utilizing FLASH chip, adopts many group FLASH chip to build pipeline processing architecture; Pair of pages programming technique is the pair of pages independence feature utilizing single FLASH chip, and realize pair of pages in the unit interval and programme simultaneously, program speed can double by this technology; Interleaved programming technique is then the feature utilizing the multiple core of one single chip, and timesharing utilizes these core, thus realizes the lifting of storage speed, the highlyest can meet 1GB/s storage speed.
FLASH is due to the characteristic of production technology and medium itself, the BIT mistake of randomness is there will be in programming process, therefore in order to ensure the user demand of user, the present invention adopts real-time error coding techniques, ensure the correctness of data, user manual according to FLASH is known, there are at most 24 BIT mistakes in 1080 Byte, the BCH error correction coding that the present invention adopts, the correction process of nearly 32 BIT can be realized to 1080 Byte, farthest can meet consumers' demand, make bit error rate <10
-12.
As shown in Figure 4, described AD acquisition module comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, and the other end is connected with gigabit Ethernet by ethernet PHY chip; Described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, and timer manager is isometric to the PCB track lengths on each road of multi-channel A/D collector.
As shown in Figure 5, described optical-fibre channel unit comprises fpga chip, fiber optical transceiver and ethernet PHY chip, described fpga chip is connected by high-speed bus between GTX with plate, fpga chip is also connected with fiber optical transceiver by GTX, fiber optical transceiver exports data by light mouth, fpga chip is also connected with gigabit Ethernet by ethernet PHY chip, and fpga chip is also connected with PCIe bus and CAN respectively.
Described main control computer module selects the High performance industrial computer card CPCI-6210 of the standard C PCI of AD-link company.
The Acquire and process system of described a kind of radiofrequency signal also comprises a Power Management Unit, is responsible for the power supply providing complete machine to need, and receives the direct supply that outside 220V AC power is converted to other modules of complete machine needs.
Claims (6)
1. an Acquire and process method for radiofrequency signal, is characterized in that: it comprises the following steps:
S1. gather storage: radio frequency signal gathers, and is converted into digital signal, and carry out real-time storage;
S2. data processing: process the digital signal obtained, comprises playback process sub-step and file management sub-step.
2. the Acquire and process method of a kind of radiofrequency signal according to claim 1, is characterized in that: described step S1 comprises following sub-step:
S11. signal acquisition: array antenna obtains radiofrequency signal;
S12. Signal transmissions: multichannel receiver is by the Signal transmissions of acquisition to AD acquisition module, and the collection of described AD acquisition module is multi pass acquisition;
S13. signal conversion: AD acquisition module synchronous acquisition, and ensure that each road AD gathers the sampling clock homology homophase used, synchronous trigger input signal is utilized in fpga chip, realize the synchronous reception to multi-channel A/D image data, signal is converted to digital signal, and carries out channel uncertainty calibration in acquisition module;
S14. signal storage: will collect numeral letter by high-speed bus between plate and be transferred to high speed memory modules, high speed memory modules is to the real-time storage of the high-speed data from AD acquisition module.
3. the Acquire and process method of a kind of radiofrequency signal according to claim 1, is characterized in that: the playback process sub-step in described step S2 comprises following sub-step:
S211. after optical-fibre channel unit receives the data readback order from main control computer module, optical-fibre channel unit reads data by GTX interface from high speed memory modules, by PCIe interface, data is stored into main control computer module local hard disk;
S212. the process software of main control computer module completes the process afterwards to playback of data.
4. the Acquire and process method of a kind of radiofrequency signal according to claim 1, is characterized in that: the file management sub-step in described step S2 comprises file erase, file reads and document formatting.
5. the Acquire and process method of a kind of radiofrequency signal according to claim 2, is characterized in that: in described AD acquisition module, clock signal is isometric to the PCB track lengths of each road AD device of multi-channel A/D collector.
6. the Acquire and process method of a kind of radiofrequency signal according to claim 2, it is characterized in that: described high speed memory modules includes FLASH array, described FLASH array is the FLASH array that have employed BCH error correction coding, FLASH array comprises organizes FLASH chip more, described many groups FLASH chip is the chip of pipeline processing architecture, and described FLASH chip is the chip adopting pair of pages programming technique and comprise the core that multiple timesharing utilizes.
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| CN201410695342.XA CN104361373A (en) | 2014-11-27 | 2014-11-27 | Collecting and processing method of radio-frequency signals |
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| CN106405585A (en) * | 2016-08-29 | 2017-02-15 | 北京华力创通科技股份有限公司 | Radiofrequency signal acquisition playback method and radiofrequency signal acquisition playback device |
| CN107491404A (en) * | 2017-07-17 | 2017-12-19 | 成都普诺科技有限公司 | A kind of signal acquisition and playback system |
| CN111752184A (en) * | 2020-05-20 | 2020-10-09 | 哈船光电(武汉)有限公司 | System and method for synchronously acquiring multiple paths of vibration signals |
| CN113722270A (en) * | 2021-07-20 | 2021-11-30 | 湖南艾科诺维科技有限公司 | Recording playback device and control method thereof |
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| CN113722270A (en) * | 2021-07-20 | 2021-11-30 | 湖南艾科诺维科技有限公司 | Recording playback device and control method thereof |
| CN113722270B (en) * | 2021-07-20 | 2023-07-11 | 湖南艾科诺维科技有限公司 | Recording playback device and control method thereof |
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Application publication date: 20150218 |