CN112213694B - Radar control module and use method thereof - Google Patents

Radar control module and use method thereof Download PDF

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CN112213694B
CN112213694B CN202011379504.0A CN202011379504A CN112213694B CN 112213694 B CN112213694 B CN 112213694B CN 202011379504 A CN202011379504 A CN 202011379504A CN 112213694 B CN112213694 B CN 112213694B
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CN112213694A (en
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林立法
柯贵树
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Nanjing Tianlang Defense Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/282—Transmitters

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a radar control module and a using method thereof, wherein the control module comprises an FPGA module and a modulation module; the FPGA module is used for converting one path of TTL level input signals into n paths of TTL level output signals; the modulation module receives n paths of TTL level output signals transmitted by the FPGA module and controls an output signal Vd through the signals; the amplifying module receives an output signal Vd of the modulating module and controls power amplification through the signal; the phase of an output signal Vd is controlled by controlling the time sequence of inputting TTL level input signals, so that an amplified signal which is not overshot and has symmetrical front edges and back edges is obtained, the frequency spectrum bandwidth occupied by the radar when the radar works in a saturation state is reduced, and the frequency spectrum resources are saved.

Description

Radar control module and use method thereof
Technical Field
The invention relates to the technical field of radars, in particular to a radar control module and a using method thereof.
Background
With the development of microwave technology, the occupied frequency spectrum bandwidth of the traditional radar is also wider and wider, and the frequency spectrum resources are also more and more tense, so that the radar is required to be developed to higher frequency, however, in reality, due to the influence of the development of a power amplifier, the frequency spectrum resources cannot be developed to higher frequency infinitely, and at the present stage, a terahertz microwave device appears, but the large-scale application of the terahertz microwave device is influenced again by small output power and design difficulty.
At the present stage, except for a small part of radars such as communication radars, most radars adopt a power amplifier device which takes saturated amplification as an amplification mode. Due to the characteristics of the power amplifier device, when the power amplifier device works in a saturation state, the spectrum bandwidth (such as 6dB and 10dB bandwidth) of the power amplifier device is widened, so that the spectrum bandwidth occupied by the radar is wider than that actually needed at the moment, and spectrum resources are wasted.
In addition, in the current radar design, most radars are multi-stage amplification, that is, the input power is amplified by multi-stage power to obtain the output power, the working time of each power amplifier is controlled by the grid voltage of a power tube, the grid voltage is generated by a TTL modulation circuit, the input low-power signal is amplified by multi-stage power to obtain the output signal, and the working time of a power amplifier module is controlled by a TTL level. Due to the characteristics of the power amplifier, the leading edge of the amplified signal will overshoot and the leading edge and the trailing edge will not be consistent. The existing radar only comprises a modulation module and an amplification module, and a time sequence control means is not applied to the radar.
Chinese patent document No. CN 102170277 a in 2011.08.31 discloses a method for obtaining picosecond precision narrow pulse width TTL signals based on phase shift phase inversion, which divides TTL signals into two parts, delays one of the two parts and makes the two parts of signals pass through a logic and gate to perform logic phase inversion operation, thereby compressing pulse width, implementing pulse width compression of pulse laser trigger signals or ICCD trigger signals in range gated imaging, and separately processes the two parts of TTL signals, but not processes the time sequence of leading edge and trailing edge, the circuit is slightly complex and is not applied to the radar field, and the problems of overshoot and spectrum asymmetry of radar multi-stage amplified signals are not solved.
Chinese patent document No. CN 109743045 a discloses "logic level jump detection and adjustable width narrow pulse generating circuit" in 2019.05.10, an output signal of the logic level jump detection and adjustable width narrow pulse generating circuit is output from an output port of an xor gate to obtain a narrow pulse signal with a certain pulse width, so as to solve the problem of interference immunity of wireless transmission signals, the logic circuit is used to control the pulse signal, which is different from singly controlling TTL time sequence, the circuit is slightly complex, and is not applied to the radar field, and the problem of too wide spectrum bandwidth occupied by radar and the problem of wasting spectrum resources is not solved.
Chinese patent document No. CN 106059522B discloses "a method and a circuit for controlling a power amplifier without overshoot", which sets a large attenuation value for an electrically tunable attenuator to attenuate a signal to a proper level, thereby solving the problem of avoiding overshoot of output power.
Chinese patent document No. CN 104777457B discloses "a frequency scanning beam timing control apparatus and a control method thereof" to implement timing control and beam control by a signal processor and a communication apparatus. The time sequence control inevitably affects the waveform, the patent does not disclose a control module, and does not apply the time sequence control to the voltage of the modulating radar, and simultaneously does not solve the problems that the frequency spectrum bandwidth occupied by the radar is too wide and the frequency spectrum resources are wasted.
Disclosure of Invention
The invention provides a radar control module and a using method thereof aiming at the condition that the occupied frequency spectrum bandwidth of a radar is large when the radar works in a saturation state, and aims to control the amplified signal frequency spectrum by controlling the time sequence of TTL level signals so as to achieve the purpose of reducing the frequency bandwidth.
The scheme of the invention is as follows:
a radar control module comprises an amplification module, an FPGA module and a modulation module;
the FPGA module comprises an I/O unit and a time sequence unit, wherein the I/O unit is used for converting one path of TTL level input signals into n paths of TTL level output signals, and the time sequence unit controls the time sequence of the TTL level output signals;
the modulation module receives n paths of TTL level output signals transmitted by the FPGA module and controls the time sequence of an output signal Vd through the time sequence of the TTL level output signals;
the amplifying module receives the output signal Vd of the modulating module and outputs an RFout signal as the working voltage of the amplifying module.
Preferably, the FPGA module includes a TTL level input port and n TTL level output ports, and is connected to the n modulation modules through the n TTL level output ports.
Preferably, the FPGA module further includes a CLOCK signal, and a CLOCK square-wave signal is input through a CLOCK signal port for realizing timing synchronization of the control module.
Preferably, the modulation module further comprises a VCC input port, a VIN input port and a VD output port, the VCC input port is connected to the power voltage, the VIN input port is connected to the signal voltage, and the VD output port is connected to the amplification module.
Preferably, the amplifying module comprises an RFout output port, and the n amplifying modules are sequentially cascaded through the RFout output port to realize multi-stage amplification.
The invention also provides a use method of the radar control module, and by using the radar control module disclosed by the invention,
accessing a TTL level signal with a signal width of t1 to a TTL level input port of an FPGA module, and realizing signal synchronization through a synchronous CLOCK (CLOCK) signal;
step two, when the rising edge of the input signal of the 1 st TTL level arrives, the high level is input after the time of delaying T1, when the falling edge of the TTL level arrives, the low level is input after the time of delaying T1, the same conversion is carried out in the next period, and the TTL is obtained1Outputting the signal;
step three, inputting high level when rising edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, inputting low level when falling edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, and performing same conversion in next period to obtain TTL2、TTL3……TTLn-1Outputting the signal;
step four, when the rising edge of the nth TTL level comes, inputting a high level and keeping the high level for T1-T2 time, and carrying out the same conversion in the next period to obtain the TTLnAnd outputting the signal.
Step five, generating n paths of TTL output signals and input voltage VIN by the FPGAxRespectively used as input signals of n modulation modules to obtain n paths of modulation pulse signals VdxWherein x is 1, 2 … … n;
step six, VdxAs the working voltage of each stage of amplifier, and inputting RFin signal as the radio frequency input signal of each stage of amplifier to control the output signal RFout of amplifierxWhere x is 1, 2 … … n.
Preferably, TTL2……TTLn-1Is a signal with the same amplitude and phase as the TTL level input signal.
Preferably, TTL1And TTLnThe signal is a signal having the same amplitude as the input signal of the TTL level and different in phase from each other by T1 and T2.
Preferably, the pulse signal Vd is modulatedxIs equal to the input voltage VINxSquare wave signals of equal amplitude, where x is 1, 2 … … n, by varying the input voltage VINxTo change the magnitude of the modulated pulse signal VdxThereby changing the magnitude of the radar output power.
Preferably, the sum of the TTL level rising edge time and the overshoot time is H1, and the TTL level falling edge time of the n-stage amplification is L1, T1 is H1, and T2 is T1-L1.
Has the advantages that:
(1) according to the invention, TTL time sequence control is applied to the radar, the output signal Vd of the radar modulation module is skillfully controlled, only the FPGA module is additionally arranged, the design cost is low, and the industrial popularization is easy.
(2) The invention cuts off the overshoot part in the radar output signal by adjusting the T1 time, thereby reducing the occupied frequency spectrum bandwidth when the radar actually works and greatly saving the frequency spectrum resource.
(3) According to the invention, by adjusting the time of T2, the rising edge and the falling edge of the output signal of the radar tend to be symmetrical, namely, the left and the right of the frequency spectrum tend to be symmetrical in the frequency domain, and the quality of the output frequency spectrum is excellent.
(4) The invention only needs to adjust TTL1And TTLnThe phase of the frequency spectrum can realize the symmetry of the frequency spectrum, the bandwidth can be reduced without a logic circuit, the operation is simple, and the popularization and the operation are easy.
Drawings
FIG. 1 is a schematic diagram of a radar control circuit according to an embodiment of the present invention;
FIG. 2 shows a TTL according to an embodiment of the invention1A schematic diagram of the output signal;
FIG. 3 shows a TTL according to an embodiment of the invention2、TTL3......TTLn-1A schematic diagram of the output signal;
FIG. 4 shows a TTL according to an embodiment of the inventionnA schematic diagram of the output signal;
FIG. 5 is a schematic circuit diagram of a modulation module according to an embodiment of the present invention;
FIG. 6 is a signal diagram of a modulation module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of n modulated pulses according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of the raw RFout detection signal according to one embodiment of the present invention;
FIG. 9 is one of the present inventionRFout of an embodiment1A detection signal schematic diagram;
FIG. 10 shows an embodiment of the present invention, RFoutxA detection signal schematic diagram;
FIG. 11 is an RFout of an embodiment of the present inventionnA detection signal schematic diagram;
FIG. 12 is an RFout of an embodiment of the present inventionnSchematic comparison before and after detection signal processing.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a system and a method for reducing the working bandwidth of a radar aiming at the condition that the radar occupies a large frequency spectrum bandwidth when working in a saturation state, and aims to change the working time of each power amplification module by controlling TTL level signals so as to control the frequency spectrum of amplified signals and achieve the purpose of reducing the frequency bandwidth.
Fig. 1 is a schematic diagram of the operation of the radar control module of the present invention. A radar control module comprises an FPGA module, a modulation module and an amplification module. The FPGA module comprises a TTL level input port, a synchronous CLOCK CLOCK port and n TTL level output ports, wherein an I/O unit of the FPGA module is used for converting input TTL level input signals into n TTL level output signals and carrying out CLOCK synchronization of the whole circuit through the synchronous CLOCK CLOCK signals of the time sequence unit. The modulation module comprises a TTL level input port, a VCC input port, a VIN input port and a VD output port, wherein the TTL level input port is connected with an n-path TTL level output port output by the FPGA module, the VCC input port is connected with power supply voltage, the VIN input port is connected with signal voltage, and the VD output port is connected with the amplification module. The amplifying module comprises an RFin input port, an RFout output port and a VE input port, the RFin is connected with a radio frequency input signal, the VE is connected with a transmitting stage voltage, the RFout output port outputs a radio frequency output signal, and the n amplifying modules are sequentially cascaded through the RFout output port to realize multi-stage amplification.
The invention also provides a use method of the radar control circuit, which uses the radar control module disclosed by the invention to:
step one, a TTL level signal with a signal width of t1 is accessed to a TTL level input port of the FPGA module, and signal synchronization is achieved through a synchronous CLOCK CLOCK signal.
Step two, when the rising edge of the input signal of the 1 st TTL level arrives, the high level is input after the time of delaying T1, when the falling edge of the TTL level arrives, the low level is input after the time of delaying T1, the same conversion is carried out in the next period, and the TTL is obtained1And outputting the signal. As shown in FIG. 2, the TTL of the present invention1Output signal schematic, TTL1The phase of the output signal is shifted back by T1 cells compared to the phase of the input TTL level.
Step three, inputting high level when rising edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, inputting low level when falling edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, and carrying out same conversion in next period to obtain TTL2、TTL3……TTLn-1And outputting the signal. As shown in FIG. 3, the TTL of the present invention is2、TTL3......TTLn-1Output signal schematic, TTL in figurexThe value of x is in the range of 2 and 3 … … n-1. TTL (transistor-transistor logic)2、TTL3......TTLn-1The output signal is phase-synchronized with the signal at the TTL input level, is equal in amplitude, and has a pulse width of t1 cells.
Step four, when the rising edge of the nth TTL level comes, inputting a high level and keeping the high level for T1-T2 time, and carrying out the same conversion in the next period to obtain the TTLnAnd outputting the signal. As shown in FIG. 4, it is TTL of the present inventionnOutput signal schematic, TTLnThe output signal is synchronous in the leading edge compared with the TTL input level, but the trailing edge is advanced by T2 units, and the pulse width is T1-T2 units.
Step (ii) ofFifthly, the n TTL output signals and the input voltage VIN generated by the FPGAxRespectively used as input signals of n modulation modules to obtain n paths of modulation pulse signals VdxWhere x is 1, 2 … … n. As shown in fig. 5, as a schematic circuit diagram of the modulation module, the modulation module uses an XCM670 high-power and high-voltage type modulation switch, an N-channel MOSFET with extremely small on-resistance is built in the modulation switch, which is helpful to reduce the loss of the system and improve the reliability of the operation, and the MOSFET built in the modulation switch can quickly respond to an external TTL modulation signal to realize the quick rise and fall of the output voltage. The module is internally provided with a bleeder circuit, so that the falling edge of the output voltage can be accelerated. The circuit is simpler while the conduction loss is greatly reduced. VIN of XCM670 high-power and high-voltage type modulation switch is input power pin, and in order to prevent high-frequency interference, at least C is connected between the pin and the groundINIs a 4.7uF ceramic capacitor. Because VD pin is directly connected to drain electrode of GaN power amplifier, in order to prevent interference of radio frequency signal to modulation module, C is placed between VD pin and GNDVDThe capacitor is 1nF, because of the influence of the power amplifier microstrip line, a voltage peak suppression capacitor is added at the position of the power amplifier drain electrode, but the capacitor additionally increases the loss of a bleeder circuit, and the capacitance value of the power amplifier drain electrode port to the ground is set to be not more than 0.1uF while the microstrip line is reasonably designed. VIN voltage range is 8V to 80V, TTL signal input pin is connected with n TTL output signals of FPGA module, Vd is output signal, and pulse voltage synchronous with TTL signal time sequence is provided by inputting TTL signal. As shown in fig. 6, a signal diagram of a modulation module is shown, where VIN is an input voltage waveform, TTL is a TTL level input waveform, Vd is a modulation module output voltage waveform, the rise times of VIN input signals, TTL level input signals, and Vd output signals are the same, the timings of TTL level input signals and Vd output signals are the same, Vh1 is the amplitude of the power input signal VIN, and Vh2 is the amplitude of Vd, so Vh1 is equal to Vh 2.
Step six, VdxAs the working voltage of each stage of amplifier, and inputting RFin signal as the radio frequency input signal of each stage of amplifier to control the output signal RFout of amplifierxWhere x is 1, 2 … … n. Such asFIG. 7 is a schematic diagram of n-channel modulated pulse signals, Vd1、Vd2……VdnAmplitude is respectively equal to VIN1、VIN2……VINnEqual amplitude one-to-one correspondence, TTLxIn synchronization with the TTL level input signal, where x is 2,3 … … n-1. TTL (transistor-transistor logic)1Level control Vd1Signal, therefore Vd1Phase-delayed TTL level of signal input signal T1 units, Vd2、Vd3……Vdn-1Is in accordance with the phase of the TTL level input signal, VdnPhase at the falling edge advances the TTL level input signal by T2 units at the falling edge, and VdnHas a pulse width of T1-T2. Let H1 be the sum of the rising edge and the overshoot time of the 1-stage amplification and L1 be the falling edge time of the n-stage amplification, then T1 is H1 and T2 is T1-L1. In practical application, fine adjustment can be performed according to a test result, so that the falling edge and the rising edge tend to be symmetrical.
As shown in fig. 8, which is a schematic diagram of the unprocessed RFout detection signal, the input rf signal RFin is a sine wave, the output RFout rf signal exhibits an overshoot phenomenon, and the detected signal image of the RFout signal is an impulse signal with an overshoot and an asymmetry. At this time, the spectrum signal will be widened, resulting in the waste of spectrum resources.
By using the method disclosed by the invention, each Vd is used as the working voltage of each stage of amplification module.
First, TTL is controlled1Signals to control Vd1Signal to thereby obtain RFout1Signal:
TTL to be delayed1After the signal is used for controlling the drain voltage of the 1-stage amplification module, the drain voltage of the amplification module is Vd1The output signal of the amplifying module is RFout1The leading edge of the signal, regardless of other influences, is TTL-ed1Signal impact, RFout can be controlled by changing the value of T1, controlling the rising edge of the amplifier's drain voltage1The rising edge of the radio frequency signal.
Shown in FIG. 9 as RFout1Schematic diagram of the detected signal, RFout1After the signal passes through the detector, its rising edgeSignificantly slower than the falling edge, i.e. the rise time is greater.
Second, TTL is controlled2、TTL3……TTLn-1Signals to control Vd2、Vd3……Vdn-1Signal to thereby obtain RFout2、RFout3……RFoutn-1Signal:
TTL to be synchronized with TTLxThe output signal is used for controlling the drain voltage of the x-stage amplifier, and the drain voltage of the amplifier is VdxThe amplifier output signal is RFoutxSignal due to TTLxIn synchronization with the TTL input signal, where x is 2,3 … … n-1, the detection signal of the output signal generated by amplification theoretically has its waveform unchanged except for its amplitude.
Shown in FIG. 10 as RFoutxSchematic diagram of the detected signal, see, input signal RFout of the n-stage amplifiern-1And RFout1The waveform of the signal is unchanged except for the amplitude.
Finally, TTL is controllednSignals to control VdnSignal to thereby obtain RFoutnSignal:
TTL to be lead aheadnThe output signal of the amplifier is RFout after the signal is used for controlling the drain voltage of the n-stage amplifiernThe amplifier drain voltage is VdnRFout at this time without considering the influence of other factorsnWill be subjected to TTLnThe signal influence. The drain voltage Vd of the amplifier can be controlled by changing the value of T2 at this timenTo control RFoutnThe falling edge of the radio frequency signal.
Shown in FIG. 11 as RFoutnDetection signal diagram, VdnThe falling edge of the TTL level signal is advanced by T2 units to obtain RFoutnThe falling edge of the detected signal is more gradual.
Shown in FIG. 12 as RFoutnSchematic comparison before and after detection signal processing, processed RFoutnThe output waveform obtained after the signal is detected by the detector can achieve the effect of almost symmetrical rising edge and falling edge. Conventional radars typically have rising edges on the order of one or two hundred nanosecondsOn the right, the falling edge is generally in tens of nanoseconds to tens of nanoseconds due to the fast discharge of the modulation circuit and the self influence of the power tube, and the symmetrical effect of the rising edge and the falling edge cannot be achieved. By utilizing the application method of the radar control module disclosed by the invention, the frequency spectrum characteristic can be improved in a frequency domain, so that the reduction of 3dB, 6dB and other frequency spectrum bandwidths is realized, and the complete left-right symmetry of a frequency spectrum can be realized theoretically.
For verifying the correctness of the patent, the patent utilizes three-level amplification to carry out experiments, the frequency range is 2.7-3.1 GHz, and the test frequency point is 2.7 GHz. The sum of the rising edge and the overshoot time of the 1-level amplification is 90ns, and the falling edge time of the 3-level amplification is 20 ns. Theoretically, T1-90 ns and T2-70 ns. In practical application, fine adjustment can be performed according to a test result, so that the falling edge and the rising edge tend to be symmetrical.
By adjustment, T1 is finally set to 100ns and T2 is finally set to 80 ns.
The results of the actual test are shown in Table 1:
TABLE 1 comparison of bandwidth before and after processing
Figure GDA0002907253040000081
Figure GDA0002907253040000091
According to the comparison result, it can be seen that the bandwidths of 6dB, 20dB, 40dB and the like are obviously reduced under the condition that the output main frequency width is unchanged after the output signal is processed, and the frequency spectrum resource is saved.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. A method for using a radar control module is characterized in that: using a radar control module comprising an amplification module, an FPGA module and a modulation module,
the FPGA module comprises an I/O unit and a time sequence unit, wherein the I/O unit is used for converting one path of TTL level input signals into n paths of TTL level output signals, and the time sequence unit controls the time sequence of the TTL level output signals;
the modulation module receives n paths of TTL level output signals transmitted by the FPGA module and controls the time sequence of an output signal Vd through the time sequence of the TTL level output signals;
the amplifying module receives an output signal Vd of the modulating module, takes the output signal Vd as the working voltage of the amplifying module and outputs an RFout signal;
accessing a TTL level signal with a signal width of t1 to a TTL level input port of an FPGA module, and realizing signal synchronization through a synchronous CLOCK (CLOCK) signal;
step two, when the rising edge of the input signal of the 1 st TTL level arrives, the high level is input after the time delay of T1, when the falling edge of the 1 st TTL level arrives, the low level is input after the time delay of T1, the same conversion is carried out in the next period, and the TTL is obtained1Outputting the signal;
step three, inputting high level when rising edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, inputting low level when falling edge of 2 nd and 3 rd … … th n-1 th TTL level input signals arrives, and performing same conversion in next period to obtain TTL2、TTL3……TTLn-1Outputting the signal;
step four, when the rising edge of the nth TTL level comes, inputting a high level and keeping the high level for T1-T2 time, and carrying out the same conversion in the next period to obtain the TTLnOutputting the signal;
step five, generating n paths of TTL output signals and input voltage VIN by the FPGAxRespectively used as input signals of n modulation modules to obtain n paths of modulation pulse signals VdxWherein x is 1, 2 … … n;
step six, VdxAs the working voltage of each stage of amplifier, and inputting RFin signal as the radio frequency input signal of each stage of amplifier to control the output signal RFout of amplifierxWhere x is 1, 2 … … n.
2. The method of claim 1, wherein the radar control module is configured to: step three, the TTL2……TTLn-1The input signal is a signal with the same amplitude and phase as the input TTL level signal.
3. The method of claim 2, wherein the radar control module is configured to: the TTL1And TTLnThe signal is a signal having the same amplitude as the input signal of the TTL level and different in phase from each other by T1 and T2.
4. The method of using a radar control module of claim 3, wherein: said modulated pulse signal VdxIs equal to the input voltage VINxSquare wave signals of equal amplitude, where x is 1, 2 … … n, by varying the input voltage VINxTo change the magnitude of the modulated pulse signal VdxThereby changing the magnitude of the radar output power.
5. The method of using a radar control module of claim 4, wherein: the sum of the rising edge time and the overshoot time of the TTL level is H1, the falling edge time of the TTL level of the n-stage amplification is L1, T1 is H1, and T2 is T1-L1.
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