JPS61226669A - Direction signal multiplying circuit of radar antenna - Google Patents

Abstract

PURPOSE:To form the communications circuit of a duty ratio which can be optionally adjusted by constituting the circuit of an input signal inverting device, a frequency dividing circuit, a signal wave detecting device and an integrating circuit. CONSTITUTION:TTL gates IC 1-7 are integrators composed of an input signal inverting device 1, edge detecting devices 3, 4, 6 and 7, a frequency dividing circuit 8 composed of the flip-flop of the negative edge trigger, a detecting device 9, a resistance R and a capacitor C. When the period stipulated by an integrating circuit R1 C1 is smaller than a period T of the input signal, T is changed to the frequency higher than the period T, and then, the voltage of an (e) point is 1/2 of a C point, and therefore, the frequency two times as much as the input signal can be generated. Provided that the upper limit of the frequency is determined by the limit of the gain of the detecting device 9. By increasing the input voltage to an integrating circuit R1, the reference voltage of the detecting device 9 rises, and the margin for the noise can be made large.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an azimuth signal multiplier circuit for a radar antenna, and is capable of increasing the resolution by 9 without changing the rotational azimuth signal generator. It is something.

(Prior Art) Conventionally, this type of device uses a phase-locked loop (PL).
L) devices, or two-phase signals with different phase shifts of 90°.

(Problems to be solved by the invention) The circuit using the above-mentioned PLL device is complicated;
The latter is not economical (and the latter has poor precision in the phase shift angle between the two phases and the precision in the duty ratio, which poses a problem in improving functionality).

In contrast to such conventional techniques, there has been a need for an economical and highly accurate means for multiplication of signals of radar antennas.

(Means for Solving the Problems) The present invention provides a transmitting circuit with an arbitrarily adjustable duty ratio by comprising an input signal inverter, a nine-channel divider, a signal wave detector, and an integrating circuit. This will be explained in detail below with reference to the drawings.

(Embodiment) FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part of FIG. 1. In Figure 1, 1 to 7 are TTL
game) IC, 1 is input signal inverter, 3, 4, 6.7
8 is an edge detector, 8 is a divider made of a negative edge trigger flip-flop, 9 is a detector, R is a resistor, and C is an integrator made of a capacitor. Next, the operation is as follows: The antenna direction signal (Fig. 2 g) is input to the input terminal point a, and the inverted signal (Fig. 2 b) is input to the input signal inverter 1 at point b.
). Furthermore, frequency 7 of the input wave (FIG. 2C) is obtained by the splitter 8 with a duty of 50%. Next, a resistor R1 whose time constant is 9 times larger than the period T of the input signal (Fig. 2g),
The signal passing through the first integrating circuit of the capacitor C1 is as shown in FIG.
is input to the positive phase input of On the other hand, the signal (Fig. 2 e) obtained by inputting it to a second integrating circuit composed of a resistor R2 and a capacitor C2 with a time constant sufficiently larger than the period T of the integral signal (Fig. 2 d) is Input to the negative phase input of the detector 9. As a result, the output of the detector 9 (FIG. 2 f) is a signal (FIG. 2 f) with a phase shift of 90° relative to the 1/2 frequency signal (FIG. 2 C). The falling edge of the f signal is detected by the detector 3 to obtain a signal (Fig. 2 g), and the rising edge thereof is detected by the detector 4 to obtain a signal (Fig. 2 h). Further, the falling edge of the signal at point b (FIG. 2b) is detected by the detector 6 to obtain the signal (FIG. 2i). Signal (Fig. 2g +
h + 1 ) is formed based on the rising edge of the input signal (FIG. 2g), and when the sum signal is taken by the detector 7, the sum signal (FIG. 2 j) is.

The transmission frequency is twice that of the input signal (Fig. 2g).

In the above, from the period T of the input signal, the integrator circuit RI C1
If the period determined by T is small, the frequency T is higher than two periods T.
Even if the voltage changes, the voltage at point e is 7 at point C, so it is possible to generate a frequency twice that of the input signal. However, the upper limit of one frequency is determined by the limit of the gain of the detector 9.

Also, by increasing the input voltage to the integrating circuit R1.

The reference voltage of the detector 9 increases, and the margin against noise increases.

(Effects of the Invention) As explained above, the present invention provides a simple circuit including an input signal inverter, a 2-frequency divider, an integrating circuit, and a detector.
This kind of multiplier circuit can be provided with an arbitrary duty ratio.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram of its operating waveforms. 1... Input signal inverter, 2.5... TTL gate. 3.4.6,7,9... Edge detector (TTL gate).

Claims (1)

[Claims] means for inverting the phase of the antenna azimuth signal a; means for frequency-dividing the phase-inverted signal b to 1/2 the frequency c; a signal d obtained by two integrating means having a time constant larger than the period of the input signal; e, and detecting means for obtaining a signal f whose phase is shifted by 90° with respect to the 1/2 frequency; detecting means for obtaining signals g and h based on the falling or rising edge of the signal; and the phase inversion. The detection means obtains the signal i based on the falling edge of the input signal b, and the detecting means obtains a double frequency of the detected signals g and hi based on the rising edge of the input signal a. A featured radar antenna azimuth signal multiplier circuit.