JPS58129864A - Demodulator for phase modulated signal - Google Patents

Abstract

PURPOSE:To prevent an error of output due to phase variation of clock pulses by generating two 90 deg. out-of-phase clock pulses and using those clock pulses for sampling. CONSTITUTION:A comparator 21 shapes the waveform of an input analog signal to output a digital signal A to D flip-flops 22 and 23. An oscillating circuit 31 oscillates at a frequency which is an integral multiple of the carrier of the input signal. A phase shifter 30 divides the frequency of a signal from the oscillating circuit 31 to output two clock pulses B and C which have the carrier frequency of the phase modulated signal and are 90 deg. out of phase with each other. The D flip-flops 22 and 23 sample a signal from a comparator 21 by those clock pulses B and C to output signals D and E. The signals D and E are converted into signals H and I by differentiating circuits 24 and 25 and monostable multivibrating circuits 26 and 27. The signals H and I are converted into a demodulated output signal K through an AND circuit 28 and a T flip-flop 28.

Description

[Detailed description of the invention] The present invention relates to a demodulating device for phase modulated signals.

Conventionally, as a phase modulation method, for example, the configuration shown in FIG. 1 is known. This demodulation method is called a synchronous detection method, and as shown in the figure, the input signal is input to a frequency multiplier 11, where the frequency is multiplied and input to a phase locked loop (PLL) 12. It has become. The signal whose phase is synchronized by the phase synchronization circuit 12 is sent to the frequency divider 13.
The frequency of the signal is divided by 2 and input to the detection circuit 14. The detection circuit 14 receives an input signal and performs detection using this input signal as a reference.

However, in such a configuration, although the phase synchronized circuit 12 uses an analog circuit integrated into an IC, a small number of external components such as resistors and capacitors tend to need to be installed, and furthermore, design and Adjustment was difficult, and long-term stability and environmental resistance were poor.

Therefore, to prevent these drawbacks, phase-locked circuits configured as digital circuits are being considered;
The rotational configuration is extremely complex, especially if you consider making it into a shed, unless you consider creating a dedicated IC, you will not be able to achieve the purpose.Also, even if you create a dedicated IC, there will be little flexibility to change the specifications. It was something like that.

In general, phase-locked circuits require a certain amount of time to achieve synchronization with respect to signal input, and when applied to a system that communicates in bursts, a dummy circuit is used to promote synchronization prior to data transmission. Therefore, it was not suitable for systems with limited communication time.

An object of the present invention is to provide a phase f1iI that does not require synchronization means such as a phase synchronization circuit, and can be extremely simple and unadjusted.
The present invention provides a signal demodulation device.

In order to achieve such an object, the present invention includes an oscillation circuit having an oscillation frequency that is approximately an integral multiple of the carrier frequency of a phase modulation signal, and an output of the oscillation circuit that divides the output of the oscillation circuit to obtain the carrier frequency,
a phase chic that outputs first and second clock pulses with a phase difference of about 90°, a waveform shaping circuit that converts the phase modulation signal into a digital signal, and an output of this waveform shaping circuit The first and second 7-lip-flops are sampled by the second clock pulse, and Ui
14i.

Hereinafter, the present invention will be explained in detail using Examples.

Here, before showing specific embodiments of the present invention, the basics of the invention will be explained. The JIz diagram is a timing chart illustrating a waveform on an input signal, which is a phase modulation signal, and one method of demodulation. In the figure, nine modulated input signal signals are waveform-shaped and converted into digital signals.In this case, four carrier waves are assigned to one bit, but generally more than one wave is used. An integer wavenumber of #) is assigned. The phase of the input signal changes by 180 degrees (from B in the figure) in response to changes in data. One method for demodulating the original data from the input signal is to use the signal C in the same figure, which maintains a constant phase even if the phase of the input signal I changes by 180 degrees.
The clock pulse shown by the solid line P1 is reproduced by, for example, a PLL. At the rising edge of this clock pulse CPs, the incoming signal is sampled and the demodulated signal 01t-
Obtainable. Generally, the input signal is based on the output of an oscillator using a crystal resonator, so its frequency accuracy is extremely high and stable. Therefore, a fixed oscillator may be used on the receiving side as well, and the clock pulse CPI shown in FIG. 2 may be used. However, in this case, the carrier frequency of the input signal I cannot be expected to completely match the frequency of the fixed oscillator, and for a long time the clock pulse CPI
As shown by the O dotted line, the phase relationship may change with respect to the input signal. For this reason, the sampling output changes even though the phase of the input signal I does not change.Therefore, the input signal is sampled using two clock pulses cpi and CP2 with a 90° phase difference.
Even if the rising edge of one clock pulse is near the changing point of the input signal I, the rising edge of the other clock pulse is near the center of the pulse on the input signal (LJ), allowing stable sampling. For example, even if the relative phases of clock pulses CPI and CF2 with respect to the input signal change as shown by the dotted line, and the sampling output 01 due to clock pulse CPI changes regardless of the phase change of input signal I, clock pulse CP
The sampling output 02 by 2 does not change. Conversely, if there is a phase change indicating a change in data on the input signal, the sampling outputs 01 and 02 caused by the clock pulses CPI and CF2 change one after the other. The time interval of the change is the clock pulse CP1t or CF2
This is 1/4 period or 3/4 period. That is, 2
If changes in the two sampling outputs Of, 02 occur one after another within 3/4 cycle, the phase of the input signal changes and can be determined to be 9, and demodulation is performed.

FIG. 3 shows an embodiment of a phase modulation signal demodulation device according to the present invention based on this idea.

In the figure, if the comparator 21 is small, an analog signal is input to the comparator 21, and a digital signal as shown in FIG. 4 is output. In the figure, the resistor R1e Rv*Rs connected to the comparator 21 provides an appropriate bias to the comparator,
Further, the capacitor C performs AC coupling. The output signal from the comparator 21 (see FIG. 4) is input to the D7 lip 70 knobs 22 and 23, respectively.

On the other hand, if the oscillator circuit 31 which receives the oscillation output using a crystal or ceramic oscillator 32 with good frequency accuracy and stability is installed, the oscillation frequency of the oscillation output is an integral multiple of the carrier frequency in the human signal. There is. Oscillation circuit 31
The output signal from the oscillator is input to the phase shifter 30, which divides the output signal 1g from the oscillator @31 and divides the frequency of the output signal from the oscillator @31 into 90@ Two systems of clock pulses B (@Figure 4B) with phase differences and clock pulses C (Figure 4C)
)t-output.

The clock pulse B1 and the clock pulse C are input to the D7 flip-flop 22 and the D flip-flop 23, respectively.
The 7 flip-flop 22 and the D flip-flop 23 sample the output signal from the comparator 21 and output a signal D (FIG. 4D) and a signal E (FIG. 4E). The signal RI and the signal E are inputted to a differentiating circuit 24 and a differentiating circuit 25, respectively, and each of these differentiating circuits 24.2s has a time width when the signals RI and B rise and fall. Signal F (Fig. 4F) and signal G (Fig. 4G), which are small pulses of
) is now output. The signal F and signal G are input to a monostable multivibrator 26 and a monostable multivibrator 27, respectively, and these monostable multivibrators 26 and 27 input the time widths of the signals F and G, respectively. The small pulse width is expanded to produce good signal H (Fig. 4 H) and signal I (Fig. 4 I).
) is now output.

Here, when the monostable multivibrator 26, 27 receives a trigger pulse, it generates a clock pulse B or C.
The circuit is configured to output signals H and I having a time width between 374 cycles and 7/4 cycles. In this case, if the output signals F and G of the differentiating circuits 24 and 25 can be made into pulses with the above-mentioned time width, the pK signal I can be substituted for the signals H and I.
i', G can also be used.

The signals H and I are each input to an AND circuit 28, and this AND circuit 28 inputs each of the signals H and I.
The logical product of I is taken and a signal J (J in FIG. 4) is output. The signal is input to the 1tT-7 lip 70 tube 29, and a demodulated signal K (K in FIG. 4) is output.

In this way, if the signal shown in Figure 4 is assigned, for example, four carrier waves per one bit, clock pulses B and C advance the phase of the signal wave on the way, and then Therefore, the signal as a result of sampling signal A with clock pulse B changes even though there is no change in the phase of signal A. Furthermore, when sampling is performed using the clock pulse C, the data changes like the signal E in response to the change in the phase of the signal person. Pulses are formed as signals F and G at the rising and falling points of signals F and E, respectively, and the signals F and G are used as trigger signals to generate pulses with a constant time width from their rising points. Signal H,
If the signals H and I are formed like I, and the signal H and the signal I are ANDed, a signal like J (it) is obtained. Since a positive pulse is generated only when the input signal is A 4i-tone signal K can be obtained by dividing the signal into two channels.

In this way, it can be easily configured with an oscillator, a clip-flop, a multivibrator, a comparator, and a gate nut. Furthermore, the oscillation circuit can also be used for transmission. In addition, the circuit configuration itself is a digital terrorism.The output pulse width of the monostable multivibrator 26.27 is within a tolerance range of 3/4 period to 7/4 period of the clock pulse, which is larger than the component error. No upper adjustment is necessary.

- The human input signal is an analog signal, and if the signal-to-noise power ratio is low, the noise component will be superimposed on the signal component as shown in FIG.
When waveform shaping is performed, noise pulses are added to the output digital signal due to the influence of noise especially at the nine phase switching points. In such a case, malfunction can be prevented by applying positive feedback to the comparator 21 and setting the comparison level Vle VmL shown in FIG.

Here, when applying the demodulator to an in-vehicle device, for example,
Demodulators are often used together with information processing devices.

FIG. 6 is a block diagram showing another embodiment of the present invention. The same symbols as in FIG. 3 indicate the same circuits. As described above, the two signals processed by the D flip-flops 22 and 23 are simultaneously read into the microprocessor (MPU) 36 via the input/output circuit (Ilo) 34 using clock signals with different 90' phases. It looks like this. Based on the read data, the MPU 36 demodulates the data according to the procedure described later, and writes the data to the random access memory (RAM) 33.
) 35 stores the program of the MPU 36.

Here, the demodulation algorithm will be explained using FIG. 7. It is assumed that the signals A and E in FIG. 1s7 are the output sides of the D flip 70 knobs 22 and 23, respectively, and in particular, the signal E has a phase shift in the middle and outputs incorrect data. The MPU 36 repeatedly sends a signal at the timing shown in the figure below, monitors the H state, finds a change in level, and detects a change in the other level for a certain period of time ΔT.
If it occurs within +, that point is determined to be a phase change point. what if,
ΔT in the figure! As shown, the change in both levels is constant time Δ
The change is ignored if it does not occur within T1.

By measuring the time between the level change points in this way and dividing the time Ttl by the bit width Th, the number of bits during fleshing can be found. That is, if there is no phase change, it is either 10" or 11# of n bits. Such a timer means may be realized by software, or a hardware tie CR37 shown in the figure may be used. .

FIG. 8 shows a processing flow according to the algorithm. First, in step 81, the timer is reset to T=0. Hereinafter, T is the value of the timer. Next, step 8
At step 2, the data is read and at step 83, points of change in the data are found. When a change point is found, the timer Il[Tk at that time is stored in the memory M in step 84. At step 85, the existing data is inserted, and at step 86, a change point in the other data is searched for. If no change point is found, the process goes back to step 87 until time TM=Tt, and when TM>Ts, the process ignores the change and returns to the second stage of the flow. Here, T1 is set to fall between 3/4 period and 7/4 period of clock pulse B1 or C shown in FIG. If the other change point is found within the time T M < T, then in step 88 n
=T/Tb. Here, Th is the time for 1 bit. In step 89, the previous data is set to 1.
1'', the n bit is bound @0# in step 90, and in the opposite case, it is bound @1' in step 91.

Thereafter, return to the beginning and repeat the process.

According to such an embodiment, the microphone processor for data processing and control of the device can be used for demodulation operation, so the entire device can be simplified and can be made into a shed. In addition, since all parts related to demodulation are digitized, there are no adjustment points and productivity can be improved. Furthermore, since no PLL is used, there is no loss time such as synchronization time, and communication time can be saved. Moreover, it is possible to easily apply a system that performs communication within a limited period of nine hours.

As is clear from the above description, the phase modulation signal demodulation device according to the present invention does not require synchronization means such as a phase synchronization circuit, and can be extremely simple and eliminate adjustment.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional demodulator, and FIG.
FIG. 3 is an explanatory diagram showing the principle of the present invention, and FIG. 3 is a block diagram showing an embodiment of a demodulating device for a phase modulated signal according to the present invention.
FIG. 4 is a timing chart showing signals of each part of the demodulation device according to the present invention, FIG. 5 is an explanatory diagram of input signals of the demodulation device according to the present invention, and FIG. 6 is a diagram of the demodulation device for phase modulated signals according to the present invention. A block diagram showing another embodiment, FIG. 7 is a flowchart showing signals of each part in another embodiment of the demodulation device according to the present invention, and FIG. 8 is a demodulation 1 according to the present invention.
! FIG. 2 is an explanatory diagram showing an operation 70 of the MPU in another embodiment of FIG.

Claims (1)

[Claims] 1. Approximately the carrier frequency of the phase modulation signal! an oscillation circuit having an oscillation frequency multiplied by I, and a first and second oscillator circuit which divides the output of this oscillation circuit and has a phase difference of about 90° with respect to the carrier frequency.
a phase shifter that outputs a clock pulse; a waveform shaping circuit that converts the phase quality signal into a digital signal; and a first circuit that samples the output of the waveform shaping circuit with the first and second clock pulses. second 7 lip 7
1. A demodulating device for a phase modulated signal, comprising: a quadruple flip-flop; and means for performing Ill modulation on the outputs of the first and second seven lip-flops.