CN205228473U - Miniature navigational computer based on field programmable gate array - Google Patents
Miniature navigational computer based on field programmable gate array Download PDFInfo
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- CN205228473U CN205228473U CN201521108858.6U CN201521108858U CN205228473U CN 205228473 U CN205228473 U CN 205228473U CN 201521108858 U CN201521108858 U CN 201521108858U CN 205228473 U CN205228473 U CN 205228473U
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- programmable gate
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Abstract
The utility model relates to a computer, more specifically say and relate to a miniature navigational computer based on field programmable gate array, and be small, and satisfy large capacity data's collection, and data operation is fast. Multiplexer is used for reading respectively and exporting of multichannel incoming signal, and adc is used for the signal conversion who exports multiplexer to export for behind the data signal. Digital signal processor carries out operation to the received signal, and digital signal processor sends logic control instruction to the field programmable gate array to multiplexer, exports the switching on and turn -offing to received 0 and then control multiplexer of chip selection control command to the received signal after field programmable gate array handles. The buffer memory and the sampling of universal asynchronous receiver -transmit quantity performed certificate. Field programmable gate array receive digital signal processor to universal asynchronous receiver -transmit's logic control instruction and will instruct most likely export universal asynchronous receiver -transmit after the conversion the messenger can with the reading and writing signal.
Description
Technical field
The utility model relates to a kind of computing machine, more specifically to a kind of microminiature navigation computer based on field programmable gate array.
Background technology
Satellite/inertia (GPS/INS) integrated navigation and location system is the first-selected navigational system of low cost precision strike and minute vehicle, it is made up of microsensor and microminiature navigation computer, therefore, the design and researchp of microminiature navigation computer becomes crucial.The electronic technology of current advanced person also accelerates the development of microminiature navigation computer.Because navigational system collection signal kind is many, the algorithm of process information is more complicated, requires higher to navigational computer interface and processing power.The miniaturization of navigational system proposes current demand to Mini Navigation Computer.With personal computer be core processor navigation computer system not only complex structure, volume is large, weight is large, power consumption is large, also add the cost of navigational system, and the dirigibility of program efficiency and direct control hardware is also all affected.
Utility model content
The technical matters that the utility model mainly solves is: provide a kind of microminiature navigation computer based on field programmable gate array, volume is little, real-time good, and meets the collection of Large Volume Data, and data operation speed is fast.
For solving the problems of the technologies described above, the utility model relates to a kind of computing machine, more specifically to a kind of microminiature navigation computer based on field programmable gate array, comprise multiplexer, analog to digital converter, digital signal processor, field programmable gate array, storer, display screen, UART Universal Asynchronous Receiver Transmitter, universal serial bus, level transferring chip and input/output interface, volume is little, real-time good, and meeting the collection of Large Volume Data, data operation speed is fast.
The output terminal of multiplexer is connected with the input end of analog to digital converter, and multiplexer is used for the reading respectively of multichannel input signal and exports, and analog to digital converter exports after being used for that the signal that multiplexer exports is converted to digital signal.The output terminal of analog to digital converter is connected with digital signal processor, input end is connected with field programmable gate array, digital signal processor is connected with field programmable gate array, digital signal processor carries out calculation process to the received signal, digital signal processor sends to the logic control instruction of multiplexer to field programmable gate array, and field programmable gate array carries out processing rear output chip to the received signal and selects steering order to analog to digital converter and then the turn-on and turn-off controlling multiplexer.Storer is connected with digital signal processor, and storer is used for the storage of data and program.Display screen is connected with digital signal processor, and the duty of digital signal processor is presented on screen by display screen.UART Universal Asynchronous Receiver Transmitter is connected with digital signal processor, carries out bidirectional data transfers between UART Universal Asynchronous Receiver Transmitter and digital signal processor, and UART Universal Asynchronous Receiver Transmitter completes buffer memory and the sampling of data.The input end of UART Universal Asynchronous Receiver Transmitter is connected with the output terminal of field programmable gate array, and field programmable gate array receives digital signal processor and exports the enable of UART Universal Asynchronous Receiver Transmitter and read-write to the logic control instruction of UART Universal Asynchronous Receiver Transmitter by after this instruction transformation.Universal serial bus one end is connected with UART Universal Asynchronous Receiver Transmitter, the other end is connected with level transferring chip, level transferring chip is connected with input/output interface, universal serial bus provides serial signal transfer passage for UART Universal Asynchronous Receiver Transmitter and level transferring chip, and the signal that UART Universal Asynchronous Receiver Transmitter sends by level transferring chip transfers to input/output interface after carrying out level conversion.
As the further optimization of this programme, the multiplexer described in a kind of microminiature navigation computer based on field programmable gate array of the utility model has multiple.
As the further optimization of this programme, digital signal processor described in a kind of microminiature navigation computer based on field programmable gate array of the utility model is connected by parallel interface with between UART Universal Asynchronous Receiver Transmitter, and is connected with address wire and data line between digital signal processor and UART Universal Asynchronous Receiver Transmitter.
As the further optimization of this programme, the storer described in a kind of microminiature navigation computer based on field programmable gate array of the utility model comprises flash memory, synchronous DRAM and magnetic RAM.
The beneficial effect of a kind of microminiature navigation computer based on field programmable gate array of the utility model is:
A. volume is little;
B. real-time is good;
C. the acquisition and processing of Large Volume Data is applicable to;
D. fast operation.
Accompanying drawing explanation
Fig. 1 is the system chart of a kind of microminiature navigation computer based on field programmable gate array of the utility model.
Embodiment
In FIG, the utility model relates to a kind of computing machine, more specifically to a kind of microminiature navigation computer based on field programmable gate array, comprise multiplexer, analog to digital converter, digital signal processor, field programmable gate array, storer, display screen, UART Universal Asynchronous Receiver Transmitter, universal serial bus, level transferring chip and input/output interface, volume is little, real-time good, and meeting the collection of Large Volume Data, data operation speed is fast.
The output terminal of multiplexer is connected with the input end of analog to digital converter, and multiplexer is used for the reading respectively of multichannel input signal and exports, and analog to digital converter exports after being used for that the signal that multiplexer exports is converted to digital signal.The output terminal of analog to digital converter is connected with digital signal processor, input end is connected with field programmable gate array, digital signal processor is connected with field programmable gate array, digital signal processor carries out calculation process to the received signal, digital signal processor sends to the logic control instruction of multiplexer to field programmable gate array, and field programmable gate array carries out processing rear output chip to the received signal and selects steering order to analog to digital converter and then the turn-on and turn-off controlling multiplexer.Multiplexer has multiple.Amount of navigation traffic is large, and information needs to gather respectively, utilizes multiple multiplexer to carry out multichannel collecting.Send the reading command of some multiplexers at digital signal processor after, this instruction transformation is that sheet selects steering order by field programmable gate array, the collection of data is carried out in the multiplexer conducting controlling the respective pins that analog to digital converter connects, and avoids signal chaotic.
Storer is connected with digital signal processor, and storer is used for the storage of data and program.Storer comprises flash memory, synchronous DRAM and magnetic RAM.Need when navigational computer runs to carry out real-time storage to result and program, this is extremely important for system.The correctness of data communication ensure that the validity of system, but important procedure and correct result need record to preserve simultaneously, the reliability of such guarantee system.Do not lose after power down when flash memory and magnetic RAM carry out the storage of data and program.The interface of flash memory and synchronous DRAM is simple, the storage space of direct expansion of digital signal processor.Magnetic RAM is grown and stable performance the power down protection timeliness of data, increases the reliability of system data and program preservation.
Display screen is connected with digital signal processor, and the duty of digital signal processor is presented on screen by display screen.
UART Universal Asynchronous Receiver Transmitter is connected with digital signal processor, carries out bidirectional data transfers between UART Universal Asynchronous Receiver Transmitter and digital signal processor, and UART Universal Asynchronous Receiver Transmitter completes buffer memory and the sampling of data.The input end of UART Universal Asynchronous Receiver Transmitter is connected with the output terminal of field programmable gate array, and field programmable gate array receives digital signal processor and exports the enable of UART Universal Asynchronous Receiver Transmitter and read-write to the logic control instruction of UART Universal Asynchronous Receiver Transmitter by after this instruction transformation.Universal serial bus one end is connected with UART Universal Asynchronous Receiver Transmitter, the other end is connected with level transferring chip, level transferring chip is connected with input/output interface, universal serial bus provides serial signal transfer passage for UART Universal Asynchronous Receiver Transmitter and level transferring chip, and the signal that UART Universal Asynchronous Receiver Transmitter sends by level transferring chip transfers to input/output interface after carrying out level conversion.Expansion special UART Universal Asynchronous Receiver Transmitter in digital signal processor outside is utilized to complete buffer memory and the sampling of data, be conducive to like this improving the CPU work efficiency in digital signal processor, meet navigation computer system data transmission each side requirement, make CPU can monograph in the solution calculation and Analysis of data.And asynchronism transceiver chip hardware circuit realiration is simple, low in energy consumption, extensive interface enriches, and can realize the real-time transmission of a large amount of variety classes data.Be connected by parallel interface between digital signal processor with UART Universal Asynchronous Receiver Transmitter, and between digital signal processor and UART Universal Asynchronous Receiver Transmitter, be connected with address wire and data line.Digital signal processor carries out addressing by address bus to the internal register of UART Universal Asynchronous Receiver Transmitter, inputs correct control word to each register, carry out initialization by data bus.After carrying out correct initial work, just can realize basic serial communication.Changed by level format, the data communication between PC and digital signal processor can be realized.
Certain above-mentioned explanation is not limitation of the utility model; the utility model is also not limited only to above-mentioned citing; the change that those skilled in the art make in essential scope of the present utility model, remodeling, interpolation or replacement, also belong to protection domain of the present utility model.
Claims (4)
1. the microminiature navigation computer based on field programmable gate array, comprise multiplexer, analog to digital converter, digital signal processor, field programmable gate array, storer, display screen, UART Universal Asynchronous Receiver Transmitter, universal serial bus, level transferring chip and input/output interface, it is characterized in that: the output terminal of multiplexer is connected with the input end of analog to digital converter, multiplexer is used for the reading respectively of multichannel input signal and exports, and analog to digital converter exports after being used for that the signal that multiplexer exports is converted to digital signal; The output terminal of analog to digital converter is connected with digital signal processor, input end is connected with field programmable gate array, digital signal processor is connected with field programmable gate array, digital signal processor carries out calculation process to the received signal, digital signal processor sends to the logic control instruction of multiplexer to field programmable gate array, and field programmable gate array carries out processing rear output chip to the received signal and selects steering order to analog to digital converter and then the turn-on and turn-off controlling multiplexer; Storer is connected with digital signal processor, and storer is used for the storage of data and program; Display screen is connected with digital signal processor, and the duty of digital signal processor is presented on screen by display screen; UART Universal Asynchronous Receiver Transmitter is connected with digital signal processor, carries out bidirectional data transfers between UART Universal Asynchronous Receiver Transmitter and digital signal processor, and UART Universal Asynchronous Receiver Transmitter completes buffer memory and the sampling of data; The input end of UART Universal Asynchronous Receiver Transmitter is connected with the output terminal of field programmable gate array, and field programmable gate array receives digital signal processor and exports the enable of UART Universal Asynchronous Receiver Transmitter and read-write to the logic control instruction of UART Universal Asynchronous Receiver Transmitter by after this instruction transformation; Universal serial bus one end is connected with UART Universal Asynchronous Receiver Transmitter, the other end is connected with level transferring chip, level transferring chip is connected with input/output interface, universal serial bus provides serial signal transfer passage for UART Universal Asynchronous Receiver Transmitter and level transferring chip, and the signal that UART Universal Asynchronous Receiver Transmitter sends by level transferring chip transfers to input/output interface after carrying out level conversion.
2. a kind of microminiature navigation computer based on field programmable gate array according to claim 1, is characterized in that: described multiplexer has multiple.
3. a kind of microminiature navigation computer based on field programmable gate array according to claim 1, it is characterized in that: described digital signal processor is connected by parallel interface with between UART Universal Asynchronous Receiver Transmitter, and between digital signal processor and UART Universal Asynchronous Receiver Transmitter, be connected with address wire and data line.
4. a kind of microminiature navigation computer based on field programmable gate array according to claim 1, is characterized in that: described storer comprises flash memory, synchronous DRAM and magnetic RAM.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521108858.6U CN205228473U (en) | 2015-12-28 | 2015-12-28 | Miniature navigational computer based on field programmable gate array |
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| CN201521108858.6U CN205228473U (en) | 2015-12-28 | 2015-12-28 | Miniature navigational computer based on field programmable gate array |
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| CN205228473U true CN205228473U (en) | 2016-05-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109186604A (en) * | 2018-08-30 | 2019-01-11 | 衡阳市衡山科学城科技创新研究院有限公司 | A kind of inertial navigation computer system |
| CN109443362A (en) * | 2018-10-30 | 2019-03-08 | 中国船舶重工集团公司第七〇九研究所 | Navigational computer based on DSP and FPGA |
-
2015
- 2015-12-28 CN CN201521108858.6U patent/CN205228473U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109186604A (en) * | 2018-08-30 | 2019-01-11 | 衡阳市衡山科学城科技创新研究院有限公司 | A kind of inertial navigation computer system |
| CN109443362A (en) * | 2018-10-30 | 2019-03-08 | 中国船舶重工集团公司第七〇九研究所 | Navigational computer based on DSP and FPGA |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160511 Termination date: 20161228 |