CN108600066B - Single bus communication method - Google Patents

Single bus communication method Download PDF

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Publication number
CN108600066B
CN108600066B CN201810315773.7A CN201810315773A CN108600066B CN 108600066 B CN108600066 B CN 108600066B CN 201810315773 A CN201810315773 A CN 201810315773A CN 108600066 B CN108600066 B CN 108600066B
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delimiter
host
data
transmission unit
slave
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CN108600066A (en
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谭庆弟
罗巍
余华军
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Wuhan Hongchuang Lianzhong Technology Co ltd
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Wuhan Hongchuang Lianzhong Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40045—Details regarding the feeding of energy to the node from the bus

Abstract

The invention discloses a single bus communication method. The physical layer of the invention adopts 4bit data as a transmission unit to encode data to be transmitted, and the time length of high level represents the code value of the transmission unit. The invention has simple realization and low cost, does not need a special physical layer chip, has high direct current component on a signal line and can supply power to passive equipment.

Description

Single bus communication method
Technical Field
The invention relates to a communication method, in particular to a single bus communication method.
Background
In some communication systems requiring saving of signal line resources, the number of signal lines must be reduced as much as possible, and single bus communication is a better solution. I.e. the connection of two devices via a signal line and a ground line, and in many communication applications, power is required to be supplied via the signal line. However, the common One Wire bus is not suitable for providing power through a signal line, and the One Wire bus needs a special chip to support a physical layer protocol thereof, so that the implementation cost is high.
In view of the above, there is a need for a single bus approach that provides power and communication over signal lines.
Disclosure of Invention
In order to solve the problems that the existing single bus is complex in use, high in cost, needs a special chip and cannot provide power through a signal line, the invention provides a method for performing master-slave half-duplex communication while supplying power on the single bus. The method is simple in implementation mode and low in cost, and can provide power through the signal line.
The communication bus of the present invention physically comprises two wires: a signal line and a ground line.
The invention adopts 4bit (4 bit) data as a transmission unit to encode the data to be transmitted, and the time length of the high level of the signal line represents the code value of the transmission unit. Suppose the minimum unit time length of the high level of the transmission unit is TpThe transmission unit coding rule is as follows: (Transmission Unit code value +1) × TpA long high level.
For example, take TpIs 1ms (1 millisecond), then
4 b' 0000 is encoded as: (4 b' 0000+1) × 1ms ═ 1ms high;
4 b' 0101 is encoded as: (4 b' 0101+1) × 1ms ═ 6ms high;
4 b' 1111 encodes as: (4 b' 1111+1) × 1ms ═ 16ms high.
Coding data to be transmitted according to a group of 4 bits, wherein each code is a transmission unit D, and coding the data to be transmitted into a transmission unit group D1、D2…DnAnd n transmission units. Each transmission unit DxThe value of (x is an integer between 1 and n) is one of 16 values such as 4b '0000-4 b' 1111, and the corresponding coded high level time length is 1Tp～16TpOne of 16 time lengths.
The data types of the invention are: start symbol 0, start symbol 1, start symbol 2, transmission unit, stop symbol, delimiter. Wherein:
the start symbol 0 is low and the time length is Tstart0；
Start symbol 1 is high for a time period Tstart1；
Start symbol 2 is high for a time period Tstart2；
The transmission unit is at high level and has a time length of (transmission unit code value +1) x Tp；
The stop sign is high level and has a time length of Tstop，TstopIs TpInteger multiples;
the delimiter is at low level and has a time length of Tint。
The communication process of the invention is divided into 4 stages: idle phase, start phase, master sending data phase and slave answering data phase.
The idle phase signal line is high.
The starting stage is initiated by a host, and the sequence is as follows: { Start character 0, start character 1, delimiter, start character 2}
The host sends data phase initiated by the host, aiming at transmitting the transmission unit group D of the host1、D2…DnThe n transmission units and the stop symbols are sequentially transmitted to the slave. Before each transmission unit, a delimiter is inserted before and after the stop symbol, and the whole host sends data orderThe sequence of the segments is:
{ delimiter, D1Delimiter, D2Delimiter … Dn-1Delimiter, DnDelimiter, stop symbol, delimiter }
And after the host sends the last delimiter, the host enters an idle stage and waits for the response of the slave. If a certain time T is setdelayIf the slave response is not received, the slave is considered not to receive the data, and the master needs to execute the starting stage and the data sending stage again.
The slave response data phase is initiated by the slave, with the aim of setting the group D of transmission units of the slave1、D2…DnAnd sequentially sending the n transmission units and the stop symbols to the host. Before each transmission unit, a delimiter is inserted before and after a stop symbol, and the sequence of the whole slave response data phase is as follows:
{ delimiter, D1Delimiter, D2Delimiter … Dn-1Delimiter, DnDelimiter, stop symbol, delimiter }
And after the slave machine finishes sending the last delimiter, entering an idle stage and waiting for the master machine to send data.
The method has the advantages of realizing reliable data communication, being simple and convenient, being easy to realize and having low cost. And controls the delimiter T appropriatelyintAnd a minimum unit time length T of the transmission unitpA value of (e.g. T)int≤TpThe signal line can be in a high level state in most of the whole communication process, and the signal line contains a high direct current component and can supply power to equipment during communication.
Drawings
The invention is further described with reference to the following figures and detailed description.
FIG. 1 is a signal timing diagram;
FIG. 2 is a schematic diagram of a bus execution flow;
fig. 3 is a circuit schematic.
Detailed Description
As shown in the signal timing diagram of FIG. 1, the data types are: start symbol 0, start symbol 1, start symbol 2, transmission unit, stop symbol, delimiter. Wherein:
the start symbol 0 is low and the time length is Tstart0；
Start symbol 1 is high for a time period Tstart1；
Start symbol 2 is high for a time period Tstart2；
The transmission unit is at high level and has a time length of (transmission unit code value +1) x Tp；
The stop sign is high level and has a time length of Tstop，TstopIs TpInteger multiples;
the delimiter is at low level and has a time length of Tint。
The invention adopts 4-bit data as a transmission unit to encode data to be transmitted, and the time length of high level represents the code value of the transmission unit. Suppose the minimum unit time length of the high level of the transmission unit is TpThe transmission unit coding rule is as follows: (Transmission Unit code value +1) × TpA long high level.
For example, take TpIs 1ms (1 millisecond), then
4 b' 0000 is encoded as: (4 b' 0000+1) × 1ms ═ 1ms high;
4 b' 0101 is encoded as: (4 b' 0101+1) × 1ms ═ 6ms high;
4 b' 1111 encodes as: (4 b' 1111+1) × 1ms ═ 16ms high.
Coding data to be transmitted according to a group of 4 bits, wherein each code is a transmission unit D, and coding the data to be transmitted into a transmission unit group D1、D2…DnAnd n transmission units. Each transmission unit DxThe value of (x is an integer between 1 and n) is one of 16 values such as 4b '0000-4 b' 1111, and the corresponding coded high level time length is 1Tp～16TpOne of 16 time lengths.
The communication process of the invention is divided into 4 stages: idle phase, start phase, master sending data phase and slave answering data phase.
The idle phase signal line is high.
The starting stage is initiated by a host, and the sequence is as follows: { Start character 0, start character 1, delimiter, start character 2}
The host sends data phase initiated by the host, aiming at transmitting the transmission unit group D of the host1、D2…DnThe n transmission units and the stop symbols are sequentially transmitted to the slave. Before each transmission unit, a delimiter is inserted before and after the stop symbol, and the sequence of the whole host data sending stage is as follows:
{ delimiter, D1Delimiter, D2Delimiter … Dn-1Delimiter, DnDelimiter, stop symbol, delimiter }
And after the host sends the last delimiter, the host enters an idle stage and waits for the response of the slave. If a certain time T is setdelayIf the slave response is not received, the slave is considered not to receive the data, and the master needs to execute the starting stage and the data sending stage again.
The slave response data phase is initiated by the slave, with the aim of setting the group D of transmission units of the slave1、D2…DnAnd sequentially sending the n transmission units and the stop symbols to the host. Before each transmission unit, a delimiter is inserted before and after a stop symbol, and the sequence of the whole slave response data phase is as follows:
{ delimiter, D1Delimiter, D2Delimiter … Dn-1Delimiter, DnDelimiter, stop symbol, delimiter }
And after the slave machine finishes sending the last delimiter, entering an idle stage and waiting for the master machine to send data.
The high level time length of the transmission unit is in the range of 1Tp～16TpIn between, thus Tstop≥17TpAnd TstopIs TpThe stop sign of the bus is more easily recognized at integer multiples. Generally, T is taken in consideration of the actual processing capacity of the system and the high-level duty ratio of the signal linedelay≥Tp。
Typically, take Tstart0＝Tp，Tint＝Tp，Tstart1＝Tp，Tstart2＝16Tp,，Tstop＝17Tp，Tdelay＝20Tp. The high-level duty ratio of the signal wire can be ensured to be more than 50% under any condition.
Typically, take Tstart0＝0.5Tp，Tint＝0.5Tp，Tstart1＝Tp，Tstart2＝16Tp,，Tstop＝17Tp，Tdelay＝20Tp. The high-level duty ratio of the signal wire can be ensured to be more than 66.67 percent under any condition.
Typically, take Tstart0＝0.25Tp，Tint＝0.25Tp，Tstart1＝Tp，Tstart2＝16Tp,，Tstop＝17Tp，Tdelay＝20Tp. The high-level duty ratio of the signal wire can be ensured to be more than 80% under any condition.
Fig. 2 is a schematic diagram of a bus execution sequence, where the execution sequence is:
1.100, starting, initializing a bus, and entering 101;
2.101, in the bus idle stage, after a host unit group to be transmitted is prepared, entering 102;
3.102, starting the phase, and entering 103 after the host executes the starting phase;
4.103, the host sends the data stage, after the host sends the data, enter 104;
5.104, idle phase, entry 105;
6.105 if the host is at TdelayIf the slave response is not received within the time, the slave is considered not to receive the data sent by the host, the process enters 102, and the host needs to execute the starting stage and the data sending stage of the host again; if T isdelayIf the slave response is received, the process goes to 106;
7.106, the slave response data phase is executed, and the process proceeds to 101.
As shown in the circuit diagram of fig. 3, the method of the present invention can provide hardware support, and has simple implementation and low cost. The master machine and the slave machine are connected with a ground wire through a signal wire, namely a single bus. The master machine is an active device, and the slave machine is a passive device.
The host comprises a Power supply Power, a microcontroller MCU1, a resistor R1, a resistor R2 and an NPN type triode Q1.
The slave machine comprises a diode D1, a capacitor C1, an NPN type triode Q2, a resistor R3 and a microcontroller MCU 2.
On the master side, the Power supply Power generates a Power supply VCC for supplying Power to the master and the slave. The GPIO2 of the microcontroller MCU1 is connected with the base of the Q1 through a resistor R2; the signal wire is connected to the GPIO1 of the MCU1 and the collector of Q1 and is pulled up to VCC through R1; the emitter of Q1 is connected to ground.
The GPIO1 is configured as a high impedance input pin for the MCU1 to receive data of the signal line; the GPIO2 is configured as an output pin for the MCU1 to send data to a signal line. When the GPIO2 is high, the signal line is low, and when the GPIO2 is low, the signal line is high.
On the slave side, the anode of the D1 is connected with the signal wire, the cathode is connected with the capacitor C1, the other end of the C1 is connected with the ground, and the connection position of the D1 and the C1 is marked as VDD and used for extracting electric energy from the signal wire to supply power to the slave. The GPIO4 of the MCU2 is connected to the base of the Q2 through a resistor R3. The signal line is connected to the collectors of GPIOs 3 and Q2 of the MCU 2. The emitter of Q2 is grounded. When the signal line is high, the D1 charges the C1, and when the C1 capacitor is enough, the D1 can be used for supplying power to the slave machine, so that power can be extracted from the signal line to supply power to the equipment.
The GPIO3 is configured as a high impedance input pin for the MCU2 to receive data of the signal line; the GPIO4 is configured as an output pin for the MCU2 to send data to a signal line. When the GPIO4 is high, the signal line is low, and when the GPIO2 is low, the signal line is high.
When the bus is in an idle stage, both the GPIO2 and the GPIO4 are in a low level state, the signal line is in a high level state, the host power supply VCC charges the C1 through the R1 and the D1, and when the VDD is higher than the working voltage of the slave, the slave can work.
When the bus is in the start phase, the GPIO2 of the master MCU1 is responsible for transmitting data, and the GPIO3 of the slave MCU2 is responsible for receiving data. The GPIO4 of the slave MCU2 is in a low state.
When the bus is in the data transmitting phase of the host, the GPIO2 of the host MCU1 is responsible for transmitting data, and the GPIO3 of the slave MCU2 is responsible for receiving data. The GPIO4 of the slave MCU2 is in a low state.
When the bus is in the slave response data phase, the GPIO1 of the master MCU1 is responsible for receiving data, and the GPIO4 of the slave MCU2 is responsible for transmitting data. The GPIO2 of the host MCU1 is in a low state.

Claims (4)

1. A single bus communication method, the data type is divided into: start symbol 0, start symbol 1, start symbol 2, transmission unit, stop
Stopmarks and delimiters; the communication time sequence comprises an idle stage, a starting stage, a host data sending stage and a slave data answering stage;
the method is characterized in that:
the data to be transmitted is coded by adopting 4-bit data as a transmission unit, and the data to be transmitted forms a transmission unit group D after being coded1、D2....Dn(ii) a The time length of high level of the signal line represents the code value of the transmission unit, and the minimum unit high level time length of the transmission unit is Tp；
The start symbol 0 is low and the time length is Tstart0；
Start symbol 1 is high for a time period Tstart1；
Start symbol 2 is high for a time period Tstart2；
The transmission unit is at high level and has a time length of (transmission unit code value +1) x Tp；
The stop sign is high level and has a time length of Tstop，TstopIs TpInteger multiples;
the delimiter is at low level and has a time length of Tint；
The idle stage signal line is at a high level;
the starting stage is initiated by a host, and the sequence is as follows: { start character 0, start character 1, delimiter, start character 2 };
the host sends data phase initiated by the host, the sequence of the host sending data phase is { delimiter, D1Delimiter, D2、
Delimitern-1Delimiter, DnDelimiter, stopgap, delimiter };
the slave response data phase is initiated by the slave, and the sequence of the slave response data phase is { delimiter, D1Delimiter, D2、
Delimitern-1Delimiter, DnDelimiter, stopgap, delimiter };
the bus execution flow is as follows:
(100) starting, initializing a bus, and entering (101);
(101) in the bus idle stage, after a host standby transmission unit group is prepared, entering (102);
(102) the host computer enters (103) after the execution of the starting phase is finished;
(103) in the data sending stage of the host, the host enters (104) after the data sending is finished;
(104) an idle phase, entering (105);
(105) if the host is at TdelayIf the slave response is not received within the time, the slave is considered not to receive the data sent by the host, and the step (102) is entered, and the host needs to execute the starting stage and the data sending stage of the host again; if T isdelayIf the slave response is received, entering (106);
(106) and a slave response data phase, wherein after the slave response data phase is executed, the operation is started to (101).
2. A single bus communication method as claimed in claim 1, wherein: t isstart0 =Tp，Tint=Tp，Tstart1=Tp， Tstart2=16Tp，Tstop≥17 TpAnd TstopIs TpInteger multiple, Tdelay≥Tp。
3. A single bus communication method as claimed in claim 2, wherein: t isstop=17Tp，Tdelay=20Tp。
4. A single bus communication method as claimed in claim 3, wherein: t isp=1ms。
CN201810315773.7A 2018-04-10 2018-04-10 Single bus communication method Active CN108600066B (en)

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CN109495363A (en) * 2018-12-13 2019-03-19 上海申矽凌微电子科技有限公司 A kind of single bus data transmission chip and method

Citations (3)

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Publication number Priority date Publication date Assignee Title
CN103077142A (en) * 2012-12-28 2013-05-01 中国电子科技集团公司第五十四研究所 Simple communication method of bus transmission protocols
CN104657303A (en) * 2014-10-13 2015-05-27 江苏瑞微电子有限公司 Unibus data communication method
CN106453383A (en) * 2016-11-07 2017-02-22 深圳拓邦股份有限公司 UART (universal asynchronous receiver/transmitter)-based master-slave multi-processor communication system and method

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Publication number Priority date Publication date Assignee Title
FR2963449B1 (en) * 2010-07-27 2013-01-25 St Microelectronics Rousset CONVERSION OF A BIFILAR BUS IN A UNIFIL BUS

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103077142A (en) * 2012-12-28 2013-05-01 中国电子科技集团公司第五十四研究所 Simple communication method of bus transmission protocols
CN104657303A (en) * 2014-10-13 2015-05-27 江苏瑞微电子有限公司 Unibus data communication method
CN106453383A (en) * 2016-11-07 2017-02-22 深圳拓邦股份有限公司 UART (universal asynchronous receiver/transmitter)-based master-slave multi-processor communication system and method

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