CN211239866U - Quasi-bidirectional out-of-band communication circuit based on POE network line - Google Patents
Quasi-bidirectional out-of-band communication circuit based on POE network line Download PDFInfo
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Abstract
The utility model discloses a quasi two-way outband communication circuit based on POE network line is last, include: the main end is a POE Ethernet power supply equipment end, the slave end is a POE Ethernet powered equipment end, and the main end is connected with the slave end through a twisted pair; the utility model discloses before ethernet equipment starts or after starting, the break-make of host end to POE power supply is implemented the code control and is received by the follow end again and decode, realize the outband communication of host end to the follow end, when the host end need receive the follow end data, the host end at first notifies the follow end and prepares to send out data, then the host end control POE power is in the off-state, the slave end singlechip passes through from end line voltage control unit code control line voltage this moment, the host end singlechip receives and decodes through host end line voltage detection unit, realize the outband communication of host end inquiry receipt follow end data.
Description
Technical Field
The utility model relates to a POE network field especially relates to a based on accurate two-way outband communication circuit on POE network line.
Background
The Ethernet communication network is the most widely used communication network in the world at present, and the application of adding a Power Over Ethernet (POE) function to the terminal on the basis of the Ethernet network is also very common; in a traditional analog wired telephone line, a telephone line can complete voice communication and supply power to a telephone terminal, and number information can be transmitted through voltage pulse dialing, but the power supply capacity of the telephone line is very small and is only about 1W, the speed of pulse dialing transmission signals is also very low, and only about 10 pulses can be transmitted in about 1 second; asynchronous serial communication is a basic serial communication protocol, and communication is realized by serially coding and decoding high and low signal levels, but the protocol can only realize unidirectional data transmission by a single wire.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a to the weak point of background art and current design, propose one kind and utilize on current POE network line outside ordinary ethernet packet communication, realize the method of accurate two-way data communication.
A quasi-bidirectional out-of-band communication circuit over a POE-based network line, comprising: the main end is a POE Ethernet power supply equipment end, the main end mainly comprises a main end single chip microcomputer, a POE power supply control execution unit, a main end line bias unit, a main end line voltage detection unit and other circuit units of the main end, the slave end is a POE Ethernet powered equipment end and mainly comprises a line equivalent capacitive reactance charge absorption unit, a slave end line voltage control unit, a slave end isolation diode, a slave end line pulse voltage/current detection unit, a slave end single chip microcomputer, an energy storage capacitor and other circuit units of the slave end, and the main end is connected with the slave end through a twisted pair; outside the general ethernet packet communication, utilize the main end singlechip to carry out the code control to the break-make of POE power supply and receive by the slave and decode, realize the outband communication of main end to the slave, when the main end needs to receive the slave end data, the main end at first notifies the slave end and prepares to send data, then the main end control POE power is in the off-state, the slave end singlechip passes through slave end line voltage control unit code control line voltage this moment, the main end singlechip receives and decodes through main end line voltage detection unit, realize the outband communication of main end inquiry receiving slave end data, moreover, the steam generator is simple in structure, and the implementation is convenient.
The main terminal includes:
a main-end single chip microcomputer: the POE power on-off state is controlled by coding, and the slave end data is inquired, received and decoded;
POE power control execution unit: converting serial pulses output by a main-end singlechip into an on-off state of line power supply;
main end line bias unit: providing a certain working current for the line in the state that the POE power supply is closed;
main end line voltage detection unit: providing a line voltage signal for a main-end singlechip;
the other circuit units: circuitry other than POE power and out-of-band communications;
the slave end includes:
line equivalent capacitive reactance charge absorbing unit: controlling the power-off state of the POE at the main end, absorbing the current provided by the main end line bias unit and rapidly discharging the charges stored in the equivalent capacitive reactance of the line so as to reduce the direct-current voltage of the line;
a slave-side line voltage control unit: under the state that the POE power supply is turned off, the slave-end single chip microcomputer controls line voltage through the unit;
from-side isolation of the diode: controlling the power-off state of the POE at the master end to prevent the energy storage capacitor at the slave end from supplying power to the line;
a slave line pulse voltage/current detection unit: converting a pulse voltage/current signal generated by a POE power switch into a signal which can be identified by a slave end single chip microcomputer;
a slave end single chip microcomputer: decoding and receiving data transmitted by the main end, receiving the query of the single chip microcomputer of the main end, and returning the data;
energy storage capacitor: and keeping the power supply of the slave-end singlechip under the state that the main-end POE power supply is closed.
The other circuit units: POE is a circuit other than power receiving and out-of-band communication.
Further, the master end is a POE ethernet power supply device end, and the slave end is a POE ethernet powered device end.
Further, the POE power supply coding control execution unit is composed of a P-type transistor and an N-type transistor (including an NMOS transistor and an NPN transistor).
Further, the main terminal line bias unit is composed of a constant current diode.
Further, the main line bias unit is formed by a resistor.
Furthermore, the main end circuit biasing unit is formed by a constant current circuit consisting of an N-type transistor and a voltage stabilizing diode.
Furthermore, the main end circuit biasing unit is formed by a constant current circuit consisting of a P-type transistor and a voltage stabilizing diode.
Further, the main terminal line voltage detection unit is composed of a voltage comparator.
Further, the main terminal line voltage detection unit is formed by a resistance voltage division circuit.
Further, the line equivalent capacitive reactance charge absorption unit is composed of a constant current diode.
Further, the circuit is equivalent to a capacitive reactance charge absorption unit or is composed of a resistor.
Furthermore, the circuit equivalent capacitive reactance charge absorption unit is formed by a constant current circuit consisting of an N-type transistor and a voltage stabilizing diode.
Furthermore, the circuit equivalent capacitive reactance charge absorption unit is formed by a constant current circuit consisting of a P-type transistor and a voltage stabilizing diode.
Further, the slave line voltage control unit is composed of a zener diode and an N-type transistor.
Further, the slave line voltage control unit is composed of a resistor and an N-type transistor.
Further, the slave isolation diode is constituted by one diode.
Further, the slave line pulse voltage/current detection unit is composed of a P-type transistor and an N-type transistor.
Further, the slave line pulse voltage/current detection unit is formed by a voltage comparator.
Further, the slave line pulse voltage/current detection unit is formed by a resistance voltage division circuit.
Furthermore, the slave line pulse voltage/current detection unit is composed of a P-type transistor and a resistance voltage division circuit.
Further, the slave line pulse voltage/current detection unit is composed of a P-type transistor and a voltage comparator.
Further, the single chip is various 4-bit, 8-bit, 16-bit and 32-bit single chips or is equivalently replaced by an ASIC (application specific integrated circuit), an FPGA (field programmable gate array) and a CPLD (complex programmable logic device).
The utility model has the advantages that: out-of-band communication on a POE-based ethernet network line is established, and parameters can be set before network work (not limited to before network work) through the communication capability to meet the requirement of real-time automatic configuration of some devices, example 1: every network card all has unique MAC address, and the MAC address can change after the network card trouble is changed, then IP address, some software (a lot of software pass through with binding of network card MAC address accomplish use authorization), router setting etc. that bind with network card MAC address need manual resetting, the utility model discloses can be before the network starts, pass specific MAC address to the singlechip of slave end, reuse certain method let the ethernet card of slave end use this MAC address work after starting, then realized the long-range real-time automatic setting of network card MAC address to realized changing the network card and need not manual configuration, improved work efficiency;
example 2: the POE network slave-end powered device can be a Personal Computer (PC) with a POE network, the PC is provided with a real-time clock, and batteries are configured on a PC mainboard in order to maintain the operation of the real-time clock; can be before the operation of end PC, utilize the utility model discloses pass the singlechip of end to the current time, reuse certain method lets end PC according to this time value operation from end, then from end PC internal clock can be appointed by the singlechip before PC starts in real time, so in order to maintain the battery of the inside real-time clock continuous operation of PC can be cancelled, key parts such as mainboard, CPU, the memory of PC all are semi-permanent life-span, but the life-span of battery is often only 3~5 years, we have cancelled the trouble-free operating time and the reliability that the battery can improve equipment.
Example 3: the POE network slave-end powered device can be a Personal Computer (PC) with a POE network, the PC is provided with a boot password of a BIOS, in some public machine rooms, a manager may hope to have the boot password in some application occasions and hope not to have the boot password in some application occasions, and if the efficiency is low by manual setting; utilize the utility model discloses a with password (including empty password) to pass to the singlechip of slave end before PC starts, reuse certain method lets BIOS according to this password operation, then has realized the long-range real-time automatic control of start password.
Example 4: the slave-end powered device can be a Personal Computer (PC) with a POE network, the PC often has multiple system starting modes (such as network starting and local hard disk starting), in some public machine rooms, a manager may need network starting in some application occasions, and needs local hard disk starting in some application occasions, and if manual setting is needed, the efficiency is low; utilize the utility model discloses the singlechip to system startup item pass to the slave end before PC starts, and certain method of reuse lets PC according to this system startup item operation, has then realized the long-range real-time automatic control of PC start item.
Drawings
Fig. 1 is a detailed schematic diagram of a quasi-bidirectional out-of-band communication circuit on a POE network line;
fig. 2 is an equivalent circuit diagram of a quasi-bidirectional out-of-band communication circuit on a POE network line;
fig. 3 is a schematic diagram of a POE power control execution unit;
FIG. 4 is a schematic diagram of four main side line biasing units;
FIG. 5 is a schematic diagram of two main side line voltage detection units;
FIG. 6 is a schematic diagram of four circuit-equivalent capacitive reactance charge absorbing units;
FIG. 7 is a schematic diagram of two slave side line voltage control units; fig. 8 is a schematic diagram of five slave line pulse voltage/current detection units.
Detailed Description
The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description.
The specific embodiment is shown in fig. 1, wherein ZA at the master terminal and CA at the slave terminal, ZB at the master terminal and CB at the slave terminal are connected together through an ethernet twisted pair, an equivalent impedance (Rxl) of the connection is about several ohms to several tens of ohms, an equivalent capacitive reactance (Cxl, including a transistor junction capacitor and a line capacitor) is about several thousand PF, the equivalent inductive reactance is ignored, and an equivalent diagram is shown in fig. 2.
A main-end single chip microcomputer: the POE power supply on-off state is controlled by coding, and can be realized by 4-bit, 8-bit, 16-bit and 32-bit single-chip microcomputer, or by equivalent logic circuits such as ASIC, FPGA, CPLD and the like.
POE power control execution unit: the serial pulse output by the single chip microcomputer is converted into the on-off of line power supply through the unit, as shown in fig. 3.
Main end line bias unit: a bias current is provided to the line in the state where the main POE power is off, as shown in fig. 4.
Main end line voltage detection unit: the line voltage is converted into a signal that the master-end singlechip can recognize, as shown in fig. 5.
Other circuit units of the main end: circuits other than POE power supply and out-of-band communication may be a network chip, a logic circuit, a CPU, and the like.
Line equivalent capacitive reactance charge absorbing unit: when the POE power supply is switched from the on state to the off state, the bias current provided by the main line bias unit and the charge of the line equivalent capacitive reactance Cxl will maintain the line dc voltage (Uc _ a-Uc _ b) high, and the line equivalent capacitive reactance charge absorbing unit absorbs the bias current provided by the main line bias unit and quickly discharges the charge of Cxl, so that the line dc voltage quickly becomes low, as shown in fig. 6.
A slave-side line voltage control unit: in the state that the main POE power is turned off, the slave-end single chip microcomputer can control the voltage of the line through the slave-end single chip microcomputer, as shown in fig. 7.
From-side isolation of the diode: when the main end POE power supply is turned off, the energy storage capacitor at the slave end is prevented from supplying power to the line.
A slave line pulse voltage/current detection unit: when the POE master power switch is used, master serial signal information is obtained through the line voltage level or the current direction, and is converted into a signal which can be identified by the slave single chip microcomputer, and the signal is sent to the slave single chip microcomputer for processing, as shown in fig. 8.
A slave end single chip microcomputer: the data transmitted from the decoding receiving main end can be a 4-bit, 8-bit, 16-bit or 32-bit single chip microcomputer, or can be equivalently realized by logic circuits such as an ASIC (application specific integrated circuit), an FPGA (field programmable gate array), a CPLD (complex programmable logic device) and the like.
Energy storage capacitor: and in the main-end POE power supply off state, the slave-end single chip microcomputer keeps working by depending on the energy storage and power supply of the capacitor.
Slave side other circuit unit: circuits other than POE power supply and out-of-band communication may be a network chip, a logic circuit, a CPU, and the like.
Fig. 3 illustrates a mode of the POE power switch control execution unit, which includes a P-type transistor (including a PMOS transistor and a PNP transistor) and an N-type transistor (including an NMOS transistor and an NPN transistor), to switch the positive electrode of the POE power supply.
Fig. 4 illustrates four constituent modes of the main terminal line bias unit, wherein a first mode is that a constant current diode is placed at ZC and ZA points; the second mode is that a resistor is placed at ZC and ZA points; in the third mode, a constant current circuit consisting of a voltage stabilizing diode and an N-type transistor (comprising an NMOS (N-channel metal oxide semiconductor) transistor and an NPN (negative-positive-negative) triode) is placed at ZC and ZA points; and the fourth mode is that a constant current circuit consisting of a voltage stabilizing diode and a P-type transistor (comprising a PMOS tube and a PNP triode) is placed at ZC and ZA points.
Fig. 5 illustrates two component modes of the main-end line voltage detection unit, wherein in the first mode, the input end of a voltage comparator is connected to the points ZA and ZB, the output end of the voltage comparator is connected to ZF, and the line voltage is converted into a signal which can be identified by a main-end single chip microcomputer, in the second mode, two ends of a voltage division circuit formed by R1 and R2 resistors are connected to the points ZA and ZB, the middle point of the voltage division circuit is connected to the point ZF to send AD sampling, and the main-end single chip microcomputer analyzes and judges the line signal according to the AD sampling value.
FIG. 6 illustrates four modes of the equivalent capacitive reactance charge absorbing unit, one mode being a constant current diode connected between CC and CD, and the other mode being a resistor connected between CC and CD; in the third mode, a constant current circuit consisting of a voltage stabilizing diode and an N-type transistor (comprising an NMOS (N-channel metal oxide semiconductor) transistor and an NPN (negative-positive-negative) triode) is placed at the point of CC (charge coupled device) and CD (compact disc); and the fourth mode is that a constant current circuit consisting of a voltage stabilizing diode and a P-type transistor (comprising a PMOS tube and a PNP triode) is placed at the point of CC and CD.
FIG. 7 illustrates two modes of the slave side line voltage control unit, wherein a Zener diode and an N-type transistor (comprising an NMOS transistor and an NPN triode) are connected between the CD and the CF, the voltage drop of the circuit is close to 0 when the N-type transistor is controlled by the slave side single chip microcomputer to be turned on, and the voltage drop of the circuit is the Zener diode voltage stabilizing value when the N-type transistor is controlled by the slave side single chip microcomputer to be turned off; in the second mode, a resistor and an N-type transistor (comprising an NMOS transistor and an NPN triode) are connected between the CD and the CF, the voltage drop of the circuit is close to 0 when the N-type transistor is controlled by the slave end singlechip to be switched on, and the voltage drop of the circuit is the voltage drop of the resistor R1 when the N-type transistor is controlled by the slave end singlechip to be switched off.
Fig. 8 illustrates five modes of the slave side line pulse voltage/current detection unit, where the mode one is composed of a P-type transistor (including a PMOS transistor and a PNP transistor) and an N-type transistor (including an NMOS transistor and an NPN transistor), and pulses are obtained by detecting the current direction from CE to CG; in the second mode, CG in the module is suspended, CF point voltage is collected through the input end of a voltage comparator U1, a main end serial pulse signal is obtained through the comparison of line voltage and threshold voltage through the voltage comparator, and the output end of the voltage comparator is connected to a CH point; in the third mode, CG in the module is suspended, two ends of a divider resistor R1 and a resistor R2 are connected with CE and CF points, the middle point is connected with CH point to send AD sampling, and a slave singlechip analyzes and judges a line signal according to the AD sampling value; the fourth mode is composed of a voltage division circuit composed of a P-type transistor (comprising a PMOS tube and a PNP triode) and resistors R2 and R3, and pulse voltage is obtained through detecting the current direction between CE and CG and is transmitted to the singlechip at the slave end for processing; and the fifth mode is composed of a P-type transistor (comprising a PMOS tube and a PNP triode) and a voltage comparator, and pulse voltage obtained by detecting the current direction from CE to CG is shaped by the voltage comparator and then is sent to a slave-end singlechip for processing.
S1 the master transmitting serial data to the slave, comprising the steps of:
s11: the OUT pin of the main-end single-chip microcomputer ZU1 is converted from high level to low level, the POE power supply is converted from on to off state, the 3-line equivalent capacitive reactance charge absorption unit rapidly discharges the charges of the line equivalent capacitive reactance Cxl, the voltage value (Uc _ a-Uc _ b) of the slave-end line is rapidly converted to low, and the slave-end single-chip microcomputer CU1 recognizes the change through the 4-slave-end line pulse voltage/current detection unit.
S12: waiting for a time of one bit at a specified communication rate, sending a high level through an OUT pin of the main-end single-chip microcomputer ZU1, switching the POE power supply from off to on, rapidly changing the voltage values (Uc _ a-Uc _ b) of the slave-end lines to high values, and identifying the change through a 4 slave-end line pulse voltage/current detection unit by the slave-end single-chip microcomputer CU 1.
S13: by using the asynchronous serial communication coding and decoding principle, the operations of S1 or S2 are repeated, and the master-end singlechip ZU1 can send data to the slave-end singlechip CU1 to realize the transmission of master-end data to the slave-end.
S2 the master query receives the slave data, including the steps of:
s21: the master-end single chip microcomputer sends a query command to the slave-end single chip microcomputer through the S1 process to inform the slave-end single chip microcomputer of preparing to send data.
And S22, the main end single chip microcomputer controls the power supply of the circuit to be closed.
And S23, according to the appointed time sequence, the slave end single chip microcomputer controls the line voltage to change through the slave end line voltage control unit, and at the moment, the slave end single chip microcomputer keeps working by means of the energy storage capacitor.
And S24, the master-end singlechip recognizes the signal sent by the slave-end singlechip through the master-end line voltage detection unit, and receives the data of the slave-end singlechip by utilizing the asynchronous serial communication coding and decoding principle.
By integrating the processes of S1 and S2, the quasi-bidirectional communication between the master end and the slave end is realized.
The basic principles and the main features of the invention and the advantages of the invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, but rather is described in the embodiments and descriptions herein to illustrate the principles of the invention and that various changes and modifications may be made without departing from the spirit and scope of the invention, all of which fall within the scope of the claimed invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A quasi-bidirectional out-of-band communication circuit over a POE network line, comprising: the main end is a POE power over Ethernet equipment end and is connected with the slave end through a twisted pair; before or after the Ethernet equipment is started, the main end performs coding control on the power-on and power-off of POE power supply and then receives and decodes the power-on and power-off of the POE power supply from the auxiliary end, so that out-of-band communication from the main end to the auxiliary end is realized, when the main end needs to receive data from the auxiliary end, the main end firstly informs the auxiliary end of preparing to send the data, then the main end controls a POE power supply to be in a closed state, at the moment, the auxiliary end single chip controls line voltage through a line voltage control unit of the auxiliary end in a coding mode, and the main end single chip receives and decodes the data through a line voltage;
the main terminal includes:
a main-end single chip microcomputer: the POE power on-off state is controlled by coding, and the slave end data is inquired, received and decoded;
POE power control execution unit: converting serial pulses output by a main-end singlechip into an on-off state of line power supply;
main end line bias unit: providing a certain working current for the line in the state that the POE power supply is closed;
main end line voltage detection unit: providing a line voltage signal for a main-end singlechip;
other circuit units of the main end: circuitry other than POE power and out-of-band communications;
the slave end includes:
line equivalent capacitive reactance charge absorbing unit: controlling the power-off state of the POE at the main end, absorbing the current provided by the main end line bias unit and rapidly discharging the charges stored in the equivalent capacitive reactance of the line so as to reduce the direct-current voltage of the line;
a slave-side line voltage control unit: under the state that the POE power supply is turned off, the slave-end single chip microcomputer controls line voltage through the unit;
from-side isolation of the diode: controlling the power-off state of the POE at the master end to prevent the energy storage capacitor at the slave end from supplying power to the line;
a slave line pulse voltage/current detection unit: converting a pulse voltage/current signal generated by a POE power switch into a signal which can be identified by a slave end single chip microcomputer;
a slave end single chip microcomputer: decoding and receiving data transmitted by the main end, receiving the query of the single chip microcomputer of the main end, and returning the data;
energy storage capacitor: and keeping the power supply of the slave-end singlechip under the state that the main-end POE power supply is closed.
2. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the POE power code control execution unit comprises a P-type transistor and an N-type transistor.
3. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the main line bias unit is formed by a constant current diode, or a resistor, or a constant current circuit formed by an N-type transistor and a voltage regulator diode, or a constant current circuit formed by a P-type transistor and a voltage regulator diode.
4. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the main line voltage detection unit is formed by a voltage comparator or a resistor divider circuit.
5. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the line equivalent capacitive reactance charge absorption unit is formed by a constant current diode, or a resistor, or a constant current circuit formed by an N-type transistor and a voltage regulator diode, or a constant current circuit formed by a P-type transistor and a voltage regulator diode.
6. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the slave line voltage control unit comprises a zener diode and an N-type transistor, or comprises a resistor and an N-type transistor.
7. The POE-based network line quasi-bidirectional out-of-band communication circuit as recited in claim 1, wherein the slave isolation diode comprises a diode.
8. The POE network line-based quasi-bidirectional out-of-band communication circuit as claimed in claim 1, wherein the slave line pulse voltage/current detection unit comprises a P-type transistor and an N-type transistor, or a voltage comparator, or a resistance voltage divider circuit, or a P-type transistor and a voltage comparator.
9. The circuit of claim 1, wherein the single chip microcomputer is a 4-bit, 8-bit, 16-bit, or 32-bit single chip microcomputer, or is equivalently replaced by an ASIC, FPGA, or CPLD logic circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921978968.6U CN211239866U (en) | 2019-11-15 | 2019-11-15 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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| CN201921978968.6U CN211239866U (en) | 2019-11-15 | 2019-11-15 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110677266A (en) * | 2019-11-15 | 2020-01-10 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
| CN110677266B (en) * | 2019-11-15 | 2024-05-28 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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2019
- 2019-11-15 CN CN201921978968.6U patent/CN211239866U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110677266A (en) * | 2019-11-15 | 2020-01-10 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
| CN110677266B (en) * | 2019-11-15 | 2024-05-28 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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