CN110677266B - Quasi-bidirectional out-of-band communication circuit based on POE network line - Google Patents
Quasi-bidirectional out-of-band communication circuit based on POE network line Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention discloses a quasi-bidirectional out-of-band communication circuit based on POE network lines, which comprises: the power supply system comprises a main end and a slave end, wherein the main end is a POE Ethernet power supply equipment end, the slave end is a POE Ethernet power receiving equipment end, and the main end is connected with the slave end through a twisted pair; before or after the Ethernet equipment is started, the main end performs coding control on the on-off of POE power supply, then the slave end receives and decodes the POE power supply, so that out-of-band communication from the main end to the slave end is realized, when the main end needs to receive data of the slave end, the main end firstly informs the slave end to prepare to send the data, then the main end controls the POE power supply to be in a closed state, at the moment, the slave end singlechip controls the line voltage through the code of the slave end line voltage control unit, and the main end singlechip receives and decodes the POE power supply through the main end line voltage detection unit, so that out-of-band communication of the data of the slave end is inquired and received by the main end.
Description
Technical Field
The invention relates to the field of POE networks, in particular to a quasi-bidirectional out-of-band communication circuit based on a POE network line.
Background
The ethernet communication network is the most widely used communication network in the world at present, and the application of adding power supply functions (Power Over Ethernet, POE) to the terminal based on the ethernet network is also very common; in the traditional analog wired telephone line, the telephone line can complete voice communication and supply power to a telephone terminal, and meanwhile, the number information can be transmitted through voltage pulse dialing, but the power supply capacity of the telephone line is very small, only about 1W, the pulse dialing transmission signal rate is very low, and only about 10 pulses can be transmitted in about 1 second; asynchronous serial communication is a basic serial communication protocol, and communication is realized by serial encoding and decoding of high and low signal levels, but only unidirectional data transmission can be realized by a single protocol line.
Disclosure of Invention
The invention aims at overcoming the defects of the background technology and the prior design, and provides a method for realizing quasi-bidirectional data communication by utilizing the conventional POE network line to communicate with the common Ethernet data packet.
A quasi-bi-directional out-of-band communication circuit on a POE-based network link, comprising: the main end is a POE Ethernet power supply equipment end, and is mainly composed of a main end singlechip, a POE power supply control execution unit, a main end line bias unit, a main end line voltage detection unit and main end other circuit units, and the auxiliary end is a POE Ethernet power supply equipment end, and is mainly composed of a line equivalent capacitive reactance charge absorption unit, an auxiliary end line voltage control unit, an auxiliary end isolation diode, an auxiliary end line pulse voltage/current detection unit, an auxiliary end singlechip, an energy storage capacitor and auxiliary end other circuit units, and is connected with the auxiliary end through twisted pairs; besides the normal Ethernet data packet communication, the encoding control is implemented on the on-off of POE power supply by utilizing the master end singlechip, then the slave end receives and decodes the POE power supply, the out-of-band communication from the master end to the slave end is realized, when the master end needs to receive the slave end data, the master end firstly informs the slave end to prepare to send data, then the master end controls the POE power supply to be in a closed state, at the moment, the slave end singlechip controls the line voltage by encoding through the slave end line voltage control unit, and the master end singlechip receives and decodes the POE power supply through the master end line voltage detection unit, so that the out-of-band communication of the slave end data is inquired and received by the master end, and meanwhile, the device is simple in structure and convenient to implement.
The main end comprises:
main end singlechip: the POE power on-off state is controlled by encoding, and the slave-end data is inquired, received and decoded;
POE power control execution unit: converting serial pulse output by the main end singlechip into on-off state of line power supply;
A main-end line bias unit: providing a certain working current for the circuit in the POE power-off state;
A main end line voltage detection unit: providing a line voltage signal for a main-end singlechip;
Other circuit units: a circuitry other than POE power and out-of-band communications;
the slave comprises:
Line equivalent capacitive reactance charge absorption unit: controlling the POE power supply to be in a closed state at the main end, absorbing the current provided by the main end line bias unit and rapidly discharging the charge stored by the equivalent capacitive reactance of the line, so that the direct-current voltage of the line is lowered;
Slave-end line voltage control unit: in the state that the POE power supply is closed, the slave singlechip controls the line voltage through the unit;
slave-side isolation diode: controlling the POE power supply to be in a closed state at the main end, and preventing the energy storage capacitor of the slave end from supplying power to the line;
The slave-end line pulse voltage/current detection unit: converting a pulse voltage/current signal generated by the POE power switch into a signal which can be identified by a slave-end singlechip;
slave end singlechip: decoding and receiving data transmitted by a main terminal, receiving inquiry of a single-chip microcomputer at the main terminal, and returning the data;
energy storage capacitor: and in the state that the POE power supply at the main end is closed, the power supply of the singlechip at the slave end is kept.
Other circuit units: POE power up and circuitry other than out-of-band communications.
Further, the master terminal is a POE Ethernet power supply equipment terminal, and the slave terminal is a POE Ethernet power receiving equipment terminal.
Further, the POE power supply coding control execution unit is composed of a P-type transistor and an N-type transistor (including an NMOS transistor and an NPN triode).
Further, the main-end line bias unit is composed of a constant current diode.
Further, the main end line bias unit is alternatively constituted by a resistor.
Further, the main end circuit bias unit is formed by a constant current circuit consisting of an N-type transistor and a voltage stabilizing diode.
Further, the main end circuit bias unit is formed by a constant current circuit consisting of a P-type transistor and a voltage stabilizing diode.
Further, the main terminal line voltage detection unit is constituted by a voltage comparator.
Further, the main end line voltage detection unit is formed by a resistor voltage division circuit.
Further, the line equivalent capacitive reactance charge absorption unit is composed of a constant current diode.
Further, the line equivalent capacitive reactance charge absorption unit is alternatively formed by a resistor.
Further, the circuit equivalent capacitive reactance charge absorption unit is formed by a constant current circuit consisting of an N-type transistor and a voltage stabilizing diode.
Further, the circuit equivalent capacitive reactance charge absorption unit is formed by a constant current circuit consisting of a P-type transistor and a voltage stabilizing diode.
Further, the slave-end line voltage control unit is composed of a zener diode and an N-type transistor.
Further, the slave-end line voltage control unit is composed of a resistor and an N-type transistor.
Further, the slave-side isolation diode is constituted by one diode.
Further, the slave-end line pulse voltage/current detection unit is composed of a P-type transistor and an N-type transistor.
Further, the slave-end line pulse voltage/current detection unit is constituted by a voltage comparator.
Further, the slave-end line pulse voltage/current detection unit is formed by a resistor voltage division circuit.
Further, the slave-end line pulse voltage/current detection unit is formed by a P-type transistor and a resistor voltage division circuit.
Further, the slave-end line pulse voltage/current detection unit is composed of a P-type transistor and a voltage comparator.
Further, the single chip is various 4-bit, 8-bit, 16-bit and 32-bit single chip computers or is equivalently replaced by ASIC, FPGA, CPLD logic circuits.
The beneficial effects of the invention are as follows: by establishing the out-of-band communication on the POE-based Ethernet line, the parameters can be set by the communication capability before network operation (not limited to before network operation), so that the requirement of real-time automatic configuration of some devices can be met, and example 1: each network card has a unique MAC address, the MAC address changes after the network card is in fault replacement, then the IP address bound with the MAC address of the network card, certain software (a lot of software completes the use authorization through the binding with the MAC address of the network card), router setting and the like are required to be reset manually;
Example 2: the POE network slave end power receiving equipment can be a Personal Computer (PC) with the POE network, the PC is provided with a real-time clock, and in order to maintain the operation of the real-time clock, a battery is arranged on a PC main board; before the slave PC operates, the present invention transmits the current time to the slave PC, and the slave PC operates according to the time value by using a certain method, so that the internal clock of the slave PC can be appointed by the singlechip in real time before the PC is started, and in order to maintain the continuous operation of the internal real-time clock of the PC, the main board, the CPU, the internal memory and other key components of the PC are all semi-permanent life, but the life of the battery is only 3-5 years, and the fault-free operation time and the reliability of the equipment can be improved by canceling the battery.
Example 3: the POE network slave end powered device can be a Personal Computer (PC) with the POE network, the PC is provided with a startup password of a BIOS, in some public machine rooms, a manager may wish to have the startup password in some application occasions, and some application occasions wish to have no startup password, if the efficiency is very low by manual setting; the invention transmits a password (including an empty password) to the singlechip of the slave before the PC is started, and then the BIOS operates according to the password by a certain method, thereby realizing the remote real-time automatic control of the startup password.
Example 4: the slave power receiving equipment can be a Personal Computer (PC) with a POE network, the PC often has various system starting modes (such as network starting and local hard disk starting), in some public machine rooms, a manager can need network starting in some application occasions, and in some application occasions, local hard disk starting is needed, if the efficiency is very low by manual setting; the invention transmits the system startup item to the singlechip of the slave before the PC is started, and then the PC runs according to the system startup item by a certain method, thereby realizing the remote real-time automatic control of the PC startup item.
Drawings
FIG. 1 is a schematic diagram of a quasi-bi-directional out-of-band communication circuit on a POE network line;
FIG. 2 is an equivalent circuit diagram of a quasi-bi-directional out-of-band communication circuit on a POE network line;
FIG. 3 is a schematic diagram of a POE power control execution unit;
FIG. 4 is a schematic diagram of four main end line bias units;
FIG. 5 is a schematic diagram of two main-end line voltage detection units;
FIG. 6 is a schematic diagram of four circuit equivalent capacitive reactance charge absorption units;
FIG. 7 is a schematic diagram of two slave-side line voltage control units; fig. 8 is a schematic diagram of five slave-end line pulse voltage/current detection units.
Detailed Description
The technical solution of the present invention will be described in further detail with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description.
In the specific embodiment shown in fig. 1, ZA at the master end and CA at the slave end, ZB at the master end and CB at the slave end are connected together by an ethernet twisted pair, according to the length of the ethernet twisted pair, the equivalent impedance (Rxl) of the connection is about several ohms to tens of ohms, the equivalent capacitive reactance (Cxl, including transistor junction capacitance and line capacitance) is about thousands of PFs, and the equivalent inductive reactance is negligible, and the equivalent diagram is shown in fig. 2.
Main end singlechip: the POE power on-off state can be controlled by codes, which can be 4-bit, 8-bit, 16-bit and 32-bit singlechips, and can also be equivalently realized by logic circuits such as ASIC, FPGA, CPLD.
POE power control execution unit: serial pulse output by the singlechip is converted into on-off of line power supply through the unit, as shown in figure 3.
A main-end line bias unit: the main POE power off state provides a bias current to the line, as shown in fig. 4.
A main end line voltage detection unit: the line voltage is converted into a signal which can be identified by the master singlechip, as shown in fig. 5.
Other circuit units at the main end: the circuitry other than POE power supply and out-of-band communication may be circuitry such as a network chip, logic circuitry, CPU, etc.
Line equivalent capacitive reactance charge absorption unit: when the POE power supply is switched from the on state to the off state, the bias current provided by the main-end line bias unit and the charge of the line equivalent capacitive reactance Cxl will maintain the line dc voltage (uc_a-uc_b) to be high, and the line equivalent capacitive reactance charge absorption unit absorbs the bias current provided by the main-end line bias unit and rapidly discharges the charge of Cxl, so that the line dc voltage becomes low rapidly, as shown in fig. 6.
Slave-end line voltage control unit: in the state that the POE power supply at the main end is closed, the slave-end singlechip can control the voltage of the circuit through the POE power supply, and the voltage is shown in fig. 7.
Slave-side isolation diode: when the POE power supply of the main end is closed, the energy storage capacitor of the auxiliary end is prevented from supplying power to the line.
The slave-end line pulse voltage/current detection unit: when the POE main end power switch is used, main end serial signal information is obtained through the voltage or current direction of the line and is converted into a signal which can be identified by the slave end singlechip, and the signal is sent to the slave end singlechip for processing, as shown in fig. 8.
Slave end singlechip: the decoding receiving main end can be used for transmitting data, and the decoding receiving main end can be a 4-bit, 8-bit, 16-bit and 32-bit singlechip or can be equivalently realized by a ASIC, FPGA, CPLD logic circuit and the like.
Energy storage capacitor: in the POE power supply off state of the master end, the slave end singlechip is powered by the capacitor energy storage to keep working.
Slave-side other circuit units: the circuitry other than POE power supply and out-of-band communication may be circuitry such as a network chip, logic circuitry, CPU, etc.
Fig. 3 illustrates a composition mode of a POE power switch control execution unit, in which a P-type transistor (including a PMOS transistor and a PNP transistor) and an N-type transistor (including an NMOS transistor and an NPN transistor) are formed, and the positive electrode of the POE power supply is switched.
FIG. 4 illustrates four modes of composition of the main-side line bias unit, mode one being a constant current diode placed at ZC, ZA points; the second mode is that a resistor is arranged at ZC and ZA points; the third mode is that a constant current circuit consisting of a voltage stabilizing diode and an N-type transistor (comprising an NMOS tube and an NPN triode) is arranged at ZC and ZA points; and in the fourth mode, a constant current circuit consisting of a voltage stabilizing diode and a P-type transistor (comprising a PMOS tube and a PNP triode) is arranged at ZC and ZA points.
Fig. 5 illustrates two modes of the main-end line voltage detection unit, wherein one mode is that the input end of a voltage comparator is connected with ZA and ZB points, the output end of the voltage comparator is connected with ZF to convert line voltage into signals which can be identified by a main-end singlechip, the other mode is that two ends of a voltage dividing circuit formed by R1 and R2 resistors are connected with ZA and ZB points, the middle point of the voltage dividing circuit is connected with ZF to send AD samples, and the main-end singlechip analyzes and judges the line signals according to AD sampling values.
FIG. 6 illustrates four modes of circuit equivalent capacitive reactance charge absorption units, mode one being a constant current diode connected between CC and CD, mode two being a resistor connected between CC and CD; the third mode is that a constant current circuit consisting of a voltage stabilizing diode and an N-type transistor (comprising an NMOS tube and an NPN triode) is arranged at the points CC and CD; mode four is that a constant current circuit composed of a voltage stabilizing diode and a P-type transistor (comprising a PMOS tube and a PNP triode) is arranged at the points CC and CD.
FIG. 7 illustrates two modes of the slave-side line voltage control unit, wherein one mode is that a voltage stabilizing diode and an N-type transistor (comprising an NMOS transistor and an NPN triode) are connected between a CD and a CF, when the N-type transistor is controlled to be conducted by the slave-side singlechip, the voltage drop of the circuit is approximately 0, and when the N-type transistor is controlled to be turned off by the slave-side singlechip, the voltage drop of the circuit is the voltage stabilizing value of the voltage stabilizing diode; and a resistor and an N-type transistor (comprising an NMOS tube and an NPN triode) are connected between the CD and the CF in the second mode, when the N-type transistor is controlled to be conducted by the slave-end singlechip, the voltage drop of the circuit is approximately 0, and when the N-type transistor is controlled to be turned off by the slave-end singlechip, the voltage drop of the circuit is the voltage drop of the resistor R1.
Fig. 8 illustrates five modes of the slave-end line pulse voltage/current detection unit, wherein the first mode is composed of a P-type transistor (including a PMOS transistor and a PNP transistor) and an N-type transistor (including an NMOS transistor and an NPN transistor), and pulses are obtained through current direction detection from CE to CG; in the second mode, the CG inside the module is suspended, CF point voltage is acquired through the input end of a voltage comparator U1, the voltage comparator obtains a main end serial pulse signal through comparing line voltage with threshold voltage, and the output end of the voltage comparator is connected with a CH point; in the third mode, the CG in the module is suspended, two ends of the voltage dividing resistor R1 and R2 are connected with CE and CF points, the midpoint is connected with a CH point to send AD sampling, and the slave singlechip analyzes and judges a line signal according to the AD sampling value; the fourth mode is composed of a voltage dividing circuit composed of a P-type transistor (comprising a PMOS tube and a PNP triode) and resistors R2 and R3, and pulse voltage is obtained through current direction detection between CE and CG and is sent to a slave-end singlechip for processing; the fifth mode is composed of a P-type transistor (comprising a PMOS tube and a PNP triode) and a voltage comparator, pulse voltage is obtained through current direction detection between CE and CG, and then the pulse voltage is processed by a slave-end singlechip after being shaped by the voltage comparator.
S1, a master end transmits serial data to a slave end, and the method comprises the following steps:
S11: the OUT pin of the master end singlechip ZU1 is converted from high level to low level, the POE power supply is converted from on to off state, the line equivalent capacitive reactance charge absorption unit discharges the charge of the line equivalent capacitive reactance Cxl rapidly, the slave end line voltage value (Uc_a-Uc_b) is converted to low rapidly, and the slave end singlechip CU1 recognizes the change through the slave end line pulse voltage/current detection unit 4.
S12: waiting for the time of one bit of the specified communication rate, then sending high level through the OUT pin of the master end singlechip ZU1, switching the POE power supply from off to on, enabling the slave end line voltage value (Uc_a-Uc_b) to be rapidly increased, and recognizing the change through the slave end singlechip CU1 through 4 and the slave end line pulse voltage/current detection unit.
S13: the operation of the S1 or the S2 is repeated by utilizing the asynchronous serial communication coding and decoding principle, and the master-end singlechip ZU1 can send data to the slave-end singlechip CU1, so that the data transmission of the master-end to the slave-end is realized.
S2, the master-end inquires and receives slave-end data, and the method comprises the following steps of:
s21: the master end singlechip sends a query command to the slave end singlechip through the S1 process, and informs the slave end singlechip of preparing to send data.
S22, the master-end singlechip controls the circuit to be powered off.
S23, controlling the line voltage to change by the slave-end single-chip microcomputer through the slave-end line voltage control unit according to the agreed time sequence, and enabling the slave-end single-chip microcomputer to work by means of energy of the energy storage capacitor.
S24, the master end singlechip recognizes the signal sent by the slave end singlechip through the master end line voltage detection unit, and receives the data of the slave end singlechip by utilizing the asynchronous serial communication coding and decoding principle.
And the S1 and S2 processes are integrated, so that the quasi-bidirectional communication between the master terminal and the slave terminal is realized.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the invention, and various changes and modifications may be made therein without departing from the spirit and scope of the invention, which is defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A quasi-bi-directional out-of-band communication circuit on a POE-based network link, comprising: the power supply system comprises a main end and a slave end, wherein the main end is a POE (Power over Ethernet) power supply equipment end, the slave end is a POE Ethernet power receiving equipment end, and the main end is connected with the slave end through a twisted pair; before or after the Ethernet equipment is started, the main end carries out coding control on the on-off of POE power supply, then the main end receives and decodes the POE power supply, so as to realize out-of-band communication from the main end to the auxiliary end, when the main end needs to receive the auxiliary end data, the main end firstly informs the auxiliary end to prepare to send data, then the main end controls the POE power supply to be in a closed state, at the moment, the auxiliary end singlechip carries out coding control on line voltage through the auxiliary end line voltage control unit, and the main end singlechip receives and decodes the POE power supply through the main end line voltage detection unit, so as to realize out-of-band communication of the auxiliary end data inquired and received by the main end;
the main end comprises:
main end singlechip: the POE power on-off state is controlled by encoding, and the slave-end data is inquired, received and decoded;
POE power control execution unit: converting serial pulse output by the main end singlechip into on-off state of line power supply;
A main-end line bias unit: providing a certain working current for the circuit in the POE power-off state;
A main end line voltage detection unit: providing a line voltage signal for a main-end singlechip;
other circuit units at the main end: a circuitry other than POE power and out-of-band communications;
the slave comprises:
Line equivalent capacitive reactance charge absorption unit: controlling the POE power supply to be in a closed state at the main end, absorbing the current provided by the main end line bias unit and rapidly discharging the charge stored by the equivalent capacitive reactance of the line, so that the direct-current voltage of the line is lowered;
Slave-end line voltage control unit: in the state that the POE power supply is closed, the slave singlechip controls the line voltage through the unit;
slave-side isolation diode: controlling the POE power supply to be in a closed state at the main end, and preventing the energy storage capacitor of the slave end from supplying power to the line;
The slave-end line pulse voltage/current detection unit: converting a pulse voltage/current signal generated by the POE power switch into a signal which can be identified by a slave-end singlechip;
slave end singlechip: decoding and receiving data transmitted by a main terminal, receiving the inquiry of a single chip microcomputer at the main terminal, and returning the data;
energy storage capacitor: in the state that the POE power supply of the main end is closed, the power supply of the slave end singlechip is maintained;
Slave-side other circuit units: POE power up and circuitry other than out-of-band communications.
2. The quasi-bi-directional out-of-band communication circuit of claim 1, wherein said POE power coding control execution unit comprises a P-type transistor and an N-type transistor.
3. The quasi-bidirectional out-of-band communication circuit on POE-based network line according to claim 1, wherein said main-side line bias unit is composed of a constant current diode, a resistor, an N-type transistor and a zener diode, or a P-type transistor and a zener diode.
4. The quasi-bi-directional out-of-band communication circuit on POE-based network jack of claim 1, wherein said main-side line voltage detecting means is comprised of a voltage comparator or a resistor divider circuit.
5. The quasi-bidirectional out-of-band communication circuit on a POE-based network line according to claim 1, wherein said line equivalent capacitive reactance charge absorbing unit is comprised of a constant current diode, or a resistor, or a constant current circuit comprised of an N-type transistor and a zener diode, or a constant current circuit comprised of a P-type transistor and a zener diode.
6. The quasi-bi-directional out-of-band communication circuit on POE-based network jack of claim 1, wherein said slave-side line voltage control unit is comprised of a zener diode and an N-type transistor, or a resistor and an N-type transistor.
7. The quasi-bi-directional out-of-band communication circuit on POE-based network jack of claim 1, wherein said slave-side isolation diode is comprised of a diode.
8. The quasi-bi-directional out-of-band communication circuit according to claim 1, wherein said slave-side line pulse voltage/current detection unit is composed of a P-type transistor and an N-type transistor, or a voltage comparator, or a resistor voltage divider, or a P-type transistor and a voltage comparator.
9. The quasi-bi-directional out-of-band communication circuit based on POE network of claim 1, wherein said single chip microcomputer is a 4-bit, 8-bit, 16-bit, 32-bit single chip microcomputer, or equivalently replaced by ASIC, FPGA, CPLD logic circuits.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101132284A (en) * | 2006-08-23 | 2008-02-27 | 何自强 | Internet communication device |
| CN211239866U (en) * | 2019-11-15 | 2020-08-11 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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| US11307778B2 (en) * | 2018-03-09 | 2022-04-19 | Kioxia Corporation | Power management for solid state drives in a network |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101132284A (en) * | 2006-08-23 | 2008-02-27 | 何自强 | Internet communication device |
| CN211239866U (en) * | 2019-11-15 | 2020-08-11 | 成都喜马科技发展有限公司 | Quasi-bidirectional out-of-band communication circuit based on POE network line |
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