CN111263891A

CN111263891A - Instruction time testing method and system and computer storage medium

Info

Publication number: CN111263891A
Application number: CN201880033229.1A
Authority: CN
Inventors: 田晨
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2018-09-30
Filing date: 2018-09-30
Publication date: 2020-06-09
Anticipated expiration: 2038-09-30
Also published as: JP7223835B2; US11614484B2; EP3709036A4; CN111263891B; KR20210030425A; EP3709036B1; KR102557374B1; US20200132755A1; WO2020062306A1; JP2021533654A; EP3709036A1

Abstract

A test method and system of instruction time and computer storage medium, the test method includes: after the connection with the adapter is established, receiving a clock signal sent by the adapter; wherein the clock signal is used for indicating the transmission time (101) of the instruction; acquiring a first effective interrupt corresponding to a clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt (102); acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt (103); a test result (104) of the instruction time is generated according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.

Description

Instruction time testing method and system and computer storage medium

Technical Field

The embodiment of the application relates to a charging technology in the field of terminals, in particular to a method and a system for testing instruction time and a computer storage medium.

Background

The quick charging technology can charge the battery of the terminal in a segmented constant current mode through the adapter, so that quick charging can be carried out on the premise of ensuring safety and reliability, and the charging speed of the terminal is greatly improved. When the flash charging is performed, the adapter needs to perform bidirectional communication with the terminal, so that the time for the adapter to send the instruction has a certain influence on the flash charging effect.

In the prior art, when the time for sending the instruction by the adapter is detected by the oscilloscope, the detection instruction quantity is large, the detection process is complex, the detection efficiency is low, and the precision is poor.

Disclosure of Invention

The embodiment of the application provides a method and a system for testing instruction time and a computer storage medium, which can reduce the number of detection instructions and simplify the detection process when the time for sending instructions to an adapter is detected, thereby greatly improving the detection efficiency and precision.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a method for testing instruction time, which comprises the following steps:

after connection with an adapter is established, receiving a clock signal sent by the adapter; wherein the clock signal is used for indicating the transmission time of the instruction;

acquiring a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt;

acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt;

and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.

The embodiment of the application provides a method and a system for testing instruction time and a computer storage medium, wherein after the test system establishes connection with an adapter and establishes connection with the adapter, the test system receives a clock signal sent by the adapter; the clock signal is used for indicating the transmission time of the instruction; acquiring a first effective interrupt corresponding to a clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt; acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt; and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge. Therefore, in the embodiment of the application, after the test system establishes connection with the configurator, according to the clock signal sent by the configurator, the falling edge and the rising edge corresponding to the first effective interrupt, the square wave and the next effective interrupt during communication are respectively determined, so that the detection result of the instruction time corresponding to the adapter can be further obtained according to the rising edge and the falling edge of the clock signal. The test system can directly detect the instruction time of the adapter when communicating with the adapter, so that the number of detection instructions can be reduced and the detection process is simplified when the time for sending the instructions is detected, thereby greatly improving the detection efficiency and precision.

Drawings

Fig. 1 is a schematic flow chart illustrating an implementation of a method for testing instruction time according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a test system in an embodiment of the present application;

FIG. 3 is a schematic view of a test platelet;

FIG. 4 is a schematic diagram of the connection of a test system to an adapter;

FIG. 5 is a schematic diagram of clock signals in the present application;

FIG. 6 is a diagram illustrating clock and data signals during command transmission according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an embodiment of the present application for effectively interrupting rising and falling edges;

FIG. 8 is a first schematic structural diagram of a test system according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a second exemplary embodiment of a test system.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.

When the terminal is charged quickly, the flash charging function needs to be realized through a customized adapter and a battery, and generally, a Micro Control Unit (MCU) intelligent chip is configured in the adapter for flash charging, so that the adapter is an upgraded intelligent charger.

Further, in the embodiment of the present application, the adapter may mainly include the following five stages in the process of rapidly charging the terminal:

stage 1: the terminal detects the type of the adapter, the adapter starts handshake communication between the adapter and the terminal, the adapter sends a first instruction to inquire whether the terminal starts a quick charging mode, and after the terminal agrees to start quick charging, a quick charging communication flow enters a stage 2.

And (2) stage: the adapter sends a second instruction to the terminal to inquire whether the output voltage of the adapter is matched, and after the terminal replies that the output voltage of the adapter is higher, lower or matched, the adapter adjusts the output voltage until the output voltage is proper.

And (3) stage: the adapter sends a third instruction to the terminal asking for the maximum charging current currently supported by the terminal, which replies to the adapter maximum charging current and enters stage 4.

And (4) stage: the adapter can set the output current to the maximum charging current currently supported by the terminal, entering the constant current phase, i.e. phase 5.

And (5) stage: when entering the constant current stage, the adapter may send a fourth instruction at intervals to inquire about the current voltage of the terminal battery, the terminal may feed back the current voltage of the terminal battery to the adapter, and the adapter may determine whether the contact is good and whether the current charging current value of the terminal needs to be reduced according to the feedback of the terminal about the current voltage of the terminal battery.

It should be noted that the constant current phase does not mean that the output current of the adapter is kept constant in the phase 5, and the constant current is a segmented constant current, that is, the constant current is kept constant for a period of time.

Because the rapid charging is realized by establishing bidirectional communication between the adapter and the terminal to perform segmented constant current charging on the terminal, each parameter of the instruction sent by the adapter has a great influence on the flash charging effect, and the detection of the parameter of the instruction sent by the adapter is particularly important.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

An embodiment of the present application provides a method for testing instruction time, where fig. 1 is a schematic flow chart illustrating an implementation of the method for testing instruction time provided in the embodiment of the present application, and as shown in fig. 1, in the embodiment of the present application, the method for testing instruction time by using the test system may include the following steps:

step 101, after establishing connection with an adapter, receiving a clock signal sent by the adapter; wherein the clock signal is used for indicating the transmission time of the instruction.

In an embodiment of the present application, the test system may receive a clock signal sent by the adapter after establishing a connection with the adapter.

In the embodiment of the present application, when the adapter and the test system perform instruction transmission, the clock signal may be used to control a transmission time of an instruction, and specifically, the adapter may transmit the clock signal to the test system, so that the adapter and the test system perform bidirectional communication according to a clock cycle of the clock signal.

In an embodiment of the present application, the test system may be a system for performing parameter detection on the adapter. Fig. 2 is a schematic diagram of a test system in an embodiment of the present application, and as shown in fig. 2, the test system may include a test platelet, an electronic load, and an upper computer, where the test platelet may be connected to and cooperate with the electronic load, and may also be switched by controlling a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, MOS), so as to simulate a state of a terminal. Specifically, in the embodiment of the present application, the test platelet may transmit various detected values of the adapter to the upper computer, for example, the test platelet may report the detected output state of the adapter to the upper computer.

It should be noted that, in the embodiment of the present application, based on fig. 2, fig. 3 is a schematic diagram of a test board, and as shown in fig. 3, an MCU and an MOS may be integrated in the test board, where VBUS is a USB voltage, and GND is a power ground.

Further, in the embodiment of the present application, based on fig. 2 described above, fig. 4 is a schematic diagram of connection between the test system and the adapter, and as shown in fig. 4, the test platelet in the test system may be connected to the adapter and may perform bidirectional communication with the adapter.

It should be noted that, in the embodiment of the present application, the test system may simulate a process of performing fast charging on the terminal by the adapter through connection and communication with the adapter, so that various parameters of the adapter may be directly tested, and a parameter test result of the adapter does not need to be obtained by an oscilloscope.

Further, in this embodiment of the application, during the process of simulating the adapter to perform fast charging on the terminal through connection and communication with the adapter, the first interrupt in the received clock signal may be a first byte in the process of performing fast charging on the adapter and the terminal, that is, a first byte in the first instruction for inquiring whether to start the fast charging mode in the phase 1.

In the embodiment of the present application, the first interrupt in the clock signal may also be a test byte sent by the adapter and used for parameter detection of the adapter.

Further, in an embodiment of the present application, the adapter may be configured to perform quick charging on the terminal, and specifically, the adapter and the terminal may be connected through a Universal Serial Bus (USB) interface, where the USB interface may be a common USB interface, or may be a micro USB interface or a Type C interface. The power line in the USB interface is used for the above adapter to charge the terminal, wherein the power line in the USB interface may be a VBus line and/or a ground line in the USB interface. The data line in the USB interface is used for bidirectional communication between the adapter and the terminal, and the data line may be a D + line and/or a D-line in the USB interface.

Further, in the embodiment of the present application, the adapter may support a normal charging mode and a fast charging mode, wherein a charging current of the fast charging mode is greater than a charging current of the normal charging mode, that is, a charging speed of the fast charging mode is greater than a charging speed of the normal charging mode. In general, the normal charging mode can be understood as a charging mode in which the rated output voltage is 5V and the rated output current is 2.5A or less, and furthermore, in the normal charging mode, the output ports D + and D-of the adapter can be short-circuited, and in the fast charging mode, the adapter can communicate and exchange data with the mobile terminal using D + and D-.

It should be noted that, in the embodiment of the present application, since the adapter plays a decisive role in the effect of fast terminal charging, it is particularly important to test performance parameters of the adapter, where the performance parameters of the adapter may include a time parameter for sending an instruction, an output voltage, an output current, and the like.

In an embodiment of the application, after the test system establishes a connection with the adapter, the adapter may send a clock signal to the test system through a data line in the USB interface, where the clock signal is used to indicate a communication timing between the adapter and the test system. Specifically, the adapter actively transmits a clock signal to the test system, and the adapter can maintain the transmission of the clock signal throughout the connection with the test system, so that bidirectional communication with the test system can be performed under the control of the communication timing.

Further, in the embodiment of the present application, the communication timing includes an instruction transmission period of the above-described adapter and an instruction reception period of the above-described adapter, which are alternately generated.

Further, in an embodiment of the present application, after the test system establishes a connection with the adapter, the test system may receive the clock signal transmitted by the adapter through a D + data line.

Fig. 5 is a schematic diagram of clock signals in the present application, and as shown in fig. 5, in an embodiment of the present application, the clock signal of the D + data line includes a low level and a high level. Wherein one low level and one high level constitute one clock cycle, for example, one clock cycle comprises a low level of 10us and a high level of 500 us.

Based on fig. 5 and fig. 6 are schematic diagrams of a clock signal and a data signal when the instruction is transmitted in the embodiment of the present application, as shown in fig. 6, on one hand, each instruction sent by the adapter to the terminal includes 8 bits of data. The adapter sends 8 bits of data to the mobile terminal over successive 8 clock cycles of the clock signal. The first 10us of each of the 8 consecutive clock cycles is an interrupt and the last 500us is data. On the other hand, each reply instruction received by the adapter comprises 10 bits of data, the adapter receives 10 bits of data from the terminal through 10 consecutive clock cycles of the clock signal, the first 500us of each clock cycle in the 10 consecutive clock cycles is data, and the last 10us is interrupt.

Further, in an embodiment of the present application, the test system may test the command time through the received clock signal after establishing the connection with the adapter.

And 102, acquiring a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt.

In an embodiment of the present application, after receiving the clock signal sent by the adapter, the test system may acquire a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt, and a next effective interrupt corresponding to the first effective interrupt.

Further, in an embodiment of the present application, after receiving the clock signal, the test system may collect valid interrupts and square waves in the clock signal, and obtain a first valid terminal, a first square wave, and a second valid interrupt in the clock signal, that is, obtain the first valid interrupt, the square wave corresponding to the first valid interrupt, and the next valid interrupt.

It should be noted that, in the embodiment of the present application, since the first instruction sent by the adapter in the stage 1 is used to determine whether to start fast charging, when the test system performs a test of an instruction time, the test system needs to perform timing detection on the first instruction sent by the adapter, and therefore the square wave corresponding to the first effective interrupt and the first effective interrupt needs to be acquired.

It should be noted that, in the embodiment of the present application, when the test system performs the test of the instruction time, the interval time and the duration of the data transmission may be determined by two consecutive effective interrupts, so that the next effective interrupt corresponding to the first effective interrupt needs to be collected.

Step 103, acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt.

In an embodiment of the application, after acquiring the first effective interrupt, the square wave, and the next effective interrupt, the test system may acquire a first falling edge and a first rising edge corresponding to the first effective interrupt, may also acquire a second falling edge corresponding to the square wave, and simultaneously acquire a third falling edge corresponding to the next effective interrupt.

It should be noted that, in the embodiment of the present application, the test system may further determine whether the adapter meets the instruction timing requirement according to the first valid interrupt, the square wave, and the next valid interrupt, and specifically, the test system may first detect rising edges and falling edges of the first valid interrupt, the square wave, and the next valid interrupt, so as to obtain the first rising edge and the first falling edge of the first valid interrupt, further obtain a second falling edge corresponding to the square wave, and further obtain the third falling edge corresponding to the next valid interrupt.

Based on fig. 6 and fig. 7 are schematic diagrams of rising edges and falling edges of effective interrupts in the embodiment of the present application, and as shown in fig. 7, a test system may acquire a rising edge and a falling edge of a first effective interrupt, further acquire a falling edge corresponding to a square wave, and simultaneously acquire a falling edge corresponding to a second effective interrupt.

And 104, generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.

In an embodiment of the application, after obtaining the first falling edge and the first rising edge corresponding to the first effective interrupt, the second falling edge corresponding to the square wave, and the third falling edge corresponding to the next effective interrupt, the test system may further generate the test result according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.

Further, in an embodiment of the present application, after the first falling edge, the first rising edge, the second falling edge, and the third falling edge are determined, the test system may determine an interruption time for an effective interruption according to the first falling edge and the first rising edge, may determine a transmission time of data according to the first falling edge and the second falling edge, and may determine an interval time according to the second falling edge and the third falling edge.

In an embodiment of the present invention, when the test system generates the test result based on the first falling edge, the first rising edge, the second falling edge, and the third falling edge, the interrupt time, the transmission time, and the interval time may be directly obtained by the test platelet, or the first falling edge, the first rising edge, the second falling edge, and the third falling edge may be transmitted to the host computer by the test platelet, and then the interrupt time, the transmission time, and the interval time may be obtained by the host computer.

It should be noted that, in the embodiment of the present application, the test result is used to represent a result of testing the time parameter corresponding to the adapter, and specifically, it may be determined whether the time parameter corresponding to the adapter meets the timing requirement according to the test result.

Further, in the embodiment of the present application, the test result may include a first result for characterizing an interruption duration of the active interruption, a second result for characterizing a duration of the instruction data transmission, and a third result for characterizing a transmission interval time.

According to the method for testing the instruction time, after the connection with the adapter is established, the test system receives a clock signal sent by the adapter; the clock signal is used for indicating the transmission time of the instruction; acquiring a first effective interrupt corresponding to a clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt; acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt; and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge. Therefore, in the embodiment of the application, after the test system establishes connection with the configurator, according to the clock signal sent by the configurator, the falling edge and the rising edge corresponding to the first effective interrupt, the square wave and the next effective interrupt during communication are respectively determined, so that the detection result of the instruction time corresponding to the adapter can be further obtained according to the rising edge and the falling edge of the clock signal. The test system can directly detect the instruction time of the adapter when communicating with the adapter, so that the number of detection instructions can be reduced and the detection process is simplified when the time for sending the instructions is detected, thereby greatly improving the detection efficiency and precision.

Based on the foregoing embodiment, in another embodiment of the present application, the method for generating the test result of the instruction time by the test system according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge may include the following steps:

and 104a, determining the interruption time according to the first falling edge and the first rising edge.

In an embodiment of the application, after the first falling edge and the first rising edge corresponding to the first valid interrupt are obtained, the test system may further determine an interrupt time according to the first falling edge and the first rising edge.

It should be noted that, in the embodiment of the present application, the interrupt time may be used to characterize an interrupt duration of a valid interrupt in the clock signal sent by the adapter, and therefore, the test system may first determine the interrupt time to further determine whether the clock signal of the adapter meets a timing requirement.

And 104b, determining the transmission time according to the first falling edge and the second falling edge.

In an embodiment of the application, after the first falling edge corresponding to the first effective interrupt and the second falling edge corresponding to the square wave are obtained, the test system may further determine a transmission time according to the first falling edge and the second falling edge.

It should be noted that, in the embodiment of the present application, the transmission time may be used to represent a data transmission time when the adapter sends a command, and therefore, the test system may determine the transmission time first to further determine whether the command time of the adapter meets a timing requirement.

It should be noted that, in the embodiment of the present application, the transmission time is used to characterize the time required for a complete byte transmission, i.e., the time that the test system lasts from the time when the first valid interrupt corresponding to a byte is received to the time when the last bit corresponding to the byte is recovered.

And 104c, determining the interval time according to the second falling edge and the third falling edge.

In an embodiment of the application, after the second falling edge corresponding to the square wave and the third falling edge corresponding to the next valid interrupt are obtained, the test system may further determine an interval time according to the second falling edge and the third falling edge.

It should be noted that, in the embodiment of the present application, the interval time may be used to characterize a transmission interval between different bytes when the adapter sends a command, and therefore, the test system may first determine the interval time to further determine whether the command time of the adapter meets a timing requirement.

Further, in the embodiment of the present application, the interval time is used to characterize a time interval between two adjacent bytes, that is, an interval time between two adjacent bytes consecutively transmitted by the adapter.

And step 104d, determining a test result according to the interruption time, the transmission time and the interval time.

In an embodiment of the application, after determining the interruption time, the transmission time, and the interval time, the test system may determine the test result according to the interruption time, the transmission time, and the interval time.

Further, in an embodiment of the present invention, when determining the test result according to the interruption time, the transmission time, and the interval time, the test system may compare a preset interruption threshold, a preset transmission threshold, and a preset interval threshold with the interruption time, the preset transmission time, and the preset interval time, respectively, so as to determine the test result according to a comparison result.

Based on the foregoing embodiment, in yet another embodiment of the present application, before the test system determines the test result according to the interruption time, the transmission time, and the interval time, that is, before step 104d, the method for the test system to perform the instruction time test may further include the following steps:

and 105, acquiring a preset interruption time threshold, a preset transmission time threshold and a preset interval time threshold.

In an embodiment of the application, before the test system generates the test result according to the interruption time, the transmission time, and the interval time, the test system may first obtain a preset interruption time threshold, a preset transmission time threshold, and a preset interval time threshold.

It should be noted that, in the embodiment of the present application, the preset interruption time threshold, the preset transmission time threshold, and the preset interval time threshold may represent a time sequence requirement corresponding to the adapter.

Further, in an embodiment of the present application, the test system may preset the preset interrupt time threshold, the preset transmission time threshold, and the preset interval time threshold, where the preset interrupt time threshold is used to represent a timing requirement of an effective interrupt in the adapter sending clock signal; the preset transmission time threshold is used for representing the time sequence requirement of the adapter for transmitting data; the predetermined interval time threshold is used to characterize the timing requirement of the time interval between two consecutive bytes to be transmitted that the adapter should meet.

In an embodiment of the present application, further, the method for determining the test result by the test system according to the interruption time, the transmission time, and the interval time may include the following steps:

step 201, obtaining a first result according to the interruption time and a preset interruption time threshold.

In an embodiment of the application, after obtaining the interruption time and the preset interruption time threshold, the test system may further obtain a first result according to the interruption time and the preset interruption time threshold.

It should be noted that, in the embodiment of the present application, the test system may compare the interruption time with the preset interruption time threshold, so that the first result may be further determined according to the comparison result. Wherein the first result is used to determine whether the adapter meets timing requirements for a valid interrupt in a clock signal.

Further, in an embodiment of the application, after comparing the interruption time with the preset interruption time threshold, if the interruption time is greater than or equal to the preset interruption time threshold, the test system may determine that the first result is that the timing requirement is not satisfied.

Further, in an embodiment of the application, after comparing the interruption time with the preset interruption time threshold, if the interruption time is smaller than the preset interruption time threshold, the test system may determine that the first result is that the timing requirement is satisfied.

Step 202, obtaining a second result according to the transmission time and a preset transmission time threshold.

In an embodiment of the application, after obtaining the transmission time and the preset transmission time threshold, the test system may further obtain a second result according to the transmission time and the preset transmission time threshold.

It should be noted that, in the embodiment of the present application, the test system may compare the transmission time with the preset transmission time threshold, so that the second result may be further determined according to the comparison result. Wherein the second result is used to determine whether the adapter satisfies a timing requirement for transmitting a byte.

Further, in an embodiment of the application, after comparing the transmission time with the preset transmission time threshold, if the transmission time is greater than or equal to the preset transmission time threshold, the test system may determine that the second result does not satisfy the timing requirement.

Further, in an embodiment of the application, after comparing the transmission time with the preset transmission time threshold, if the transmission time is smaller than the preset transmission time threshold, the test system may determine that the second result satisfies the timing requirement.

And step 203, obtaining a third result according to the interval time and a preset interval time threshold.

In an embodiment of the application, after obtaining the interval time and the preset interval time threshold, the test system may further obtain the third result according to the interval time and the preset interval time threshold.

It should be noted that, in the embodiment of the present application, the test system may compare the interval time with the preset interval time threshold, so that the third result may be further determined according to the comparison result. Wherein the third result is used to determine whether the adapter meets the timing requirement for a time interval to transmit two consecutive bytes.

Further, in an embodiment of the application, after comparing the interval time with the preset interval time threshold, if the interval time is greater than or equal to the preset interval time threshold, the test system may determine that the third result is that the timing requirement is not satisfied.

Further, in an embodiment of the application, after comparing the interval time with the preset interval time threshold, if the interval time is smaller than the preset interval time threshold, the test system may determine that the third result satisfies the timing requirement.

And step 204, determining a test result according to the first result, the second result and the third result.

In an embodiment of the application, after obtaining the first result, the second result, and the third result, the test system may generate a test result corresponding to the adapter according to the first result, the second result, and the third result.

It should be noted that, in the embodiment of the present application, the test result may determine whether the time parameter of the adapter meets a preset timing requirement, that is, whether the adapter meets an interrupt timing requirement of an active interrupt, whether a duration timing requirement of sending one byte is met, and whether the adapter meets a timing requirement of a time interval of sending two consecutive bytes.

Based on the foregoing embodiment, in another embodiment of the present application, fig. 8 is a schematic structural diagram of a component of a test system provided in the embodiment of the present application, and as shown in fig. 8, a test system 1 provided in the embodiment of the present application may include a receiving portion 11, an obtaining portion 12, and a generating portion 13.

The receiving part 11 is used for receiving the clock signal sent by the adapter after the connection with the adapter is established; wherein the clock signal is used for indicating the transmission time of the instruction.

The obtaining part 12 is configured to obtain a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt, and a next effective interrupt corresponding to the first effective interrupt; and acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt.

The generating part 13 is configured to generate a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.

Further, in the embodiment of the present application, the generating part 13 is specifically configured to determine an interrupt time according to the first falling edge and the first rising edge; and determining a transmission time according to the first falling edge and the second falling edge; and determining an interval time according to the second falling edge and the third falling edge; and determining the test result according to the interruption time, the transmission time and the interval time.

Further, in an embodiment of the present application, the obtaining portion 12 is further configured to obtain a preset interrupt time threshold, a preset transmission time threshold, and a preset interval time threshold before determining the test result according to the interrupt time, the transmission time, and the interval time; the preset interrupt time threshold, the preset transmission time threshold and the preset interval time threshold are used for representing the time sequence requirement corresponding to the adapter.

Further, in an embodiment of the present application, the obtaining part 12 is specifically configured to obtain a first result according to the interruption time and the preset interruption time threshold; obtaining a second result according to the transmission time and the preset transmission time threshold; and obtaining a third result according to the interval time and the preset interval time threshold.

The generating part 13 is specifically configured to determine the test result according to the first result, the second result, and the third result.

Further, in an embodiment of the present application, the obtaining portion 12 is further specifically configured to, when the interruption time is greater than or equal to the preset interruption time threshold, determine that the first result is that the timing requirement is not satisfied; when the interruption time is smaller than the preset interruption time threshold, the first result is that the time sequence requirement is met; and when the transmission time is greater than or equal to the preset transmission time threshold, the second result is that the timing requirement is not met; and when the transmission time is less than the preset transmission time threshold, the second result is that the timing sequence requirement is met; and when the interval time is greater than or equal to the preset interval time threshold, the third result is that the timing sequence requirement is not met; and when the interval time is smaller than the preset interval time threshold, the third result is that the time sequence requirement is met.

Fig. 9 is a schematic structural diagram of a second component of the test system according to the embodiment of the present disclosure, and as shown in fig. 9, the test system 1 according to the embodiment of the present disclosure may further include a test platelet 14, an upper computer 15, and an electronic load 16. The test small plate is integrated with a processor and a memory for storing executable instructions of the processor. Optionally, the test system 1 may further include a communication interface 17, and a bus 18 for connecting the test platelet 14, the upper computer 15, the electronic load 16, and the communication interface 17.

Further, in the embodiment of the present application, a processor and a memory may also be integrated in the upper computer, and the functions of the processor and the memory in the test small board 16 are the same.

In an embodiment of the present Application, the Processor may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a ProgRAMmable Logic Device (PLD), a Field ProgRAMmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic devices for implementing the above processor functions may be other devices, and the embodiments of the present application are not limited in particular. The test system 1 may further comprise a memory which may be connected to the processor, wherein the memory is adapted to store executable program code comprising computer operating instructions, the memory may comprise a high speed RAM memory, and may further comprise a non-volatile memory, such as at least two disk memories.

In an embodiment of the application, a memory is used for storing instructions and data.

Further, in an embodiment of the present application, the processor is configured to receive a clock signal sent by an adapter after establishing a connection with the adapter; wherein the clock signal is used for indicating the transmission time of the instruction; acquiring a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt; acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt; and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.

In practical applications, the Memory may be a volatile first Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile first Memory (non-volatile Memory), such as a Read-Only first Memory (ROM), a flash Memory (flash Memory), a Hard Disk Drive (HDD) or a Solid-State Drive (SSD); or a combination of first memories of the above kind and provides instructions and data to the processor.

In addition, each functional module in this embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the integrated unit, if implemented in the form of a software functional module and not sold or used as an independent product, may be stored in a computer-readable storage medium, and based on this understanding, a part of the technical solution of the present embodiment that essentially contributes to the prior art or all or part of the technical solution may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

According to the test system provided by the embodiment of the application, after the connection with the adapter is established, the test system receives a clock signal sent by the adapter; the clock signal is used for indicating the transmission time of the instruction; acquiring a first effective interrupt corresponding to a clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt; acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt; and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge. Therefore, in the embodiment of the application, after the test system establishes connection with the configurator, according to the clock signal sent by the configurator, the falling edge and the rising edge corresponding to the first effective interrupt, the square wave and the next effective interrupt during communication are respectively determined, so that the detection result of the instruction time corresponding to the adapter can be further obtained according to the rising edge and the falling edge of the clock signal. The test system can directly detect the instruction time of the adapter when communicating with the adapter, so that the number of detection instructions can be reduced and the detection process is simplified when the time for sending the instructions is detected, thereby greatly improving the detection efficiency and precision.

The embodiment of the present application provides a first computer-readable storage medium, on which a program is stored, which when executed by a processor implements the method for testing instruction time as described above.

Specifically, the program instructions corresponding to a test method of an instruction time in the present embodiment may be stored on a storage medium such as an optical disc, a hard disc, a U-disc, etc., and when the program instructions corresponding to a test method of an instruction time in the storage medium are read or executed by an electronic device, the method includes the following steps:

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of implementations of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks in the flowchart and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.

Industrial applicability

Claims

A method of instruction time testing, the method comprising:

after connection with an adapter is established, receiving a clock signal sent by the adapter;

acquiring a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt;

acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt;

and generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.
The method of claim 1, wherein said generating a test result of an instruction time from the first falling edge, the first rising edge, the second falling edge, and the third falling edge comprises:

determining interrupt time according to the first falling edge and the first rising edge;

determining a transmission time according to the first falling edge and the second falling edge;

determining an interval time according to the second falling edge and the third falling edge;

and determining the test result according to the interruption time, the transmission time and the interval time.
The method of claim 2, wherein prior to determining the test result from the interruption time, the transmission time, and the interval time, the method further comprises:

acquiring a preset interruption time threshold, a preset transmission time threshold and a preset interval time threshold; the preset interrupt time threshold, the preset transmission time threshold and the preset interval time threshold are used for representing the time sequence requirement corresponding to the adapter.
The method of claim 3, wherein said determining the test result from the interruption time, the transmission time, and the interval time comprises:

obtaining a first result according to the interruption time and the preset interruption time threshold;

obtaining a second result according to the transmission time and the preset transmission time threshold;

obtaining a third result according to the interval time and the preset interval time threshold;

and determining the test result according to the first result, the second result and the third result.
The method of claim 4, wherein said obtaining a first result based on the interrupt time and the preset interrupt time threshold comprises:

when the interruption time is greater than or equal to the preset interruption time threshold, the first result is that the timing sequence requirement is not met;

and when the interruption time is smaller than the preset interruption time threshold, the first result is that the time sequence requirement is met.
The method of claim 4, wherein the obtaining a second result based on the transmission time and the preset transmission time threshold comprises:

when the transmission time is greater than or equal to the preset transmission time threshold, the second result is that the time sequence requirement is not met;

and when the transmission time is smaller than the preset transmission time threshold value, the second result is that the time sequence requirement is met.
The method of claim 4, wherein the obtaining a third result according to the interval time and the preset interval time threshold comprises:

when the interval time is greater than or equal to the preset interval time threshold, the third result is that the timing sequence requirement is not met;

and when the interval time is smaller than the preset interval time threshold, the third result is that the time sequence requirement is met.
A test system, wherein the test system comprises: a receiving section, an acquiring section, and a generating section,

the receiving part is used for receiving the clock signal sent by the adapter after the connection with the adapter is established; wherein the clock signal is used for indicating the transmission time of the instruction;

the acquisition part is used for acquiring a first effective interrupt corresponding to the clock signal, a square wave corresponding to the first effective interrupt and a next effective interrupt corresponding to the first effective interrupt; acquiring a first falling edge and a first rising edge corresponding to the first effective interrupt, acquiring a second falling edge corresponding to the square wave, and acquiring a third falling edge corresponding to the next effective interrupt;

the generating part is used for generating a test result of the instruction time according to the first falling edge, the first rising edge, the second falling edge and the third falling edge.
The test system of claim 8,

the generating part is specifically configured to determine an interrupt time according to the first falling edge and the first rising edge; and determining a transmission time according to the first falling edge and the second falling edge; and determining an interval time according to the second falling edge and the third falling edge; and determining the test result according to the interruption time, the transmission time and the interval time.
The test system of claim 9,

the acquisition part is further used for acquiring a preset interruption time threshold, a preset transmission time threshold and a preset interval time threshold before determining the test result according to the interruption time, the transmission time and the interval time; the preset interrupt time threshold, the preset transmission time threshold and the preset interval time threshold are used for representing the time sequence requirement corresponding to the adapter.
The test system of claim 10,

the acquisition part is specifically used for acquiring a first result according to the interruption time and the preset interruption time threshold; obtaining a second result according to the transmission time and the preset transmission time threshold; obtaining a third result according to the interval time and the preset interval time threshold;

the generating part is specifically configured to determine the test result according to the first result, the second result, and the third result;

the obtaining part is further specifically configured to determine that the first result does not satisfy the timing requirement when the interruption time is greater than or equal to the preset interruption time threshold; when the interruption time is smaller than the preset interruption time threshold, the first result is that the time sequence requirement is met; and when the transmission time is greater than or equal to the preset transmission time threshold, the second result is that the timing requirement is not met; and when the transmission time is less than the preset transmission time threshold, the second result is that the timing sequence requirement is met; and when the interval time is greater than or equal to the preset interval time threshold, the third result is that the timing sequence requirement is not met; and when the interval time is smaller than the preset interval time threshold, the third result is that the time sequence requirement is met.
A test system, wherein the test system comprises a test platelet, a host computer, and an electronic load, wherein the test platelet and the host computer have integrated therein a processor, a memory having stored thereon processor-executable instructions that, when executed, implement the method of any one of claims 1-7.
A computer-readable storage medium, on which a program is stored, for use in a test system, wherein the program, when executed by a processor, implements the method of any one of claims 1-7.