JPH02195448A - Device for tracing instruction - Google Patents

Device for tracing instruction

Info

Publication number
JPH02195448A
JPH02195448A JP1015391A JP1539189A JPH02195448A JP H02195448 A JPH02195448 A JP H02195448A JP 1015391 A JP1015391 A JP 1015391A JP 1539189 A JP1539189 A JP 1539189A JP H02195448 A JPH02195448 A JP H02195448A
Authority
JP
Japan
Prior art keywords
execution
counter
instruction
signal
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1015391A
Other languages
Japanese (ja)
Inventor
Kiyoshi Senba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1015391A priority Critical patent/JPH02195448A/en
Publication of JPH02195448A publication Critical patent/JPH02195448A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To collect data to be analyzed without increasing the execution time of a program to be traced by stopping counting operation in each prescribed interval.
CONSTITUTION: A counter 1 counts up the number of instructions to be executed by counting up the number of pulses of an instruction execution signal 12 for outputting a pulse in each execution of an instruction. The output signal 13 of the counter 1 is compared with the output signal 11 of a register 2 by a comparator 3, and when both the signals coincide with each other, an interruption signal 16 is outputted, a reset signal 15 is generated to reset a flip flop (FF) 4, the counter 1 is cleared by an output 17, and the counting operation of the counter 1 is stopped. A trace memory 5 records an executed instruction address and an executed instruction word at the timing of instruction execution and stops its operation in each resetting of the FF 4, so that trace data recording the execution of plural instructions executed before the time in each interruption interval in order is obtained.
COPYRIGHT: (C)1990,JPO&Japio
JP1015391A 1989-01-25 1989-01-25 Device for tracing instruction Pending JPH02195448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1015391A JPH02195448A (en) 1989-01-25 1989-01-25 Device for tracing instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1015391A JPH02195448A (en) 1989-01-25 1989-01-25 Device for tracing instruction

Publications (1)

Publication Number Publication Date
JPH02195448A true JPH02195448A (en) 1990-08-02

Family

ID=11887438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1015391A Pending JPH02195448A (en) 1989-01-25 1989-01-25 Device for tracing instruction

Country Status (1)

Country Link
JP (1) JPH02195448A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216056A (en) * 2010-04-02 2011-10-27 Mitsubishi Electric Corp Programmable controller and peripheral device thereof
CN111263891A (en) * 2018-09-30 2020-06-09 Oppo广东移动通信有限公司 Instruction time testing method and system and computer storage medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216056A (en) * 2010-04-02 2011-10-27 Mitsubishi Electric Corp Programmable controller and peripheral device thereof
CN111263891A (en) * 2018-09-30 2020-06-09 Oppo广东移动通信有限公司 Instruction time testing method and system and computer storage medium
CN111263891B (en) * 2018-09-30 2022-06-07 Oppo广东移动通信有限公司 Instruction time testing method and system and computer storage medium

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