CN102831092B - USB full-speed device data signal synchronous circuit - Google Patents
USB full-speed device data signal synchronous circuit Download PDFInfo
- Publication number
- CN102831092B CN102831092B CN201110159171.5A CN201110159171A CN102831092B CN 102831092 B CN102831092 B CN 102831092B CN 201110159171 A CN201110159171 A CN 201110159171A CN 102831092 B CN102831092 B CN 102831092B
- Authority
- CN
- China
- Prior art keywords
- latch
- state
- signal
- usb
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Information Transfer Systems (AREA)
Abstract
The invention discloses a kind of USB full-speed device data signal synchronous circuit.With high frequency clock, K state and SE0 condition indicative signal are synchronized, synchronous logic uses two-stage D-latch to eliminate data signal metastable issues, re-uses a D-latch and one two input eliminates, with door, the error pulse signal caused by high frequency clock sampling by mistake by burr on SE0 condition indicative signal.After synchronizing and removing bursts of error, recombinant produces K state, J state and the SE0 condition indicative signal that usb bus data signal internal logic is used.The present invention can make to meet the correctness of signal after the asynchronous data signal of the USB USB device of agreement at full speed is synchronized and ensure that synchronization.
Description
Technical field
The present invention relates to the interface field of PC (PC), particularly relate to a kind of USB full-speed device data signal same
Step circuit.
Background technology
USB (USB (universal serial bus) Universal Serial BUS) interface be the end of the year 1994 by Intel, Compaq, IBM,
Microsoft Deng Duo company combines proposition, is an outside being connected and communicate with for specification computer Yu external equipment
Bus standard.
After within 1994, having delivered USB initial version, the standard extension that USB interface has become as in current computer connects
Mouthful.USB interface transmission speed is fast, full-speed device 12Mbps (12 Gigabits per second), low-speed device 1.5Mbps；Easy to use, support
The plug and play of equipment and hot plug；The advantages such as flexible, independently-powered are connected it addition, also have.USB interface can connect Mus
Mark, keyboard, printer, scanner, photographic head, flash disk, MP3 machine, mobile phone, digital camera, portable hard drive, external smooth floppy drive,
The almost all of external equipments such as USB network card, ADSL Modem, Cable Modem.
USB full-speed device uses the interface of four lines, in addition to two power and grounds, and only two single data holding wires
Transmission for usb bus data.The most whole USB system uses asynchronous transmission means, does not has the biography of clock signal
Defeated.This just requires, when using usb bus data, be first synchronized in the work clock territory of chip internal.Simultaneously as
Sequential on two single data holding wires of USB full-speed device is inconsistent, when synchronizing usb bus data signal, can make to synchronize
After signal distortion, thus insert some error pulse signals.To this end, after synchronous logic, removal mistake to be added
The circuit of pulse signal.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of USB full-speed device data signal synchronous circuit, it is possible to synchronize
The data signal bus of USB full-speed device and ensure the correctness of data signal bus.
For solving above-mentioned technical problem, the USB full-speed device data signal synchronous circuit of the present invention, including:
SE0 condition indicative signal synchronous circuit, including the first D-latch being sequentially connected in series, the second D-latch and the 3rd D
Latch, the synchronizing clock signals of the input end of clock input chip operation clock zone of described three D-latch, the 2nd D latches
The data output end of device and the 3rd D-latch is connected with the input of door with one two input respectively, the SE0 state before synchronization
Indication signal inputs the data input pin to the first D-latch, and the SE0 state after two inputs are Tong Bu with the output of the outfan of door refers to
Show signal；
K state or J condition indicative signal synchronous circuit, including the 4 d latch being sequentially connected in series, the 5th D-latch and
6th D-latch, the synchronizing clock signals of the input end of clock input chip operation clock zone of described three D-latch, synchronize
Front K state or J condition indicative signal input the data input pin to 4 d latch, the data output end of the 6th D-latch
K state after output synchronization or J condition indicative signal.
Use the synchronous circuit of the present invention, it is possible to eliminate the metastable issues of usb bus data signal, filter out mistake arteries and veins
Rush signal；Ensure K state indication signal or J condition indicative signal, consistent with SE0 condition indicative signal sequential；Therefore, the present invention
The asynchronous data signal meeting the USB USB device of agreement at full speed can either be made to be synchronized, ensure that again the USB after synchronization is total
The correctness of line data signal.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the data signal bus oscillogram of USB full-speed device transmission；
Fig. 2 is SE0 condition indicative signal synchronous circuit schematic diagram；
Fig. 3 is K state indication signal synchronous circuit schematic diagram.
Detailed description of the invention
Two single data holding wires of USB full-speed device are for four data signal bus of transmission, as it is shown in figure 1, D+ and D-
Value be 10 expression J states, 01 represent K state, 00 represent SE0 state, 11 represent SE1 states.Wherein, J state representation is
Data 1, what K state represented is data 0；And SE0 state representation is the end signal of a usb data bag, SE1 state is one
Individual disarmed state, and use not in USB data transmission.
USB full-speed device is when transmitting a usb data bag, always by K state, and constantly sends K state table
Registration is according to the bit stream of 0 or J state representation data 1, until data signal terminates, sends SE0 state representation current USB number
According to end-of-packet.Therefore, the most only synchronize K state and SE0 condition indicative signal, after synchronization, if bus
Condition data signal is not in K state and SE0 state, and that is just it is believed that be in J state.
SE0 condition indicative signal synchronous circuit is as in figure 2 it is shown, be made up of with door three D-latch and one two input, D
Latch D1 and D-latch D2 is used for synchronizing SE0 condition indicative signal, and the concatenation of two-stage D-latch latches and ensure that signal is not
Have metastable issues.But, during due to transmission usb data bag, data signal is always K state or J state, and
The sequential of two single data holding wire D+ and D-of USB full-speed device is not completely the same, and the time of signal upset can not keep
In the same time, so jagged existence certainly on the SE0 condition indicative signal before synchronization, this burr is input to synchronize electricity
Lu Hou, it is possible to can be sampled by D-latch D1 and D-latch D2, thus produce an error pulse signal.In synchronous circuit
D-latch D3 and two input is used for removing this error pulse signal with door AND1 exactly, from circuit, only latches at D
In the case of the output of device D2 and D3 is all 1, final SE0 condition indicative signal is just 1.Such circuit ensure that to be locked at D
In the output of storage D2, the SE0 condition indicative signal being only more than a synchronised clock clk cycle can be considered as just really to have
The SE0 condition indicative signal of effect, thus filtered the error pulse signal caused by burr.
Shown in Figure 3, owing to will not jagged occur in K state indication signal, K state indication signal synchronous circuit by
Three D-latch are constituted, and D-latch D4 and D5 is for synchronizing the metastable issues in K state indication signal clear signal, same
Time after D-latch D6 is used for ensureing synchronizing, K state indication signal is consistent with the sequential of SE0 condition indicative signal.
From above analysis it will be seen that due to error pulse signal to be removed, synchronous circuit can filter out a synchronization
The signal width of clock cycle；The problem brought is, even for normal SE0 condition indicative signal, through synchronous circuit
Process after, also can be less than original data signal width.This width reduced, at a synchronised clock of synchronous circuit
About clk cycle.The most described synchronous circuit require synchronised clock CLK frequency will more than the four of frequency data signal times,
After so synchronizing, SE0 condition indicative signal only can lose 1/4th of a data signal bus bit wide, thereby ensure that with
Step circuit can normal sample K state and SE0 condition indicative signal, also can guarantee that data signal is not after whole synchronous circuit
Serious distortion.
Described synchronised clock CLK, for high frequency clock, i.e. chip operation clock zone.
After synchronous circuit, obtain SE0 condition indicative signal and K state instruction at chip operation clock zone and believed
Number, and in the case of SE0 state and K state indication signal are all zero, now J condition indicative signal is " 1 ".So, chip
The state in all usb bus data signals in inside chip work clock territory required for internal circuit just creates.
Above by detailed description of the invention, the present invention is described in detail, but being embodied as when, ability
Field technique personnel can do suitable adjustment and change, the such as frequency of synchronous circuit synchronised clock, D under the principles of the present invention
The number of latch, synchronizes K state and still synchronizes J state etc..These adjustment also should be regarded as protection scope of the present invention.
Claims (3)
1. a USB full-speed device data signal synchronous circuit, it is characterised in that including:
SE0 condition indicative signal synchronous circuit, latches including the first D-latch being sequentially connected in series, the second D-latch and the 3rd D
Device, described three D-latch input end of clock input chip operation clock zone synchronizing clock signals, the second D-latch and
The data output end of the 3rd D-latch is connected with the input of door with one two input respectively, the SE0 state instruction before synchronization
Signal inputs the data input pin to the first D-latch, the SE0 state instruction letter after two inputs are Tong Bu with the output of the outfan of door
Number；
K state or J condition indicative signal synchronous circuit, including the 4 d latch being sequentially connected in series, the 5th D-latch and the 6th D
Latch, the synchronizing clock signals of the input end of clock input chip operation clock zone of described three D-latch, the K before synchronization
State or J condition indicative signal input the data input pin to 4 d latch, the data output end output of the 6th D-latch
K state after synchronization or J condition indicative signal.
2. USB full-speed device data signal synchronous circuit as claimed in claim 1, it is characterised in that: described synchronised clock is believed
Number more than frequency is usb bus frequency data signal four times.
3. USB full-speed device data signal synchronous circuit as claimed in claim 1, it is characterised in that: after synchronization process,
Recombinant produces the K state of usb bus data signal, J state and SE0 state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110159171.5A CN102831092B (en) | 2011-06-14 | 2011-06-14 | USB full-speed device data signal synchronous circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110159171.5A CN102831092B (en) | 2011-06-14 | 2011-06-14 | USB full-speed device data signal synchronous circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102831092A CN102831092A (en) | 2012-12-19 |
| CN102831092B true CN102831092B (en) | 2016-12-28 |
Family
ID=47334237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110159171.5A Active CN102831092B (en) | 2011-06-14 | 2011-06-14 | USB full-speed device data signal synchronous circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102831092B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0942533A2 (en) * | 1998-03-13 | 1999-09-15 | Texas Instruments Limited | Circuit for Synchronisation |
| CN1917368A (en) * | 2006-09-12 | 2007-02-21 | 北京中星微电子有限公司 | Method and device for removing burrs in signal |
| CN101222222A (en) * | 2007-01-12 | 2008-07-16 | 曹先国 | Signal cleaning circuit |
-
2011
- 2011-06-14 CN CN201110159171.5A patent/CN102831092B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0942533A2 (en) * | 1998-03-13 | 1999-09-15 | Texas Instruments Limited | Circuit for Synchronisation |
| CN1917368A (en) * | 2006-09-12 | 2007-02-21 | 北京中星微电子有限公司 | Method and device for removing burrs in signal |
| CN101222222A (en) * | 2007-01-12 | 2008-07-16 | 曹先国 | Signal cleaning circuit |
Non-Patent Citations (1)
| Title |
|---|
| "面向SOC的可配置AHB接口组件";张頔等;《电子与信息学报》;20080831;第30卷(第8期);第2008-2011页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102831092A (en) | 2012-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102447477B (en) | Real-time conversion transmission method and device of parallel-series data stream for cross asynchronous clock domain | |
| CN202870808U (en) | FPGA realization device of SPI serial port module | |
| EP2587385A1 (en) | Usb key device and method for realizing intelligent card communication using usb interface | |
| CN104020691A (en) | Signal acquisition board suitable for multiple bus protocols and multiple expansion interfaces | |
| CN104639410A (en) | Design method of field bus optical fiber communication interface | |
| JP2008234222A (en) | Usb controller and method of testing usb controller | |
| CN203455835U (en) | Bus triggering backplate applied to PXI (PCI extension for instrumentation) test platform | |
| Sung et al. | USB transceiver with a serial interface engine and FIFO queue for efficient FPGA-to-FPGA communication | |
| Agrawal et al. | The design of high speed UART | |
| CN108156099A (en) | Srio switching system | |
| JP3727213B2 (en) | Synchronous element for converting asynchronous pulse signal to synchronous pulse signal | |
| CN102831092B (en) | USB full-speed device data signal synchronous circuit | |
| CN109358995A (en) | A kind of multifunctional testing backboard and test method | |
| CN107533533A (en) | Communication between integrated circuit | |
| CN213582152U (en) | PCIE signal bit width automatic switching device of desktop and server system | |
| CN203443598U (en) | Star-shaped trigger backboard applied to PXI test platform | |
| CN104331381B (en) | The anti-interference output intent of SPI chips | |
| Sung et al. | Serial interface engine asic with usb physical transceiver based on fpga development board | |
| CN203455834U (en) | Daisy chain triggering backplate applied to PXI (PCI extension for instrumentation) test platform | |
| CN101290607B (en) | Chip debugging interface device | |
| Pham-Thai et al. | A novel multichannel UART design with FPGA-based implementation | |
| CN203825617U (en) | USB (universal serial bus)-based high speed data transmission equipment | |
| CN106027192B (en) | A kind of parallel data synchronous acquisition device | |
| Shin et al. | Verilog synthesis of usb 2.0 full-speed device phy ip | |
| CN104503934A (en) | Extendable serial transmission device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |