CN1131592C - Signal phase discriminating method in state transferring sequential logic - Google Patents
Signal phase discriminating method in state transferring sequential logic Download PDFInfo
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- CN1131592C CN1131592C CN 01142025 CN01142025A CN1131592C CN 1131592 C CN1131592 C CN 1131592C CN 01142025 CN01142025 CN 01142025 CN 01142025 A CN01142025 A CN 01142025A CN 1131592 C CN1131592 C CN 1131592C
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Abstract
The present invention relates to a signal phase discriminating method in state transferring sequential logic, which comprises the following steps that firstly, the time of two square wave impulse sequence signals u1 and u2 with the phase to be discriminated are respectively delayed by Ts to obtain time delay output signals u1' and u2'; the rising edge and the falling edge of the u1 are judged according to the states of u1 and u1' to obtain a signal e1 for representing the variation of the rising edge and the falling edge of u1 by logical operation, and e2 is obtained in a similar way; a group of output signals up' and down' are generated through the logical operation of phase discrimination state transferring according to e1, e2 and the states of up and down of the phase discrimination output signals. The output signals are latched for one time at a time interval of Ts, and the latched signals are final phase discrimination output signals up and down. The method of the present invention has the advantages of simple and clear structure and explicit intermediate signal meaning, and thus, the stability and the reliability of the treatment of phase discrimination are improved.
Description
Technical field:
The present invention relates to a kind of signal phase discriminating method of state transferring sequential logic, this method changes the judgement signal that obtains reflecting the phase error between them according to the rising edge or the trailing edge of two input signals, belongs to communication, automatic control etc.
Technical field.
Background technology:
In communication, household electrical appliances, field such as control automatically, extensively need the phase error between two signals be differentiated, thereby further can realize the Synchronous Processing or the control of signal.It at the international standard number 0070050503 " phase-locked loop: principle, design and use " various traditional phase detecting methods are introduced in the book, comprising a kind of two phase detecting methods that trigger structure, this method has the dual discriminating performance of difference on the frequency and phase difference.The basic principle of sort signal phase detecting method is to utilize two groups of rim detection that trigger logic realization to two input signals, further the rising edge of detected two input signals of foundation or trailing edge change then, adopt combinational logic to realize the phase demodulation state transitions, finally obtain the phase demodulation output signal.
The circuit arrangement of realizing based on above-mentioned two phase detecting methods that trigger structures can produce some small burr pulses in the line when the detection signal edge, the existing effective control signal of these burr pulse signals also has invalid burr impulse disturbances.These burr pulse signals are easy to propagate into output, occur unnecessary glitch noise on the phase demodulation output signal thereby make.And effectively the burr pulse control signal is easy to be subjected to the influence of stray capacitance in the electromagnetic interference of idler Pulse burr and the circuit, finally makes this phase discriminator the phase discrimination signal output of mistake may occur.So this phase detecting method stability and reliability are all poor.
The phase detecting method of two triggering structures is not suitable for designing realization by the electronic design automation software instrument.Because two phase detecting methods that trigger structure have adopted combinational logic fully, and need to rely on the feedback arrangement and the signal lag of arithmetic logic unit to work.Yet the electronic design automation software instrument often has the function of logic optimization, and this function can split merging with combinatorial logic unit again in order to reduce the logic scale of design object.So, when the phase detecting method according to two triggering structures designs on the electronic design automation software instrument, the processing procedure of logic optimization can change the feedback arrangement and the signal lag relation of the combinatorial logic unit in the side circuit, makes the circuit result who finally designs can not correctly realize the function of phase demodulation.
For the needs that digital communication, Digital Control etc. are used, wish in little process chip such as single-chip microcomputer, DSP and CPU, to realize the phase discrimination function of signal, but adopt software algorithm to be not easy to realize traditional two phase detecting methods that trigger structure by software program.This is because two phase detecting method that triggers structure has adopted a lot of combinatorial logic unit, and concern complexity between these logical blocks, if these logic functions and the signal relation between them directly are converted to corresponding software algorithm, the software program that so obtains is certainly will code size huge, debug difficulties, and operational efficiency is low.
Summary of the invention:
The objective of the invention is to propose a kind of signal phase discriminating method of state transferring sequential logic, to eliminate the burr pulse signal, improve the stability and the reliability of signal phase demodulation, avoid the feedback arrangement of combinational logic, be easy to the signal phase discriminating method that adopts software algorithm to realize.
The signal phase discriminating method of the state transferring sequential logic that the present invention proposes may further comprise the steps:
1. to remaining two square-wave pulse sequence signal u1 of phase demodulation and the u2 T that delays time respectively
sTime, output signal u1 ' and u2 ', wherein T obtain delaying time
sIt is the sequential blanking time that phase demodulation is judged;
2. according to above-mentioned the 1st signal u1 that obtains of step and the state of u1 ', above-mentioned input signal u1 is carried out rising edge or trailing edge judgement, obtain a signal e1 who changes in order to rising edge or the trailing edge of characterization signal u1 through logical operation, the effective impulse width of this signal is T
sSignal u2 that above-mentioned the 1st step of foundation obtains and the state of u2 ', above-mentioned input signal u2 is carried out rising edge or trailing edge judgement, obtain a signal e2 who changes in order to rising edge or the trailing edge of characterization signal u2 through logical operation, the effective impulse width of this signal is T
s
3. according to above-mentioned the 2nd signal e1 that obtains of step and the state of e2 and phase demodulation output signal up and down,, produce one group of output signal up ' and down ' through the logical operation of phase demodulation state transitions;
4. output signal up ' that above-mentioned the 3rd step obtains and down ' are every time T
sBe latched once, latch signal is final phase demodulation output signal up and down.
Method of the present invention provides a kind of effective structure and step for realizing the signal phase demodulation.Owing to adopted sequential logic control, this method no longer to rely on the work of burr pulse signal, this has improved the antijamming capability of phase demodulation.Moreover the output of latching of above-mentioned the 4th part phase discrimination signal is carried out under sequencing control, and this has been avoided the burr pulse signal to propagate on the phase demodulation output signal, thereby has reduced the noise of phase demodulation output signal.In addition, this method simple in structure clear, the M signal meaning is clear and definite, and these have all improved the stability and the reliability of phase discrimination processing.
The 4th part of the inventive method latchs the output phase discrimination signal under sequencing control, the phase demodulation output signal enters into the phase demodulation state transitions combinational logic of the 3rd part more then, has constituted the feedback arrangement of state transitions like this.This structure has avoided adopting fully the feedback arrangement of combinational logic formation, makes this method can not be subjected to the influence that logic optimization is handled in the electronic design automation software instrument, is convenient to utilize the electronic design automation software instrument to realize design.
Can design corresponding phase demodulation program according to the principle steps of the inventive method, this program can make little process chip such as single-chip microcomputer, DSP and CPU realize the function of signal phase demodulation, and this program code has simply clearly structure flow process, debugging easily, algorithm is carried out the efficient height.
Description of drawings:
Fig. 1 is the theory diagram of the signal phase discriminating method of state transferring sequential logic of the present invention.
Fig. 2 is the truth table examples of parameters of input signal u1 rising edge decision logic computing.
Fig. 3 is the truth table examples of parameters of input signal u2 rising edge decision logic computing.
Fig. 4 is the truth table examples of parameters of phase demodulation state transitions logical operation among the present invention.
Fig. 5 is each signal waveforms in the signal phase discriminating method of the present invention.
Embodiment:
The theory diagram of the signal phase discriminating method of state transferring sequential logic of the present invention as shown in Figure 1, this flow process is differentiated the phase difference between them according to the rising edge for the treatment of phase demodulation input signal u1 and u2, produces phase demodulation output signal up and down.Entire circuit is worked under the sequential logic control of square-wave pulse clock signal clk, and the cycle of clock signal clk is exactly sequential T blanking time described in the inventive method
s
As shown in Figure 1, input signal u1 and u2 are latched constantly at each rising edge of clock signal clk, and latch output signal u1 ' and u2 ' are respectively the time delayed signals of signal u1 and u2.
Basis signal u1 and u1 ' carry out the computing of u1 rising edge decision logic, embodiments of the invention adopt the truth-table format of Digital Logic to describe this logical operation, Fig. 2 has provided the truth table parameter of u1 rising edge decision logic computing, signal e1 is the output of u1 rising edge decision logic computing, and e1 equals sequential T blanking time with width
sHigh level pulse represent that the rising edge of u1 changes.Basis signal u2 and u2 ' carry out the computing of u2 rising edge decision logic, and Fig. 3 has provided the truth table parameter of u2 rising edge decision logic computing, and signal e2 is the output of u2 rising edge decision logic computing, and e2 equals sequential T blanking time with width
sHigh level pulse represent that the rising edge of u2 changes.
Signal e1 and e2, and, carry out the logical operation of phase demodulation state transitions jointly by phase discrimination signal up and down that output feeds back, Fig. 4 has provided the truth table parameter of phase demodulation state transitions logical operation, output signal up ' and down ' after the logical operation.
In the rising edge moment of clock signal clk, signal up ' is latched output and obtains phase discrimination signal up, and signal down ' is latched output and obtains phase discrimination signal down.Signal up and down are the last phase discrimination signal that obtains of this method.
The signal waveforms of the signal phase discriminating method of state transferring sequential logic described above as shown in Figure 5, signal up and down have expressed two by the phase difference between phase demodulation input signal u1 and the u2 with the negative pulse of certain width.
The inventive method can adopt software algorithm to realize, represent the signal level state with binary code in software, wherein the high level state of signal is represented with data 1, and low level state is represented with data 0.Two is respectively u1 and u2 by phase demodulation input data, and the phase demodulation dateout is up and down, and hypothesis intermediate variable data are u1 ', u2 ', e1, e2, up ' and down '.Concrete algorithm steps is described below:
1. input data u1 and u1 ' calculate data e1 according to following rising edge decision logic formula:
e1＝u1?AND(NOT?u1′)，
Wherein, AND is and logic connective that NOT is non-logic connective.
2. be assignment operation: u1 '=u1.
3. input data u2 and u2 ' calculate data e2 according to following rising edge decision logic formula:
e2＝u2?AND(NOT?u2′)。
4. be assignment operation: u2 '=u2.
5. according to e1, e2 and current data up and down, calculate up ' and down ' according to phase demodulation state transitions logic true value table, Fig. 4 has provided the truth table of phase demodulation state transitions logical operation.
6. do assignment operation and obtain phase demodulation data up and dwon:up=up ', down=down '.
7. return step 1, this algorithm circulates.
The time that above-mentioned algorithm is carried out a cycle calculations equals sequential Ts blanking time described in the inventive method.
This algorithm is realized with software in little process chip, is just made little process chip realize the phase discrimination processing function of signal.
Claims (1)
1, a kind of signal phase discriminating method of state transferring sequential logic is characterized in that this method may further comprise the steps:
(1) to remaining two square-wave pulse sequence signal u1 of phase demodulation and the u2 T that delays time respectively
sTime, output signal u1 ' and u2 ', wherein T obtain delaying time
sIt is the sequential blanking time that phase demodulation is judged;
(2) according to above-mentioned the 1st signal u1 that obtains of step and the state of u1 ', above-mentioned signal u1 is carried out rising edge or trailing edge judgement, obtain a signal e1 who changes in order to rising edge or the trailing edge of characterization signal u1 through logical operation, the effective impulse width of this signal is T
sSignal u2 that above-mentioned the 1st step of foundation obtains and the state of u2 ' carry out rising edge or trailing edge judgement to above-mentioned signal u2, obtain a signal e2 who changes in order to rising edge or the trailing edge of characterization signal u2 through logical operation, and the effective impulse width of this signal is T
s
(3) according to above-mentioned the 2nd signal e1 that obtains of step and the state of e2 and phase demodulation output signal up and down,, produce one group of output signal up ' and down ' through the logical operation of phase demodulation state transitions;
(4) above-mentioned the 3rd output signal up ' that obtains of step and down ' are every time T
sBe latched once, latch signal is final phase demodulation output signal up and down.
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| CN 01142025 CN1131592C (en) | 2001-09-07 | 2001-09-07 | Signal phase discriminating method in state transferring sequential logic |
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| CN 01142025 CN1131592C (en) | 2001-09-07 | 2001-09-07 | Signal phase discriminating method in state transferring sequential logic |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101452012B (en) * | 2007-12-05 | 2011-01-12 | 华硕电脑股份有限公司 | Method for acquiring signal state |
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| CN102364877B (en) * | 2011-11-18 | 2013-08-28 | 中国船舶重工集团公司第七0四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101452012B (en) * | 2007-12-05 | 2011-01-12 | 华硕电脑股份有限公司 | Method for acquiring signal state |
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